[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Switch CallLowering to extended LLTs (PR #208268)
Petar Avramovic via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Jul 10 04:53:03 PDT 2026
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/208268
>From 7b6077110cc93f7d7b8719b97e818332074c86ab Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Wed, 8 Jul 2026 13:59:39 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Switch CallLowering to extended LLTs
Stop using LLT::scalar for argument lowering in AMDGPUCallLowering.
Mostly straightforward, worth noting that some places now require
a bitcast between integer and float.
---
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 63 +-
.../CodeGen/AMDGPU/GlobalISel/add.vni16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 110 +-
.../AMDGPU/GlobalISel/atomic_load_flat.ll | 3 +-
.../AMDGPU/GlobalISel/atomic_load_global.ll | 5 +-
.../AMDGPU/GlobalISel/atomic_load_local_2.ll | 1 +
llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll | 8 +-
.../GlobalISel/clamp-fmed3-const-combine.ll | 12 +-
.../GlobalISel/clamp-minmax-const-combine.ll | 24 +-
.../GlobalISel/combine-fma-add-ext-fma.ll | 18 +-
.../GlobalISel/combine-fma-add-fma-mul.ll | 12 +-
.../AMDGPU/GlobalISel/combine-fma-add-mul.ll | 12 +-
.../GlobalISel/combine-fma-sub-ext-mul.ll | 4 +-
.../GlobalISel/combine-fma-sub-ext-neg-mul.ll | 12 +-
.../AMDGPU/GlobalISel/combine-fma-sub-mul.ll | 18 +-
.../GlobalISel/combine-fma-sub-neg-mul.ll | 16 +-
.../GlobalISel/dropped_debug_info_assert.ll | 71 +-
.../CodeGen/AMDGPU/GlobalISel/dummy-target.ll | 4 +-
.../GlobalISel/dynamic-alloca-uniform.ll | 2 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll | 28 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll | 234 +-
.../CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll | 51 +-
.../CodeGen/AMDGPU/GlobalISel/flat-scratch.ll | 10 +-
.../CodeGen/AMDGPU/GlobalISel/floor.f64.ll | 4 +-
.../GlobalISel/fmed3-min-max-const-combine.ll | 16 +-
.../AMDGPU/GlobalISel/fmin3-fmax3-combine.ll | 2 +-
.../CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll | 6 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll | 28 +-
.../AMDGPU/GlobalISel/function-returns.ll | 104 +-
.../GlobalISel/irtranslator-amdgpu_kernel.ll | 976 ++--
.../GlobalISel/irtranslator-amdgpu_ps.ll | 12 +-
.../GlobalISel/irtranslator-assert-align.ll | 24 +-
.../irtranslator-call-abi-attribute-hints.ll | 52 +-
.../irtranslator-call-implicit-args.ll | 400 +-
.../GlobalISel/irtranslator-call-non-fixed.ll | 10 +-
.../irtranslator-call-return-values.ll | 939 ++--
.../GlobalISel/irtranslator-call-sret.ll | 24 +-
.../AMDGPU/GlobalISel/irtranslator-call.ll | 1852 +++----
.../GlobalISel/irtranslator-function-args.ll | 239 +-
.../GlobalISel/irtranslator-indirect-call.ll | 20 +-
.../GlobalISel/irtranslator-inline-asm.ll | 4 +-
.../GlobalISel/irtranslator-sibling-call.ll | 81 +-
.../GlobalISel/irtranslator-tail-call.ll | 6 +-
...galize-llvm.amdgcn.image.atomic.dim.a16.ll | 516 +-
.../legalize-llvm.amdgcn.image.load.2d.d16.ll | 16 +-
.../legalize-llvm.amdgcn.image.sample.a16.ll | 4660 ++++++++++-------
...galize-llvm.amdgcn.image.sample.g16.a16.ll | 344 +-
.../legalize-llvm.amdgcn.image.sample.g16.ll | 1632 +++---
...legalize-llvm.amdgcn.image.store.2d.d16.ll | 47 +-
.../CodeGen/AMDGPU/GlobalISel/llvm.abs.ll | 157 +-
.../AMDGPU/GlobalISel/llvm.amdgcn.fract.ll | 9 +-
.../llvm.amdgcn.image.gather4.a16.dim.ll | 1441 +++--
.../llvm.amdgcn.image.load.1d.d16.ll | 8 +-
.../llvm.amdgcn.image.sample.cd.g16.ll | 48 +-
.../llvm.amdgcn.image.sample.g16.ll | 236 +-
.../llvm.amdgcn.image.store.2d.d16.ll | 36 +-
.../GlobalISel/llvm.amdgcn.interp.inreg.ll | 4 +-
.../GlobalISel/llvm.amdgcn.intersect_ray.ll | 4 +-
.../llvm.amdgcn.make.buffer.rsrc.ll | 12 +-
...llvm.amdgcn.raw.buffer.store.format.f16.ll | 108 +-
.../llvm.amdgcn.raw.buffer.store.ll | 32 +-
....amdgcn.raw.ptr.buffer.store.format.f16.ll | 102 +-
.../llvm.amdgcn.raw.ptr.buffer.store.ll | 24 +-
.../llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll | 622 +--
.../llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll | 280 +-
.../llvm.amdgcn.raw.tbuffer.store.f16.ll | 646 +--
.../llvm.amdgcn.raw.tbuffer.store.i8.ll | 522 +-
...vm.amdgcn.struct.buffer.load.format.f16.ll | 12 +-
...m.amdgcn.struct.buffer.store.format.f16.ll | 283 +-
...mdgcn.struct.ptr.buffer.load.format.f16.ll | 8 +-
...dgcn.struct.ptr.buffer.store.format.f16.ll | 218 +-
.../GlobalISel/llvm.amdgcn.wqm.demote.ll | 57 +-
.../CodeGen/AMDGPU/GlobalISel/llvm.memset.ll | 2 +-
.../CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll | 6 +-
.../AMDGPU/GlobalISel/regbankselect-call.ll | 4 +-
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 53 +-
.../AMDGPU/GlobalISel/select-to-fmin-fmax.ll | 4 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll | 4 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll | 2 +-
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 53 +-
.../AMDGPU/GlobalISel/store-local.128.ll | 6 +-
.../AMDGPU/GlobalISel/store-local.96.ll | 6 +-
.../AMDGPU/GlobalISel/strict_fma.f16.ll | 24 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll | 8 +-
.../test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll | 36 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll | 4 +-
.../test/CodeGen/AMDGPU/GlobalISel/usubsat.ll | 31 +-
.../abi-attribute-hints-undefined-behavior.ll | 66 +-
.../AMDGPU/addrspacecast-known-non-null.ll | 2 +-
.../CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll | 4 +-
llvm/test/CodeGen/AMDGPU/bitop3.ll | 8 +-
llvm/test/CodeGen/AMDGPU/bitreverse.ll | 2 +-
...ffer-fat-pointers-contents-legalization.ll | 8 +-
.../build-vector-packed-partial-undef.ll | 341 +-
llvm/test/CodeGen/AMDGPU/call-c-function.ll | 6 +-
llvm/test/CodeGen/AMDGPU/call-constant.ll | 78 +-
llvm/test/CodeGen/AMDGPU/call-constexpr.ll | 364 +-
llvm/test/CodeGen/AMDGPU/call-encoding.ll | 4 +-
.../AMDGPU/call-preserved-registers.ll | 83 +-
.../CodeGen/AMDGPU/call-reqd-group-size.ll | 10 +-
llvm/test/CodeGen/AMDGPU/call-skip.ll | 84 +-
.../AMDGPU/commute-compares-scalar-float.ll | 42 +-
.../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 230 +-
.../test/CodeGen/AMDGPU/dynamic_stackalloc.ll | 2 +-
llvm/test/CodeGen/AMDGPU/fcanonicalize.ll | 14 +-
llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll | 144 +-
llvm/test/CodeGen/AMDGPU/fma.f16.ll | 149 +-
.../test/CodeGen/AMDGPU/fmed3-cast-combine.ll | 179 +-
llvm/test/CodeGen/AMDGPU/fmed3.ll | 10 +-
llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll | 477 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll | 45 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 85 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 78 +-
.../AMDGPU/fsub-as-fneg-src-modifier.ll | 226 +-
llvm/test/CodeGen/AMDGPU/indirect-call.ll | 10 +-
.../CodeGen/AMDGPU/integer-mad-patterns.ll | 8 +-
.../CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll | 80 +-
.../isel-amdgpu-cs-chain-preserve-cc.ll | 41 +-
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll | 32 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll | 154 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll | 6 +-
.../AMDGPU/llvm.amdgcn.frexp.exp.f16.ll | 2 +-
.../llvm.amdgcn.image.sample.g16.a16.dim.ll | 291 +-
.../AMDGPU/llvm.amdgcn.image.sample.noret.ll | 48 +-
.../AMDGPU/llvm.amdgcn.interp.inreg.ll | 4 +-
.../AMDGPU/llvm.amdgcn.intersect_ray.ll | 8 +-
.../CodeGen/AMDGPU/llvm.amdgcn.is.private.ll | 8 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll | 2 +-
.../AMDGPU/llvm.amdgcn.s.memrealtime.ll | 2 +-
.../CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll | 4 +-
.../CodeGen/AMDGPU/llvm.amdgcn.writelane.ll | 8 +-
llvm/test/CodeGen/AMDGPU/llvm.frexp.ll | 4 +-
llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll | 108 +-
llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll | 59 +-
.../lower-work-group-id-intrinsics-hsa.ll | 177 +-
.../AMDGPU/lower-work-group-id-intrinsics.ll | 4 +-
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll | 29 +-
llvm/test/CodeGen/AMDGPU/mad-mix.ll | 876 +---
llvm/test/CodeGen/AMDGPU/minimummaximum.ll | 17 +-
llvm/test/CodeGen/AMDGPU/minmax.ll | 85 +-
.../AMDGPU/module-lds-false-sharing.ll | 54 +-
llvm/test/CodeGen/AMDGPU/roundeven.ll | 2 +-
llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll | 9 +-
.../CodeGen/AMDGPU/shrink-add-sub-constant.ll | 8 +-
llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll | 60 +-
llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll | 4 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmax.ll | 6 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmin.ll | 6 +-
.../CodeGen/AMDGPU/vector-reduce-fminimum.ll | 4 +-
.../AMDGPU/workgroup-id-in-arch-sgprs.ll | 4 +-
150 files changed, 11017 insertions(+), 11794 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index ca541c234ba0d..bf94a48f1064c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -36,7 +36,7 @@ static Register extendRegisterMin32(CallLowering::ValueHandler &Handler,
if (VA.getLocVT().getSizeInBits() < 32) {
// 16-bit types are reported as legal for 32-bit registers. We need to
// extend and do a 32-bit copy to avoid the verifier complaining about it.
- return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
+ return Handler.MIRBuilder.buildAnyExt(LLT::integer(32), ValVReg).getReg(0);
}
return Handler.extendRegister(ValVReg, VA);
@@ -73,15 +73,15 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
= static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
if (TRI->isSGPRReg(MRI, PhysReg)) {
LLT Ty = MRI.getType(ExtReg);
- LLT S32 = LLT::scalar(32);
- if (Ty != S32) {
+ LLT I32 = LLT::integer(32);
+ if (Ty != I32 && Ty != LLT::float32()) {
// FIXME: We should probably support readfirstlane intrinsics with all
// legal 32-bit types.
assert(Ty.getSizeInBits() == 32);
if (Ty.isPointer())
- ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0);
+ ExtReg = MIRBuilder.buildPtrToInt(I32, ExtReg).getReg(0);
else
- ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0);
+ ExtReg = MIRBuilder.buildBitcast(I32, ExtReg).getReg(0);
}
auto ToSGPR = MIRBuilder
@@ -123,13 +123,20 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
// 16-bit types are reported as legal for 32-bit registers. We need to
// do a 32-bit copy, and truncate to avoid the verifier complaining
// about it.
- auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
+ auto Copy = MIRBuilder.buildCopy(LLT::integer(32), PhysReg);
// If we have signext/zeroext, it applies to the whole 32-bit register
// before truncation.
auto Extended =
buildExtensionHint(VA, Copy.getReg(0), LLT(VA.getLocVT()));
- MIRBuilder.buildTrunc(ValVReg, Extended);
+ LLT ValTy = MRI.getType(ValVReg);
+ if (ValTy.isInteger()) {
+ MIRBuilder.buildTrunc(ValVReg, Extended);
+ } else {
+ auto Trunc = MIRBuilder.buildTrunc(LLT::integer(ValTy.getSizeInBits()),
+ Extended);
+ MIRBuilder.buildBitcast(ValVReg, Trunc);
+ }
return;
}
@@ -149,18 +156,26 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
// because the inreg attribute information is not preserved in MIR. We could
// use WWM_COPY (or similar instructions) and mark it as foldable to enable
// later optimization passes to eliminate the redundant readfirstlane.
- auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
if (VA.getLocVT().getSizeInBits() < 32) {
+ auto Copy = MIRBuilder.buildCopy(LLT::integer(32), PhysReg);
auto ToSGPR = MIRBuilder
.buildIntrinsic(Intrinsic::amdgcn_readfirstlane,
{MRI.getType(Copy.getReg(0))})
.addReg(Copy.getReg(0));
auto Extended =
buildExtensionHint(VA, ToSGPR.getReg(0), LLT(VA.getLocVT()));
- MIRBuilder.buildTrunc(ValVReg, Extended);
+ LLT ValTy = MRI.getType(ValVReg);
+ if (ValTy.isInteger()) {
+ MIRBuilder.buildTrunc(ValVReg, Extended);
+ } else {
+ auto Trunc = MIRBuilder.buildTrunc(LLT::integer(ValTy.getSizeInBits()),
+ Extended);
+ MIRBuilder.buildBitcast(ValVReg, Trunc);
+ }
return;
}
+ auto Copy = MIRBuilder.buildCopy(MRI.getType(ValVReg), PhysReg);
MIRBuilder.buildIntrinsic(Intrinsic::amdgcn_readfirstlane, ValVReg)
.addReg(Copy.getReg(0));
}
@@ -239,7 +254,7 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
ISD::ArgFlagsTy Flags) override {
MachineFunction &MF = MIRBuilder.getMF();
const LLT PtrTy = LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32);
- const LLT S32 = LLT::scalar(32);
+ const LLT I32 = LLT::integer(32);
if (IsTailCall) {
Offset += FPDiff;
@@ -266,7 +281,7 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
}
}
- auto OffsetReg = MIRBuilder.buildConstant(S32, Offset);
+ auto OffsetReg = MIRBuilder.buildConstant(I32, Offset);
auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
MPO = MachinePointerInfo::getStack(MF, Offset);
@@ -446,7 +461,7 @@ void AMDGPUCallLowering::lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
MFI->getPreloadedReg(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
Register KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
- auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset);
+ auto OffsetReg = B.buildConstant(LLT::integer(64), Offset);
B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
}
@@ -950,7 +965,7 @@ bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
const ArgDescriptor *IncomingArgX = std::get<0>(WorkitemIDX);
const ArgDescriptor *IncomingArgY = std::get<0>(WorkitemIDY);
const ArgDescriptor *IncomingArgZ = std::get<0>(WorkitemIDZ);
- const LLT S32 = LLT::scalar(32);
+ const LLT I32 = LLT::integer(32);
const bool NeedWorkItemIDX = !Info.CB->hasFnAttr("amdgpu-no-workitem-id-x");
const bool NeedWorkItemIDY = !Info.CB->hasFnAttr("amdgpu-no-workitem-id-y");
@@ -962,38 +977,40 @@ bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo.WorkItemIDX &&
NeedWorkItemIDX) {
if (ST.getMaxWorkitemID(MF.getFunction(), 0) != 0) {
- InputReg = MRI.createGenericVirtualRegister(S32);
+ InputReg = MRI.createGenericVirtualRegister(I32);
LI->buildLoadInputValue(InputReg, MIRBuilder, IncomingArgX,
std::get<1>(WorkitemIDX),
std::get<2>(WorkitemIDX));
} else {
- InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0);
+ InputReg = MIRBuilder.buildConstant(I32, 0).getReg(0);
}
}
if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo.WorkItemIDY &&
NeedWorkItemIDY && ST.getMaxWorkitemID(MF.getFunction(), 1) != 0) {
- Register Y = MRI.createGenericVirtualRegister(S32);
+ Register Y = MRI.createGenericVirtualRegister(I32);
LI->buildLoadInputValue(Y, MIRBuilder, IncomingArgY,
std::get<1>(WorkitemIDY), std::get<2>(WorkitemIDY));
- Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0);
- InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y;
+ Y = MIRBuilder.buildShl(I32, Y, MIRBuilder.buildConstant(I32, 10))
+ .getReg(0);
+ InputReg = InputReg ? MIRBuilder.buildOr(I32, InputReg, Y).getReg(0) : Y;
}
if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo.WorkItemIDZ &&
NeedWorkItemIDZ && ST.getMaxWorkitemID(MF.getFunction(), 2) != 0) {
- Register Z = MRI.createGenericVirtualRegister(S32);
+ Register Z = MRI.createGenericVirtualRegister(I32);
LI->buildLoadInputValue(Z, MIRBuilder, IncomingArgZ,
std::get<1>(WorkitemIDZ), std::get<2>(WorkitemIDZ));
- Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0);
- InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z;
+ Z = MIRBuilder.buildShl(I32, Z, MIRBuilder.buildConstant(I32, 20))
+ .getReg(0);
+ InputReg = InputReg ? MIRBuilder.buildOr(I32, InputReg, Z).getReg(0) : Z;
}
if (!InputReg &&
(NeedWorkItemIDX || NeedWorkItemIDY || NeedWorkItemIDZ)) {
- InputReg = MRI.createGenericVirtualRegister(S32);
+ InputReg = MRI.createGenericVirtualRegister(I32);
if (!IncomingArgX && !IncomingArgY && !IncomingArgZ) {
// We're in a situation where the outgoing function requires the workitem
// ID, but the calling function does not have it (e.g a graphics function
@@ -1007,7 +1024,7 @@ bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
IncomingArgX ? *IncomingArgX :
IncomingArgY ? *IncomingArgY : *IncomingArgZ, ~0u);
LI->buildLoadInputValue(InputReg, MIRBuilder, &IncomingArg,
- &AMDGPU::VGPR_32RegClass, S32);
+ &AMDGPU::VGPR_32RegClass, I32);
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
index 3ca37fd6512fb..66589509f5cfb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; FIXME: codegen regression, related to:
; - looking through s16 sgpr to vgpr copy
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index 815fe47e0bb7e..8974dfc913a25 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -2015,92 +2015,36 @@ define <4 x i1> @v_ashr_v4i1(<4 x i1> %value, <4 x i1> %amount) {
}
define amdgpu_ps <4 x i2> @s_ashr_v4i2(<4 x i2> inreg %value, <4 x i2> inreg %amount) {
-; GFX6-LABEL: s_ashr_v4i2:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s4, s4, 3
-; GFX6-NEXT: s_bfe_i32 s0, s0, 0x20000
-; GFX6-NEXT: s_ashr_i32 s0, s0, s4
-; GFX6-NEXT: s_and_b32 s4, s5, 3
-; GFX6-NEXT: s_bfe_i32 s1, s1, 0x20000
-; GFX6-NEXT: s_ashr_i32 s1, s1, s4
-; GFX6-NEXT: s_and_b32 s4, s6, 3
-; GFX6-NEXT: s_bfe_i32 s2, s2, 0x20000
-; GFX6-NEXT: s_ashr_i32 s2, s2, s4
-; GFX6-NEXT: s_and_b32 s4, s7, 3
-; GFX6-NEXT: s_bfe_i32 s3, s3, 0x20000
-; GFX6-NEXT: s_ashr_i32 s3, s3, s4
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_ashr_v4i2:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b32 s0, s0, 14
-; GFX8-NEXT: s_lshl_b32 s1, s1, 14
-; GFX8-NEXT: s_lshl_b32 s2, s2, 14
-; GFX8-NEXT: s_lshl_b32 s3, s3, 14
-; GFX8-NEXT: s_sext_i32_i16 s0, s0
-; GFX8-NEXT: s_sext_i32_i16 s1, s1
-; GFX8-NEXT: s_sext_i32_i16 s2, s2
-; GFX8-NEXT: s_sext_i32_i16 s3, s3
-; GFX8-NEXT: s_and_b32 s4, s4, 3
-; GFX8-NEXT: s_and_b32 s5, s5, 3
-; GFX8-NEXT: s_and_b32 s6, s6, 3
-; GFX8-NEXT: s_and_b32 s7, s7, 3
-; GFX8-NEXT: s_ashr_i32 s3, s3, 14
-; GFX8-NEXT: s_ashr_i32 s2, s2, 14
-; GFX8-NEXT: s_ashr_i32 s1, s1, 14
-; GFX8-NEXT: s_ashr_i32 s0, s0, 14
-; GFX8-NEXT: s_ashr_i32 s3, s3, s7
-; GFX8-NEXT: s_ashr_i32 s2, s2, s6
-; GFX8-NEXT: s_ashr_i32 s1, s1, s5
-; GFX8-NEXT: s_ashr_i32 s0, s0, s4
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: s_ashr_v4i2:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX9-NEXT: v_pk_lshlrev_b16 v0, 14, s0 op_sel_hi:[0,1]
-; GFX9-NEXT: s_and_b32 s0, s5, 3
-; GFX9-NEXT: s_and_b32 s1, s4, 3
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3
-; GFX9-NEXT: v_pk_ashrrev_i16 v0, 14, v0 op_sel_hi:[0,1]
-; GFX9-NEXT: v_pk_lshlrev_b16 v1, 14, s2 op_sel_hi:[0,1]
-; GFX9-NEXT: s_and_b32 s2, s7, 3
-; GFX9-NEXT: s_and_b32 s3, s6, 3
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s1, s0
-; GFX9-NEXT: v_pk_ashrrev_i16 v1, 14, v1 op_sel_hi:[0,1]
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s2
-; GFX9-NEXT: v_pk_ashrrev_i16 v0, s0, v0
-; GFX9-NEXT: v_pk_ashrrev_i16 v1, s2, v1
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: v_readfirstlane_b32 s1, v0
-; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX9-NEXT: v_readfirstlane_b32 s2, v1
-; GFX9-NEXT: v_readfirstlane_b32 s3, v0
-; GFX9-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_ashr_v4i2:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_and_b32 s4, s4, 3
+; GCN-NEXT: s_bfe_i32 s0, s0, 0x20000
+; GCN-NEXT: s_ashr_i32 s0, s0, s4
+; GCN-NEXT: s_and_b32 s4, s5, 3
+; GCN-NEXT: s_bfe_i32 s1, s1, 0x20000
+; GCN-NEXT: s_ashr_i32 s1, s1, s4
+; GCN-NEXT: s_and_b32 s4, s6, 3
+; GCN-NEXT: s_bfe_i32 s2, s2, 0x20000
+; GCN-NEXT: s_ashr_i32 s2, s2, s4
+; GCN-NEXT: s_and_b32 s4, s7, 3
+; GCN-NEXT: s_bfe_i32 s3, s3, 0x20000
+; GCN-NEXT: s_ashr_i32 s3, s3, s4
+; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_ashr_v4i2:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX10PLUS-NEXT: s_and_b32 s1, s4, 3
-; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, 14, s0 op_sel_hi:[0,1]
-; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s2, s3
-; GFX10PLUS-NEXT: s_and_b32 s2, s7, 3
-; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v1, 14, s0 op_sel_hi:[0,1]
-; GFX10PLUS-NEXT: s_and_b32 s0, s5, 3
-; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, 14, v0 op_sel_hi:[0,1]
-; GFX10PLUS-NEXT: s_and_b32 s3, s6, 3
-; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s1, s0
-; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v1, 14, v1 op_sel_hi:[0,1]
-; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s3, s2
-; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, s0, v0
-; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v1, s1, v1
-; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v1
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v2
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: s_and_b32 s4, s4, 3
+; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x20000
+; GFX10PLUS-NEXT: s_and_b32 s5, s5, 3
+; GFX10PLUS-NEXT: s_bfe_i32 s1, s1, 0x20000
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s4
+; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s5
+; GFX10PLUS-NEXT: s_and_b32 s4, s6, 3
+; GFX10PLUS-NEXT: s_bfe_i32 s2, s2, 0x20000
+; GFX10PLUS-NEXT: s_and_b32 s5, s7, 3
+; GFX10PLUS-NEXT: s_bfe_i32 s3, s3, 0x20000
+; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s4
+; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s5
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = ashr <4 x i2> %value, %amount
ret <4 x i2> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
index 4028db557dafc..f64df3a21f86f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; xUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7 %s
+; UNSUPPORTED: true
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
index d877dc567cdca..0c27af015298c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; xUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
-; xUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7 %s
+; UNSUPPORTED: true
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
index a567741dc35fd..6119e1a9bf796 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; UNSUPPORTED: true
; xUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
index 79c87191fb560..fca7a187fa3b6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -o - %s | FileCheck -check-prefix=GFX7 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX10 %s
define amdgpu_ps i32 @s_bswap_i32(i32 inreg %src) {
; GFX7-LABEL: s_bswap_i32:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
index d00c4169fd6e7..84da2f2007d85 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
define float @test_fmed3_f32_known_nnan_ieee_true(float %a) #0 {
; GFX10-LABEL: test_fmed3_f32_known_nnan_ieee_true:
@@ -35,13 +35,13 @@ define half @test_fmed3_f16_known_nnan_ieee_false(half %a) #1 {
; GFX10-LABEL: test_fmed3_f16_known_nnan_ieee_false:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
+; GFX10-NEXT: v_add_f16_e64 v0, v0, v0 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_fmed3_f16_known_nnan_ieee_false:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
+; GFX1170-NEXT: v_add_f16_e64 v0, v0, v0 clamp
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_fmed3_f16_known_nnan_ieee_false:
@@ -61,7 +61,7 @@ define half @test_fmed3_f16_known_nnan_ieee_false(half %a) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
+; GFX12-FAKE16-NEXT: v_add_f16_e64 v0, v0, v0 clamp
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fmul = fmul half %a, 2.0
%fmed = call nnan half @llvm.amdgcn.fmed3.f16(half %fmul, half 0.0, half 1.0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
index 75be830fc8a77..d46d658e8a6b0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
define float @test_min_max_ValK0_K1_f32(float %a) #0 {
; GFX10-LABEL: test_min_max_ValK0_K1_f32:
@@ -65,13 +65,13 @@ define half @test_min_K1max_ValK0_f16(half %a) #2 {
; GFX10-LABEL: test_min_K1max_ValK0_f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
+; GFX10-NEXT: v_add_f16_e64 v0, v0, v0 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_min_K1max_ValK0_f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
+; GFX1170-NEXT: v_add_f16_e64 v0, v0, v0 clamp
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_min_K1max_ValK0_f16:
@@ -91,7 +91,7 @@ define half @test_min_K1max_ValK0_f16(half %a) #2 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
+; GFX12-FAKE16-NEXT: v_add_f16_e64 v0, v0, v0 clamp
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fmul = fmul half %a, 2.0
%maxnum = call half @llvm.maxnum.f16(half %fmul, half 0.0)
@@ -217,13 +217,17 @@ define half @test_max_K0min_ValK1_f16(half %a) #0 {
; GFX10-LABEL: test_max_K0min_ValK1_f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
+; GFX10-NEXT: v_add_f16_e32 v0, v0, v0
+; GFX10-NEXT: v_min_f16_e32 v0, 1.0, v0
+; GFX10-NEXT: v_max_f16_e32 v0, 0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_max_K0min_ValK1_f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
+; GFX1170-NEXT: v_add_f16_e32 v0, v0, v0
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: v_minmax_num_f16 v0, v0, 1.0, 0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_max_K0min_ValK1_f16:
@@ -243,7 +247,9 @@ define half @test_max_K0min_ValK1_f16(half %a) #0 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
+; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, 1.0, 0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fmul = fmul half %a, 2.0
%minnum = call nnan half @llvm.minnum.f16(half %fmul, half 1.0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
index fc6d79c17198c..d9942411f7ccc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
; fold (fadd (fma x, y, (fpext (fmul u, v))), z) -> (fma x, y, (fma (fpext u), (fpext v), z))
define amdgpu_vs float @test_f16_f32_add_fma_ext_mul(float %x, float %y, float %z, half %u, half %v) {
@@ -45,8 +45,9 @@ define amdgpu_vs float @test_f16_f32_add_fma_ext_mul(float %x, float %y, float %
define amdgpu_vs float @test_f16_f32_add_ext_fma_mul(half %x, half %y, float %z, half %u, half %v) {
; GFX9-DENORM-LABEL: test_f16_f32_add_ext_fma_mul:
; GFX9-DENORM: ; %bb.0: ; %.entry
-; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v3, v4, v2 op_sel_hi:[1,1,0]
-; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX9-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
+; GFX9-DENORM-NEXT: v_mac_f16_e32 v3, v0, v1
+; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v3, 1.0, v2 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: test_f16_f32_add_ext_fma_mul:
@@ -118,8 +119,9 @@ define amdgpu_vs float @test_f16_f32_add_fma_ext_mul_rhs(float %x, float %y, flo
define amdgpu_vs float @test_f16_f32_add_ext_fma_mul_rhs(float %x, half %y, half %z, half %u, half %v) {
; GFX9-DENORM-LABEL: test_f16_f32_add_ext_fma_mul_rhs:
; GFX9-DENORM: ; %bb.0: ; %.entry
-; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v3, v4, v0 op_sel_hi:[1,1,0]
-; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v1, v2, v0 op_sel_hi:[1,1,0]
+; GFX9-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
+; GFX9-DENORM-NEXT: v_mac_f16_e32 v3, v1, v2
+; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: test_f16_f32_add_ext_fma_mul_rhs:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
index cf7ba697ea42a..cefd1ac924274 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -fp-contract=fast < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -fp-contract=fast < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-FAKE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -fp-contract=fast < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11-DENORM,GFX11-DENORM-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11-DENORM,GFX11-DENORM-FAKE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11-DENORM,GFX11-DENORM-FAKE16 %s
; fadd (fma a, b, (fmul c, d)), e --> fma a, b, (fma c, d, e)
; fadd e, (fma a, b, (fmul c, d)) --> fma a, b, (fma c, d, e)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
index 3f6e3d81c52ad..55d8c8948ed1c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
define float @test_f32_add_mul(float %x, float %y, float %z) {
; GFX9-LABEL: test_f32_add_mul:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
index e241eca6467c0..5f02f49ca7eba 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
; fold (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z))
define amdgpu_vs float @test_f16_to_f32_sub_ext_mul(half %x, half %y, float %z) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
index 6ad7b48328a3b..b9e0f87bb8dea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
; fold (fsub (fpext (fneg (fmul, x, y))), z) -> (fneg (fma (fpext x), (fpext y), z))
define amdgpu_vs float @test_f16_to_f32_sub_ext_neg_mul(half %x, half %y, float %z) {
@@ -45,12 +45,12 @@ entry:
define amdgpu_vs float @test_f16_to_f32_sub_ext_neg_mul2(float %x, half %y, half %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul2:
; GFX9-DENORM: ; %bb.0: ; %entry
-; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, -v1, -v2, v0 op_sel_hi:[1,1,0]
+; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v1, v2, v0 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v1, -v2, v0 op_sel_hi:[1,1,0]
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v1, v2, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %y, %z
@@ -64,12 +64,12 @@ entry:
define amdgpu_vs float @test_f16_to_f32_sub_neg_ext_mul2(float %x, half %y, half %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul2:
; GFX9-DENORM: ; %bb.0: ; %entry
-; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, -v1, -v2, v0 op_sel_hi:[1,1,0]
+; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v1, v2, v0 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v1, -v2, v0 op_sel_hi:[1,1,0]
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v1, v2, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %y, %z
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
index d170ec4975edf..6fa55794d0053 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -fp-contract=fast < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -fp-contract=fast < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-FAKE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -fp-contract=fast < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-TRUE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -fp-contract=fast < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11-DENORM,GFX11-DENORM-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11-DENORM,GFX11-DENORM-FAKE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11-DENORM,GFX11-DENORM-FAKE16 %s
; fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
; fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
index 161e48ed73487..3a8c93b32d31e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
; fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
define float @test_f32_sub_ext_neg_mul(float %x, float %y, float %z) {
@@ -63,7 +63,7 @@ define half @test_f16_sub_ext_neg_mul(half %x, half %y, half %z) {
; GFX9-CONTRACT-LABEL: test_f16_sub_ext_neg_mul:
; GFX9-CONTRACT: ; %bb.0: ; %entry
; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-CONTRACT-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; GFX9-CONTRACT-NEXT: v_fma_f16 v0, -v0, v1, -v2
; GFX9-CONTRACT-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-DENORM-LABEL: test_f16_sub_ext_neg_mul:
@@ -82,7 +82,7 @@ define half @test_f16_sub_ext_neg_mul(half %x, half %y, half %z) {
; GFX10-CONTRACT-LABEL: test_f16_sub_ext_neg_mul:
; GFX10-CONTRACT: ; %bb.0: ; %entry
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-CONTRACT-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; GFX10-CONTRACT-NEXT: v_fma_f16 v0, -v0, v1, -v2
; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-DENORM-LABEL: test_f16_sub_ext_neg_mul:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
index 5ae665363cb77..dcb56b2c9f50d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=instruction-select -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=instruction-select -o - %s | FileCheck %s
; Make sure there are no assertions on dropped debug info
declare void @callee()
@@ -9,50 +9,45 @@ define amdgpu_kernel void @call_debug_loc() {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2, debug-location !7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1, debug-location !7
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0, debug-location !7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2, debug-location !7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1, debug-location !7
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0, debug-location !7
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16, debug-location !7
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15, debug-location !7
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14, debug-location !7
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11, debug-location !7
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7, debug-location !7
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5, debug-location !7
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_64(p4) = COPY $sgpr8_sgpr9
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, debug-location !7
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sreg_64(p4) = COPY [[COPY8]], debug-location !7
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:sreg_64(p4) = COPY [[COPY7]], debug-location !7
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sreg_64(s64) = COPY [[COPY6]], debug-location !7
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s32) = COPY [[COPY5]], debug-location !7
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s32) = COPY [[COPY4]], debug-location !7
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s32) = COPY [[COPY3]], debug-location !7
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32(s32) = G_IMPLICIT_DEF debug-location !7
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10, debug-location !7
- ; CHECK-NEXT: [[COPY16:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[COPY16]], [[COPY17]](s32), debug-location !7
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[COPY18]], [[SHL]], debug-location !7
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 20, debug-location !7
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[COPY20:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:vgpr(s32) = G_SHL [[COPY19]], [[COPY20]](s32), debug-location !7
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:vgpr_32(s32) = G_OR [[OR]], [[SHL1]], debug-location !7
- ; CHECK-NEXT: [[COPY21:%[0-9]+]]:sgpr_128(<4 x s32>) = COPY $private_rsrc_reg, debug-location !7
- ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>), debug-location !7
- ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4), debug-location !7
- ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4), debug-location !7
- ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY9]](p4), debug-location !7
- ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64), debug-location !7
- ; CHECK-NEXT: $sgpr12 = COPY [[COPY13]](s32), debug-location !7
- ; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32), debug-location !7
- ; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32), debug-location !7
- ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32), debug-location !7
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32), debug-location !7
- ; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee, target-flags(amdgpu-gotprel32-hi) @callee, implicit-def $scc, debug-location !7
- ; CHECK-NEXT: [[COPY22:%[0-9]+]]:sreg_64(p4) = COPY [[SI_PC_ADD_REL_OFFSET]](p4)
- ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec(p0) = S_LOAD_DWORDX2_IMM [[COPY22]](p4), 0, 0, debug-location !7 :: (dereferenceable invariant load (p0) from got, addrspace 4)
- ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]](p0), @callee, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, debug-location !7
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[COPY8]], debug-location !7
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[COPY7]], debug-location !7
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[COPY6]], debug-location !7
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[COPY5]], debug-location !7
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[COPY4]], debug-location !7
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[COPY3]], debug-location !7
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF debug-location !7
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 10, debug-location !7
+ ; CHECK-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY16]], [[COPY1]], implicit $exec, debug-location !7
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 20, debug-location !7
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY17]], [[COPY]], implicit $exec, debug-location !7
+ ; CHECK-NEXT: [[V_OR3_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR3_B32_e64 [[COPY2]], [[V_LSHLREV_B32_e64_]], [[V_LSHLREV_B32_e64_1]], implicit $exec, debug-location !7
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3, debug-location !7
+ ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]], debug-location !7
+ ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]], debug-location !7
+ ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]], debug-location !7
+ ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY9]], debug-location !7
+ ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]], debug-location !7
+ ; CHECK-NEXT: $sgpr12 = COPY [[COPY13]], debug-location !7
+ ; CHECK-NEXT: $sgpr13 = COPY [[COPY14]], debug-location !7
+ ; CHECK-NEXT: $sgpr14 = COPY [[COPY15]], debug-location !7
+ ; CHECK-NEXT: $sgpr15 = COPY [[DEF]], debug-location !7
+ ; CHECK-NEXT: $vgpr31 = COPY [[V_OR3_B32_e64_]], debug-location !7
+ ; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee, target-flags(amdgpu-gotprel32-hi) @callee, implicit-def $scc, debug-location !7
+ ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[SI_PC_ADD_REL_OFFSET]], 0, 0, debug-location !7 :: (dereferenceable invariant load (p0) from got, addrspace 4)
+ ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]], @callee, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, debug-location !7
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, debug-location !7
; CHECK-NEXT: S_ENDPGM 0
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
index a9bfa9041cc79..c6dc9bea3caec 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
@@ -8,8 +8,8 @@ define i16 @vop3p_add_i16(i16 %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i16) = G_ADD [[TRUNC]], [[TRUNC]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ADD]](i16)
; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
index 81eba12f638c0..bc1dd207948c8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
@gv = external addrspace(4) constant i32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
index 37a11c233eedc..2a46b4a150ff2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
@@ -25,25 +25,15 @@ define amdgpu_ps void @s_fabs_f16(half inreg %in, ptr addrspace(1) %out) {
ret void
}
define amdgpu_ps void @s_fabs_f16_salu_use(half inreg %in, i32 inreg %val, ptr addrspace(1) %out) {
-; GFX11-LABEL: s_fabs_f16_salu_use:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX11-NEXT: s_cmp_eq_u32 s1, 0
-; GFX11-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, s0, s1
-; GFX11-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11-NEXT: s_endpgm
-;
-; GFX12-LABEL: s_fabs_f16_salu_use:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX12-NEXT: s_cmp_eq_u32 s1, 0
-; GFX12-NEXT: s_cselect_b32 s0, s0, 0
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_mov_b32_e32 v2, s0
-; GFX12-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NEXT: s_endpgm
+; GCN-LABEL: s_fabs_f16_salu_use:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_and_b32 s0, s0, 0x7fff
+; GCN-NEXT: s_cmp_eq_u32 s1, 0
+; GCN-NEXT: s_cselect_b32 s1, -1, 0
+; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, s0, s1
+; GCN-NEXT: global_store_b16 v[0:1], v2, off
+; GCN-NEXT: s_endpgm
%fabs = call half @llvm.fabs.f16(half %in)
%cond = icmp eq i32 %val, 0
%sel = select i1 %cond, half %fabs, half 0.0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
index 4272cdf1fe067..2109168742131 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
@@ -1,94 +1,53 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel < %s | FileCheck %s --check-prefix=GFX10
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel < %s | FileCheck %s --check-prefix=GFX12
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel -global-isel-abort=2 < %s | FileCheck %s --check-prefix=GFX10
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel -global-isel-abort=2 < %s | FileCheck %s --check-prefix=GFX12
define void @fcmp_f16_uniform(half inreg %a, half inreg %b, ptr %p) {
; GFX10-LABEL: fcmp_f16_uniform:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_f16_e64 s4, s16, s17
; GFX10-NEXT: v_cmp_gt_f16_e64 s5, s16, s17
; GFX10-NEXT: v_cmp_ge_f16_e64 s6, s16, s17
-; GFX10-NEXT: v_cmp_lt_f16_e64 s7, s16, s17
; GFX10-NEXT: v_cmp_le_f16_e64 s8, s16, s17
-; GFX10-NEXT: s_cmp_lg_u32 s4, 0
-; GFX10-NEXT: v_cmp_lg_f16_e64 s9, s16, s17
-; GFX10-NEXT: s_cselect_b32 s4, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s5, 0
-; GFX10-NEXT: v_cmp_o_f16_e64 s10, s16, s17
+; GFX10-NEXT: v_cmp_o_f16_e64 s9, s16, s17
+; GFX10-NEXT: v_cmp_nle_f16_e64 s10, s16, s17
+; GFX10-NEXT: v_cmp_nge_f16_e64 s11, s16, s17
+; GFX10-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX10-NEXT: v_cmp_neq_f16_e64 s12, s16, s17
; GFX10-NEXT: s_cselect_b32 s5, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s6, 0
-; GFX10-NEXT: v_cmp_nlg_f16_e64 s11, s16, s17
+; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX10-NEXT: v_cmp_eq_f16_e64 s4, s16, s17
; GFX10-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s7, 0
-; GFX10-NEXT: v_cmp_nle_f16_e64 s12, s16, s17
-; GFX10-NEXT: s_cselect_b32 s7, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s8, 0
-; GFX10-NEXT: v_cmp_nlt_f16_e64 s13, s16, s17
+; GFX10-NEXT: s_and_b32 s8, s8, exec_lo
; GFX10-NEXT: s_cselect_b32 s8, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s9, 0
-; GFX10-NEXT: v_cmp_nge_f16_e64 s14, s16, s17
+; GFX10-NEXT: s_and_b32 s9, s9, exec_lo
; GFX10-NEXT: s_cselect_b32 s9, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s10, 0
-; GFX10-NEXT: v_cmp_ngt_f16_e64 s15, s16, s17
+; GFX10-NEXT: s_and_b32 s10, s10, exec_lo
+; GFX10-NEXT: v_cmp_lt_f16_e64 s7, s16, s17
; GFX10-NEXT: s_cselect_b32 s10, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s11, 0
-; GFX10-NEXT: v_cmp_neq_f16_e64 s18, s16, s17
+; GFX10-NEXT: s_and_b32 s11, s11, exec_lo
; GFX10-NEXT: s_cselect_b32 s11, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s12, 0
-; GFX10-NEXT: v_cmp_u_f16_e64 s16, s16, s17
+; GFX10-NEXT: s_and_b32 s12, s12, exec_lo
; GFX10-NEXT: s_cselect_b32 s12, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s13, 0
-; GFX10-NEXT: s_cselect_b32 s13, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s14, 0
-; GFX10-NEXT: s_cselect_b32 s14, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s15, 0
-; GFX10-NEXT: s_cselect_b32 s15, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s18, 0
-; GFX10-NEXT: s_cselect_b32 s17, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s16, 0
-; GFX10-NEXT: s_cselect_b32 s16, 1, 0
; GFX10-NEXT: s_cmp_lg_u32 s4, 0
-; GFX10-NEXT: s_cselect_b32 s4, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s5, 0
-; GFX10-NEXT: s_cselect_b32 s5, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s6, 1, 0
+; GFX10-NEXT: v_cmp_lg_f16_e64 s4, s16, s17
+; GFX10-NEXT: s_addc_u32 s5, s5, 0
; GFX10-NEXT: s_cmp_lg_u32 s7, 0
-; GFX10-NEXT: s_cselect_b32 s7, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s8, 0
-; GFX10-NEXT: s_cselect_b32 s8, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s9, 0
-; GFX10-NEXT: s_cselect_b32 s9, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s10, 0
-; GFX10-NEXT: s_cselect_b32 s10, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s11, 0
-; GFX10-NEXT: s_cselect_b32 s11, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s12, 0
-; GFX10-NEXT: s_cselect_b32 s12, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s13, 0
-; GFX10-NEXT: s_cselect_b32 s13, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s14, 0
-; GFX10-NEXT: s_cselect_b32 s14, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s15, 0
-; GFX10-NEXT: s_cselect_b32 s15, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s17, 0
-; GFX10-NEXT: s_cselect_b32 s17, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s16, 0
-; GFX10-NEXT: s_cselect_b32 s16, 1, 0
-; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: s_add_i32 s4, s4, s6
-; GFX10-NEXT: s_add_i32 s4, s4, s7
-; GFX10-NEXT: s_add_i32 s4, s4, s8
-; GFX10-NEXT: s_add_i32 s4, s4, s9
-; GFX10-NEXT: s_add_i32 s4, s4, s10
-; GFX10-NEXT: s_add_i32 s4, s4, s11
-; GFX10-NEXT: s_add_i32 s4, s4, s12
-; GFX10-NEXT: s_add_i32 s4, s4, s13
-; GFX10-NEXT: s_add_i32 s4, s4, s14
-; GFX10-NEXT: s_add_i32 s4, s4, s15
-; GFX10-NEXT: s_add_i32 s4, s4, s17
-; GFX10-NEXT: s_add_i32 s4, s4, s16
+; GFX10-NEXT: v_cmp_nlg_f16_e64 s7, s16, s17
+; GFX10-NEXT: s_addc_u32 s5, s5, s6
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: v_cmp_nlt_f16_e64 s4, s16, s17
+; GFX10-NEXT: s_addc_u32 s5, s5, s8
+; GFX10-NEXT: s_cmp_lg_u32 s7, 0
+; GFX10-NEXT: v_cmp_ngt_f16_e64 s6, s16, s17
+; GFX10-NEXT: s_addc_u32 s5, s5, s9
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: v_cmp_u_f16_e64 s4, s16, s17
+; GFX10-NEXT: s_addc_u32 s5, s5, s10
+; GFX10-NEXT: s_cmp_lg_u32 s6, 0
+; GFX10-NEXT: s_addc_u32 s5, s5, s11
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: s_addc_u32 s4, s5, s12
; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: flat_store_dword v[0:1], v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
@@ -102,88 +61,54 @@ define void @fcmp_f16_uniform(half inreg %a, half inreg %b, ptr %p) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_cmp_eq_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s2, 1, 0
-; GFX12-NEXT: s_cmp_gt_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s3, 1, 0
-; GFX12-NEXT: s_cmp_ge_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s4, 1, 0
+; GFX12-NEXT: s_cselect_b32 s2, -1, 0
; GFX12-NEXT: s_cmp_lt_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s5, 1, 0
-; GFX12-NEXT: s_cmp_le_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s6, 1, 0
+; GFX12-NEXT: s_cselect_b32 s3, -1, 0
; GFX12-NEXT: s_cmp_lg_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s7, 1, 0
-; GFX12-NEXT: s_cmp_o_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s8, 1, 0
+; GFX12-NEXT: s_cselect_b32 s4, -1, 0
; GFX12-NEXT: s_cmp_nlg_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s9, 1, 0
-; GFX12-NEXT: s_cmp_nle_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s10, 1, 0
+; GFX12-NEXT: s_cselect_b32 s5, -1, 0
; GFX12-NEXT: s_cmp_nlt_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s11, 1, 0
-; GFX12-NEXT: s_cmp_nge_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s12, 1, 0
+; GFX12-NEXT: s_cselect_b32 s6, -1, 0
; GFX12-NEXT: s_cmp_ngt_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s13, 1, 0
-; GFX12-NEXT: s_cmp_neq_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s14, 1, 0
+; GFX12-NEXT: s_cselect_b32 s7, -1, 0
; GFX12-NEXT: s_cmp_u_f16 s0, s1
-; GFX12-NEXT: s_cselect_b32 s0, 1, 0
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_cmp_lg_u32 s2, 0
-; GFX12-NEXT: s_cselect_b32 s1, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s3, 0
-; GFX12-NEXT: s_cselect_b32 s2, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s4, 0
-; GFX12-NEXT: s_cselect_b32 s3, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s5, 0
-; GFX12-NEXT: s_cselect_b32 s4, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s6, 0
-; GFX12-NEXT: s_cselect_b32 s5, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s7, 0
-; GFX12-NEXT: s_cselect_b32 s6, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s8, 0
-; GFX12-NEXT: s_cselect_b32 s7, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s9, 0
-; GFX12-NEXT: s_cselect_b32 s8, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s10, 0
+; GFX12-NEXT: s_cselect_b32 s8, -1, 0
+; GFX12-NEXT: s_cmp_gt_f16 s0, s1
; GFX12-NEXT: s_cselect_b32 s9, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s11, 0
+; GFX12-NEXT: s_cmp_ge_f16 s0, s1
; GFX12-NEXT: s_cselect_b32 s10, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s12, 0
+; GFX12-NEXT: s_cmp_le_f16 s0, s1
; GFX12-NEXT: s_cselect_b32 s11, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s13, 0
+; GFX12-NEXT: s_cmp_o_f16 s0, s1
; GFX12-NEXT: s_cselect_b32 s12, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s14, 0
+; GFX12-NEXT: s_cmp_nle_f16 s0, s1
; GFX12-NEXT: s_cselect_b32 s13, 1, 0
-; GFX12-NEXT: s_cmp_lg_u32 s0, 0
+; GFX12-NEXT: s_cmp_nge_f16 s0, s1
+; GFX12-NEXT: s_cselect_b32 s14, 1, 0
+; GFX12-NEXT: s_cmp_neq_f16 s0, s1
; GFX12-NEXT: s_cselect_b32 s0, 1, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s2
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s3
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s4
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s5
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s6
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s7
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s8
+; GFX12-NEXT: s_cmp_lg_u32 s2, 0
+; GFX12-NEXT: s_add_co_ci_u32 s1, s9, 0
+; GFX12-NEXT: s_cmp_lg_u32 s3, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s9
+; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s10
+; GFX12-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s10
+; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s11
+; GFX12-NEXT: s_cmp_lg_u32 s5, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s11
+; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s12
+; GFX12-NEXT: s_cmp_lg_u32 s6, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s12
+; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s13
+; GFX12-NEXT: s_cmp_lg_u32 s7, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s1, s1, s13
+; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s14
+; GFX12-NEXT: s_cmp_lg_u32 s8, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s0, s1, s0
+; GFX12-NEXT: s_add_co_ci_u32 s0, s1, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: flat_store_b32 v[0:1], v2
@@ -238,41 +163,34 @@ define void @fcmp_f16_divergent(half %a, half %b, ptr %p) {
; GFX10-LABEL: fcmp_f16_divergent:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
+; GFX10-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
+; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v5, vcc_lo
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
+; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
+; GFX10-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
+; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v5, vcc_lo
+; GFX10-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
+; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v5, vcc_lo
; GFX10-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v1, v4, v6, v7
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT: v_add3_u32 v0, v1, v5, v0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v0, vcc_lo, v4, v6, vcc_lo
; GFX10-NEXT: flat_store_dword v[2:3], v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
index 99854cb4e38d7..42f95c713e219 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -3000,23 +3000,23 @@ define half @v_neg_rsq_f16(half %a) {
; GFX89-LABEL: v_neg_rsq_f16:
; GFX89: ; %bb.0:
; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX89-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX89-NEXT: v_rsq_f16_e32 v0, v0
+; GFX89-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_neg_rsq_f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX10-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX10-NEXT: v_rsq_f16_e32 v0, v0
+; GFX10-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_neg_rsq_f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-NEXT: v_rsq_f16_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv contract half -1.0, %sqrt
@@ -3072,26 +3072,23 @@ define { half, half } @v_rsq_f16_multi_use(half %a) {
; GFX89-LABEL: v_rsq_f16_multi_use:
; GFX89: ; %bb.0:
; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT: v_sqrt_f16_e32 v2, v0
-; GFX89-NEXT: v_rsq_f16_e32 v1, v0
-; GFX89-NEXT: v_mov_b32_e32 v0, v2
+; GFX89-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX89-NEXT: v_rcp_f16_e32 v1, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_rsq_f16_multi_use:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_sqrt_f16_e32 v2, v0
-; GFX10-NEXT: v_rsq_f16_e32 v1, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, v2
+; GFX10-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX10-NEXT: v_rcp_f16_e32 v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_rsq_f16_multi_use:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v2, v0
-; GFX11-NEXT: v_rsq_f16_e32 v1, v0
+; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: v_rcp_f16_e32 v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%insert.0 = insertvalue { half, half } poison, half %sqrt, 0
@@ -3400,23 +3397,23 @@ define half @v_neg_rsq_f16_fabs(half %a) {
; GFX89-LABEL: v_neg_rsq_f16_fabs:
; GFX89: ; %bb.0:
; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT: v_sqrt_f16_e64 v0, |v0|
-; GFX89-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX89-NEXT: v_rsq_f16_e64 v0, |v0|
+; GFX89-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_neg_rsq_f16_fabs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_sqrt_f16_e64 v0, |v0|
-; GFX10-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX10-NEXT: v_rsq_f16_e64 v0, |v0|
+; GFX10-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_neg_rsq_f16_fabs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e64 v0, |v0|
+; GFX11-NEXT: v_rsq_f16_e64 v0, |v0|
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%a.fabs = call half @llvm.fabs.f16(half %a)
%sqrt = call contract half @llvm.sqrt.f16(half %a.fabs)
@@ -3461,23 +3458,23 @@ define half @v_neg_rsq_f16_arcp(half %a) {
; GFX89-LABEL: v_neg_rsq_f16_arcp:
; GFX89: ; %bb.0:
; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX89-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX89-NEXT: v_rsq_f16_e32 v0, v0
+; GFX89-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_neg_rsq_f16_arcp:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX10-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX10-NEXT: v_rsq_f16_e32 v0, v0
+; GFX10-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_neg_rsq_f16_arcp:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-NEXT: v_rsq_f16_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv contract arcp half -1.0, %sqrt
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
index f2d20a4726395..94796b8d4ecdf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX942 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+real-true16,-promote-alloca < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX942 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+real-true16,-promote-alloca < %s | FileCheck -check-prefix=GFX12 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX10 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX942 %s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
index 56f4b4404f58c..352c67f3dc269 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefix=GFX78 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefix=GFX78 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefix=GFX78 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefix=GFX78 %s
define double @v_floor_f64_ieee(double %x) {
; GFX6-LABEL: v_floor_f64_ieee:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
index 86237df697d30..e5e7af840f24b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
@@ -2,7 +2,7 @@
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
define float @test_min_max_ValK0_K1_f32(float %a) #0 {
@@ -247,13 +247,14 @@ define half @test_max_K0min_ValK1_f16(half %a) #0 {
; GFX10-LABEL: test_max_K0min_ValK1_f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_med3_f16 v0, v0, 2.0, 4.0
+; GFX10-NEXT: v_min_f16_e32 v0, 4.0, v0
+; GFX10-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_max_K0min_ValK1_f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0
+; GFX1170-NEXT: v_minmax_num_f16 v0, v0, 4.0, 2.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_max_K0min_ValK1_f16:
@@ -273,7 +274,7 @@ define half @test_max_K0min_ValK1_f16(half %a) #0 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0
+; GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, 4.0, 2.0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%minnum = call nnan half @llvm.minnum.f16(half %a, half 4.0)
%fmed = call nnan half @llvm.maxnum.f16(half 2.0, half %minnum)
@@ -291,13 +292,14 @@ define half @test_max_K0min_K1Val_f16(half %a) #1 {
; GFX10-LABEL: test_max_K0min_K1Val_f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_med3_f16 v0, v0, 2.0, 4.0
+; GFX10-NEXT: v_min_f16_e32 v0, 4.0, v0
+; GFX10-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_max_K0min_K1Val_f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0
+; GFX1170-NEXT: v_minmax_num_f16 v0, v0, 4.0, 2.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_max_K0min_K1Val_f16:
@@ -317,7 +319,7 @@ define half @test_max_K0min_K1Val_f16(half %a) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0
+; GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, 4.0, 2.0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%minnum = call nnan half @llvm.minnum.f16(half 4.0, half %a)
%fmed = call nnan half @llvm.maxnum.f16(half 2.0, half %minnum)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
index e035f19ace914..723f0cd7ac316 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
define float @test_fmin3(float %a, float %b, float %c) {
; GFX10-LABEL: test_fmin3:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
index 62326dd4e8b60..85066bd2e492f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
define <2 x half> @v_fmul_v2f16(<2 x half> %a, <2 x half> %b) {
; GFX9-LABEL: v_fmul_v2f16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
index 2ac51b5d2ab1b..f41ff7ba31a5b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
@@ -25,25 +25,15 @@ define amdgpu_ps void @s_fneg_f16(half inreg %in, ptr addrspace(1) %out) {
ret void
}
define amdgpu_ps void @s_fneg_f16_salu_use(half inreg %in, i32 inreg %val, ptr addrspace(1) %out) {
-; GFX11-LABEL: s_fneg_f16_salu_use:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_xor_b32 s0, s0, 0x8000
-; GFX11-NEXT: s_cmp_eq_u32 s1, 0
-; GFX11-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, s0, s1
-; GFX11-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11-NEXT: s_endpgm
-;
-; GFX12-LABEL: s_fneg_f16_salu_use:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_xor_b32 s0, s0, 0x8000
-; GFX12-NEXT: s_cmp_eq_u32 s1, 0
-; GFX12-NEXT: s_cselect_b32 s0, s0, 0
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_mov_b32_e32 v2, s0
-; GFX12-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NEXT: s_endpgm
+; GCN-LABEL: s_fneg_f16_salu_use:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_xor_b32 s0, s0, 0x8000
+; GCN-NEXT: s_cmp_eq_u32 s1, 0
+; GCN-NEXT: s_cselect_b32 s1, -1, 0
+; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, s0, s1
+; GCN-NEXT: global_store_b16 v[0:1], v2, off
+; GCN-NEXT: s_endpgm
%fneg = fneg half %in
%cond = icmp eq i32 %val, 0
%sel = select i1 %cond, half %fneg, half 0.0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
index 1dbe39b47fa14..4403f7ea2eab7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
@@ -152,8 +152,8 @@ define half @f16_func_void() #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f16) = G_LOAD [[DEF]](p1) :: (load (f16) from `ptr addrspace(1) poison`, addrspace 1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](f16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[LOAD]](f16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%val = load half, ptr addrspace(1) poison
ret half %val
@@ -826,38 +826,38 @@ define <16 x i8> @v16i8_func_void() #0 {
; CHECK-NEXT: [[ANYEXT13:%[0-9]+]]:_(i16) = G_ANYEXT [[UV13]](i8)
; CHECK-NEXT: [[ANYEXT14:%[0-9]+]]:_(i16) = G_ANYEXT [[UV14]](i8)
; CHECK-NEXT: [[ANYEXT15:%[0-9]+]]:_(i16) = G_ANYEXT [[UV15]](i8)
- ; CHECK-NEXT: [[ANYEXT16:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT16]](s32)
- ; CHECK-NEXT: [[ANYEXT17:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](i16)
- ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT17]](s32)
- ; CHECK-NEXT: [[ANYEXT18:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](i16)
- ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT18]](s32)
- ; CHECK-NEXT: [[ANYEXT19:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](i16)
- ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT19]](s32)
- ; CHECK-NEXT: [[ANYEXT20:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT4]](i16)
- ; CHECK-NEXT: $vgpr4 = COPY [[ANYEXT20]](s32)
- ; CHECK-NEXT: [[ANYEXT21:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT5]](i16)
- ; CHECK-NEXT: $vgpr5 = COPY [[ANYEXT21]](s32)
- ; CHECK-NEXT: [[ANYEXT22:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT6]](i16)
- ; CHECK-NEXT: $vgpr6 = COPY [[ANYEXT22]](s32)
- ; CHECK-NEXT: [[ANYEXT23:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT7]](i16)
- ; CHECK-NEXT: $vgpr7 = COPY [[ANYEXT23]](s32)
- ; CHECK-NEXT: [[ANYEXT24:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT8]](i16)
- ; CHECK-NEXT: $vgpr8 = COPY [[ANYEXT24]](s32)
- ; CHECK-NEXT: [[ANYEXT25:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT9]](i16)
- ; CHECK-NEXT: $vgpr9 = COPY [[ANYEXT25]](s32)
- ; CHECK-NEXT: [[ANYEXT26:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT10]](i16)
- ; CHECK-NEXT: $vgpr10 = COPY [[ANYEXT26]](s32)
- ; CHECK-NEXT: [[ANYEXT27:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT11]](i16)
- ; CHECK-NEXT: $vgpr11 = COPY [[ANYEXT27]](s32)
- ; CHECK-NEXT: [[ANYEXT28:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT12]](i16)
- ; CHECK-NEXT: $vgpr12 = COPY [[ANYEXT28]](s32)
- ; CHECK-NEXT: [[ANYEXT29:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT13]](i16)
- ; CHECK-NEXT: $vgpr13 = COPY [[ANYEXT29]](s32)
- ; CHECK-NEXT: [[ANYEXT30:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT14]](i16)
- ; CHECK-NEXT: $vgpr14 = COPY [[ANYEXT30]](s32)
- ; CHECK-NEXT: [[ANYEXT31:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT15]](i16)
- ; CHECK-NEXT: $vgpr15 = COPY [[ANYEXT31]](s32)
+ ; CHECK-NEXT: [[ANYEXT16:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT16]](i32)
+ ; CHECK-NEXT: [[ANYEXT17:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT1]](i16)
+ ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT17]](i32)
+ ; CHECK-NEXT: [[ANYEXT18:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT2]](i16)
+ ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT18]](i32)
+ ; CHECK-NEXT: [[ANYEXT19:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT3]](i16)
+ ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT19]](i32)
+ ; CHECK-NEXT: [[ANYEXT20:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT4]](i16)
+ ; CHECK-NEXT: $vgpr4 = COPY [[ANYEXT20]](i32)
+ ; CHECK-NEXT: [[ANYEXT21:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT5]](i16)
+ ; CHECK-NEXT: $vgpr5 = COPY [[ANYEXT21]](i32)
+ ; CHECK-NEXT: [[ANYEXT22:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT6]](i16)
+ ; CHECK-NEXT: $vgpr6 = COPY [[ANYEXT22]](i32)
+ ; CHECK-NEXT: [[ANYEXT23:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT7]](i16)
+ ; CHECK-NEXT: $vgpr7 = COPY [[ANYEXT23]](i32)
+ ; CHECK-NEXT: [[ANYEXT24:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT8]](i16)
+ ; CHECK-NEXT: $vgpr8 = COPY [[ANYEXT24]](i32)
+ ; CHECK-NEXT: [[ANYEXT25:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT9]](i16)
+ ; CHECK-NEXT: $vgpr9 = COPY [[ANYEXT25]](i32)
+ ; CHECK-NEXT: [[ANYEXT26:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT10]](i16)
+ ; CHECK-NEXT: $vgpr10 = COPY [[ANYEXT26]](i32)
+ ; CHECK-NEXT: [[ANYEXT27:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT11]](i16)
+ ; CHECK-NEXT: $vgpr11 = COPY [[ANYEXT27]](i32)
+ ; CHECK-NEXT: [[ANYEXT28:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT12]](i16)
+ ; CHECK-NEXT: $vgpr12 = COPY [[ANYEXT28]](i32)
+ ; CHECK-NEXT: [[ANYEXT29:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT13]](i16)
+ ; CHECK-NEXT: $vgpr13 = COPY [[ANYEXT29]](i32)
+ ; CHECK-NEXT: [[ANYEXT30:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT14]](i16)
+ ; CHECK-NEXT: $vgpr14 = COPY [[ANYEXT30]](i32)
+ ; CHECK-NEXT: [[ANYEXT31:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT15]](i16)
+ ; CHECK-NEXT: $vgpr15 = COPY [[ANYEXT31]](i32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
%ptr = load volatile ptr addrspace(1), ptr addrspace(4) poison
%val = load <16 x i8>, ptr addrspace(1) %ptr
@@ -872,10 +872,10 @@ define <2 x i8> @v2i8_func_void() #0 {
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[LOAD]](<2 x i8>)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[UV]](i8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[UV1]](i8)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT2]](s32)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](i16)
- ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT3]](s32)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT2]](i32)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT1]](i16)
+ ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT3]](i32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
%val = load <2 x i8>, ptr addrspace(1) poison
ret <2 x i8> %val
@@ -890,12 +890,12 @@ define <3 x i8> @v3i8_func_void() #0 {
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[UV]](i8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[UV1]](i8)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i16) = G_ANYEXT [[UV2]](i8)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT3]](s32)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](i16)
- ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT4]](s32)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](i16)
- ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT5]](s32)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT3]](i32)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT1]](i16)
+ ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT4]](i32)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT2]](i16)
+ ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT5]](i32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
%val = load <3 x i8>, ptr addrspace(1) poison
ret <3 x i8> %val
@@ -912,14 +912,14 @@ define <4 x i8> @v4i8_func_void() #0 {
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[UV1]](i8)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i16) = G_ANYEXT [[UV2]](i8)
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i16) = G_ANYEXT [[UV3]](i8)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT4]](s32)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](i16)
- ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT5]](s32)
- ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](i16)
- ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT6]](s32)
- ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](i16)
- ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT7]](s32)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT4]](i32)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT1]](i16)
+ ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT5]](i32)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT2]](i16)
+ ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT6]](i32)
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT3]](i16)
+ ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT7]](i32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
%ptr = load volatile ptr addrspace(1), ptr addrspace(4) poison
%val = load <4 x i8>, ptr addrspace(1) %ptr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
index dbcadce9e6cf1..8a36a68818f5f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
@@ -8,11 +8,11 @@ define amdgpu_kernel void @i8_arg(ptr addrspace(1) nocapture %out, i8 %in) nounw
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i8)
; HSA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -23,11 +23,11 @@ define amdgpu_kernel void @i8_arg(ptr addrspace(1) nocapture %out, i8 %in) nounw
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i8)
; LEGACY-MESA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -43,11 +43,11 @@ define amdgpu_kernel void @i8_zext_arg(ptr addrspace(1) nocapture %out, i8 zeroe
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i8)
; HSA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -58,11 +58,11 @@ define amdgpu_kernel void @i8_zext_arg(ptr addrspace(1) nocapture %out, i8 zeroe
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i8)
; LEGACY-MESA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -78,11 +78,11 @@ define amdgpu_kernel void @i8_sext_arg(ptr addrspace(1) nocapture %out, i8 signe
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD1]](i8)
; HSA-VI-NEXT: G_STORE [[SEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -93,11 +93,11 @@ define amdgpu_kernel void @i8_sext_arg(ptr addrspace(1) nocapture %out, i8 signe
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD1]](i8)
; LEGACY-MESA-VI-NEXT: G_STORE [[SEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -113,11 +113,11 @@ define amdgpu_kernel void @i16_arg(ptr addrspace(1) nocapture %out, i16 %in) nou
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i16) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i16)
; HSA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -128,11 +128,11 @@ define amdgpu_kernel void @i16_arg(ptr addrspace(1) nocapture %out, i16 %in) nou
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i16) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i16)
; LEGACY-MESA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -148,11 +148,11 @@ define amdgpu_kernel void @i16_zext_arg(ptr addrspace(1) nocapture %out, i16 zer
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i16) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i16)
; HSA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -163,11 +163,11 @@ define amdgpu_kernel void @i16_zext_arg(ptr addrspace(1) nocapture %out, i16 zer
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i16) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i16)
; LEGACY-MESA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -183,11 +183,11 @@ define amdgpu_kernel void @i16_sext_arg(ptr addrspace(1) nocapture %out, i16 sig
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i16) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD1]](i16)
; HSA-VI-NEXT: G_STORE [[SEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -198,11 +198,11 @@ define amdgpu_kernel void @i16_sext_arg(ptr addrspace(1) nocapture %out, i16 sig
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i16) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD1]](i16)
; LEGACY-MESA-VI-NEXT: G_STORE [[SEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -218,11 +218,11 @@ define amdgpu_kernel void @i32_arg(ptr addrspace(1) nocapture %out, i32 %in) nou
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -232,11 +232,11 @@ define amdgpu_kernel void @i32_arg(ptr addrspace(1) nocapture %out, i32 %in) nou
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -251,11 +251,11 @@ define amdgpu_kernel void @f32_arg(ptr addrspace(1) nocapture %out, float %in) n
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(f32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (f32) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](f32), [[LOAD]](p1) :: (store (f32) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -265,11 +265,11 @@ define amdgpu_kernel void @f32_arg(ptr addrspace(1) nocapture %out, float %in) n
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(f32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (f32) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](f32), [[LOAD]](p1) :: (store (f32) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -284,11 +284,11 @@ define amdgpu_kernel void @v2i8_arg(ptr addrspace(1) %out, <2 x i8> %in) {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x i8>) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<2 x i8>), [[LOAD]](p1) :: (store (<2 x i8>) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -298,11 +298,11 @@ define amdgpu_kernel void @v2i8_arg(ptr addrspace(1) %out, <2 x i8> %in) {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x i8>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<2 x i8>), [[LOAD]](p1) :: (store (<2 x i8>) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -317,11 +317,11 @@ define amdgpu_kernel void @v2i16_arg(ptr addrspace(1) %out, <2 x i16> %in) {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x i16>) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<2 x i16>), [[LOAD]](p1) :: (store (<2 x i16>) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -331,11 +331,11 @@ define amdgpu_kernel void @v2i16_arg(ptr addrspace(1) %out, <2 x i16> %in) {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x i16>) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<2 x i16>), [[LOAD]](p1) :: (store (<2 x i16>) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -350,11 +350,11 @@ define amdgpu_kernel void @v2i32_arg(ptr addrspace(1) nocapture %out, <2 x i32>
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x i32>) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<2 x i32>), [[LOAD]](p1) :: (store (<2 x i32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -364,11 +364,11 @@ define amdgpu_kernel void @v2i32_arg(ptr addrspace(1) nocapture %out, <2 x i32>
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x i32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<2 x i32>), [[LOAD]](p1) :: (store (<2 x i32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -383,11 +383,11 @@ define amdgpu_kernel void @v2f32_arg(ptr addrspace(1) nocapture %out, <2 x float
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x f32>) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<2 x f32>), [[LOAD]](p1) :: (store (<2 x f32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -397,11 +397,11 @@ define amdgpu_kernel void @v2f32_arg(ptr addrspace(1) nocapture %out, <2 x float
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x f32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<2 x f32>), [[LOAD]](p1) :: (store (<2 x f32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -416,11 +416,11 @@ define amdgpu_kernel void @v3i8_arg(ptr addrspace(1) nocapture %out, <3 x i8> %i
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<3 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<3 x i8>) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<3 x i8>), [[LOAD]](p1) :: (store (<3 x i8>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -430,11 +430,11 @@ define amdgpu_kernel void @v3i8_arg(ptr addrspace(1) nocapture %out, <3 x i8> %i
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<3 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<3 x i8>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<3 x i8>), [[LOAD]](p1) :: (store (<3 x i8>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -449,11 +449,11 @@ define amdgpu_kernel void @v3i16_arg(ptr addrspace(1) nocapture %out, <3 x i16>
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<3 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<3 x i16>) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<3 x i16>), [[LOAD]](p1) :: (store (<3 x i16>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -463,11 +463,11 @@ define amdgpu_kernel void @v3i16_arg(ptr addrspace(1) nocapture %out, <3 x i16>
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<3 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<3 x i16>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<3 x i16>), [[LOAD]](p1) :: (store (<3 x i16>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -482,11 +482,11 @@ define amdgpu_kernel void @v3i32_arg(ptr addrspace(1) nocapture %out, <3 x i32>
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<3 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<3 x i32>) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<3 x i32>), [[LOAD]](p1) :: (store (<3 x i32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -496,11 +496,11 @@ define amdgpu_kernel void @v3i32_arg(ptr addrspace(1) nocapture %out, <3 x i32>
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<3 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<3 x i32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<3 x i32>), [[LOAD]](p1) :: (store (<3 x i32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -515,11 +515,11 @@ define amdgpu_kernel void @v3f32_arg(ptr addrspace(1) nocapture %out, <3 x float
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<3 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<3 x f32>) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<3 x f32>), [[LOAD]](p1) :: (store (<3 x f32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -529,11 +529,11 @@ define amdgpu_kernel void @v3f32_arg(ptr addrspace(1) nocapture %out, <3 x float
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<3 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<3 x f32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<3 x f32>), [[LOAD]](p1) :: (store (<3 x f32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -548,11 +548,11 @@ define amdgpu_kernel void @v4i8_arg(ptr addrspace(1) %out, <4 x i8> %in) {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x i8>) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<4 x i8>), [[LOAD]](p1) :: (store (<4 x i8>) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -562,11 +562,11 @@ define amdgpu_kernel void @v4i8_arg(ptr addrspace(1) %out, <4 x i8> %in) {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x i8>) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<4 x i8>), [[LOAD]](p1) :: (store (<4 x i8>) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -581,11 +581,11 @@ define amdgpu_kernel void @v4i16_arg(ptr addrspace(1) %out, <4 x i16> %in) {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x i16>) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<4 x i16>), [[LOAD]](p1) :: (store (<4 x i16>) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -595,11 +595,11 @@ define amdgpu_kernel void @v4i16_arg(ptr addrspace(1) %out, <4 x i16> %in) {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x i16>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<4 x i16>), [[LOAD]](p1) :: (store (<4 x i16>) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -614,11 +614,11 @@ define amdgpu_kernel void @v4i32_arg(ptr addrspace(1) nocapture %out, <4 x i32>
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x i32>) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<4 x i32>), [[LOAD]](p1) :: (store (<4 x i32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -628,11 +628,11 @@ define amdgpu_kernel void @v4i32_arg(ptr addrspace(1) nocapture %out, <4 x i32>
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x i32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<4 x i32>), [[LOAD]](p1) :: (store (<4 x i32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -647,11 +647,11 @@ define amdgpu_kernel void @v4f32_arg(ptr addrspace(1) nocapture %out, <4 x float
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x f32>) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<4 x f32>), [[LOAD]](p1) :: (store (<4 x f32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -661,11 +661,11 @@ define amdgpu_kernel void @v4f32_arg(ptr addrspace(1) nocapture %out, <4 x float
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x f32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<4 x f32>), [[LOAD]](p1) :: (store (<4 x f32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -680,11 +680,11 @@ define amdgpu_kernel void @v8i8_arg(ptr addrspace(1) %out, <8 x i8> %in) {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<8 x i8>) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<8 x i8>), [[LOAD]](p1) :: (store (<8 x i8>) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -694,11 +694,11 @@ define amdgpu_kernel void @v8i8_arg(ptr addrspace(1) %out, <8 x i8> %in) {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<8 x i8>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<8 x i8>), [[LOAD]](p1) :: (store (<8 x i8>) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -713,11 +713,11 @@ define amdgpu_kernel void @v8i16_arg(ptr addrspace(1) %out, <8 x i16> %in) {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<8 x i16>) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<8 x i16>), [[LOAD]](p1) :: (store (<8 x i16>) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -727,11 +727,11 @@ define amdgpu_kernel void @v8i16_arg(ptr addrspace(1) %out, <8 x i16> %in) {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<8 x i16>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<8 x i16>), [[LOAD]](p1) :: (store (<8 x i16>) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -746,11 +746,11 @@ define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture %out, <8 x i32>
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<8 x i32>) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<8 x i32>), [[LOAD]](p1) :: (store (<8 x i32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -760,11 +760,11 @@ define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture %out, <8 x i32>
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 68
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<8 x i32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<8 x i32>), [[LOAD]](p1) :: (store (<8 x i32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -779,11 +779,11 @@ define amdgpu_kernel void @v8f32_arg(ptr addrspace(1) nocapture %out, <8 x float
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<8 x f32>) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<8 x f32>), [[LOAD]](p1) :: (store (<8 x f32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -793,11 +793,11 @@ define amdgpu_kernel void @v8f32_arg(ptr addrspace(1) nocapture %out, <8 x float
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 68
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<8 x f32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<8 x f32>), [[LOAD]](p1) :: (store (<8 x f32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -812,11 +812,11 @@ define amdgpu_kernel void @v16i8_arg(ptr addrspace(1) %out, <16 x i8> %in) {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x i8>) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<16 x i8>), [[LOAD]](p1) :: (store (<16 x i8>) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -826,11 +826,11 @@ define amdgpu_kernel void @v16i8_arg(ptr addrspace(1) %out, <16 x i8> %in) {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x i8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x i8>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<16 x i8>), [[LOAD]](p1) :: (store (<16 x i8>) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -845,11 +845,11 @@ define amdgpu_kernel void @v16i16_arg(ptr addrspace(1) %out, <16 x i16> %in) {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x i16>) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<16 x i16>), [[LOAD]](p1) :: (store (<16 x i16>) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -859,11 +859,11 @@ define amdgpu_kernel void @v16i16_arg(ptr addrspace(1) %out, <16 x i16> %in) {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 68
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x i16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x i16>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<16 x i16>), [[LOAD]](p1) :: (store (<16 x i16>) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -878,11 +878,11 @@ define amdgpu_kernel void @v16i32_arg(ptr addrspace(1) nocapture %out, <16 x i32
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x i32>) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<16 x i32>), [[LOAD]](p1) :: (store (<16 x i32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -892,11 +892,11 @@ define amdgpu_kernel void @v16i32_arg(ptr addrspace(1) nocapture %out, <16 x i32
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 100
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x i32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<16 x i32>), [[LOAD]](p1) :: (store (<16 x i32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -911,11 +911,11 @@ define amdgpu_kernel void @v16f32_arg(ptr addrspace(1) nocapture %out, <16 x flo
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x f32>) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](<16 x f32>), [[LOAD]](p1) :: (store (<16 x f32>) into %ir.out, align 4, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -925,11 +925,11 @@ define amdgpu_kernel void @v16f32_arg(ptr addrspace(1) nocapture %out, <16 x flo
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 100
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x f32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x f32>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](<16 x f32>), [[LOAD]](p1) :: (store (<16 x f32>) into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -944,11 +944,11 @@ define amdgpu_kernel void @kernel_arg_i64(ptr addrspace(1) %out, i64 %a) nounwin
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i64) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](i64), [[LOAD]](p1) :: (store (i64) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -958,11 +958,11 @@ define amdgpu_kernel void @kernel_arg_i64(ptr addrspace(1) %out, i64 %a) nounwin
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i64) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](i64), [[LOAD]](p1) :: (store (i64) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -976,11 +976,11 @@ define amdgpu_kernel void @f64_kernel_arg(ptr addrspace(1) %out, double %in) {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(f64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (f64) from constant-pool, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](f64), [[LOAD]](p1) :: (store (f64) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -990,11 +990,11 @@ define amdgpu_kernel void @f64_kernel_arg(ptr addrspace(1) %out, double %in) {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(f64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (f64) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](f64), [[LOAD]](p1) :: (store (f64) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -1009,11 +1009,11 @@ define amdgpu_kernel void @i1_arg(ptr addrspace(1) %out, i1 %x) nounwind {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD1]](i1), [[LOAD]](p1) :: (store (i1) into %ir.out, addrspace 1)
; HSA-VI-NEXT: S_ENDPGM 0
@@ -1023,11 +1023,11 @@ define amdgpu_kernel void @i1_arg(ptr addrspace(1) %out, i1 %x) nounwind {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](i1), [[LOAD]](p1) :: (store (i1) into %ir.out, addrspace 1)
; LEGACY-MESA-VI-NEXT: S_ENDPGM 0
@@ -1041,11 +1041,11 @@ define amdgpu_kernel void @i1_arg_zext_i32(ptr addrspace(1) %out, i1 %x) nounwin
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i1)
; HSA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1056,11 +1056,11 @@ define amdgpu_kernel void @i1_arg_zext_i32(ptr addrspace(1) %out, i1 %x) nounwin
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i1)
; LEGACY-MESA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1076,11 +1076,11 @@ define amdgpu_kernel void @i1_arg_zext_i64(ptr addrspace(1) %out, i1 %x) nounwin
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[LOAD1]](i1)
; HSA-VI-NEXT: G_STORE [[ZEXT]](i64), [[LOAD]](p1) :: (store (i64) into %ir.out, addrspace 1)
@@ -1091,11 +1091,11 @@ define amdgpu_kernel void @i1_arg_zext_i64(ptr addrspace(1) %out, i1 %x) nounwin
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[LOAD1]](i1)
; LEGACY-MESA-VI-NEXT: G_STORE [[ZEXT]](i64), [[LOAD]](p1) :: (store (i64) into %ir.out, addrspace 1)
@@ -1111,11 +1111,11 @@ define amdgpu_kernel void @i1_arg_sext_i32(ptr addrspace(1) %out, i1 %x) nounwin
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD1]](i1)
; HSA-VI-NEXT: G_STORE [[SEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1126,11 +1126,11 @@ define amdgpu_kernel void @i1_arg_sext_i32(ptr addrspace(1) %out, i1 %x) nounwin
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD1]](i1)
; LEGACY-MESA-VI-NEXT: G_STORE [[SEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1146,11 +1146,11 @@ define amdgpu_kernel void @i1_arg_sext_i64(ptr addrspace(1) %out, i1 %x) nounwin
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 8, addrspace 4)
; HSA-VI-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[LOAD1]](i1)
; HSA-VI-NEXT: G_STORE [[SEXT]](i64), [[LOAD]](p1) :: (store (i64) into %ir.out, addrspace 1)
@@ -1161,11 +1161,11 @@ define amdgpu_kernel void @i1_arg_sext_i64(ptr addrspace(1) %out, i1 %x) nounwin
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i1) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[LOAD1]](i1)
; LEGACY-MESA-VI-NEXT: G_STORE [[SEXT]](i64), [[LOAD]](p1) :: (store (i64) into %ir.out, addrspace 1)
@@ -1183,8 +1183,8 @@ define amdgpu_kernel void @empty_struct_arg({} %arg0, i32 %arg1) nounwind {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; HSA-VI-NEXT: G_STORE [[LOAD]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1)
@@ -1195,8 +1195,8 @@ define amdgpu_kernel void @empty_struct_arg({} %arg0, i32 %arg1) nounwind {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1)
@@ -1211,8 +1211,8 @@ define amdgpu_kernel void @empty_array_arg([0 x i8] %arg0, i32 %arg1) nounwind {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; HSA-VI-NEXT: G_STORE [[LOAD]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1)
@@ -1223,8 +1223,8 @@ define amdgpu_kernel void @empty_array_arg([0 x i8] %arg0, i32 %arg1) nounwind {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1)
@@ -1247,20 +1247,20 @@ define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8 %pad,
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i64) from constant-pool, addrspace 4)
- ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; HSA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; HSA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; HSA-VI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; HSA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](i64)
; HSA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 8, addrspace 4)
- ; HSA-VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; HSA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](s64)
+ ; HSA-VI-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; HSA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](i64)
; HSA-VI-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD4]](p4) :: (dereferenceable invariant load (i64) from constant-pool, addrspace 4)
; HSA-VI-NEXT: [[C5:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; HSA-VI-NEXT: G_STORE [[LOAD]](i32), [[C5]](p1) :: (volatile store (i32) into `ptr addrspace(1) null`, addrspace 1)
@@ -1275,20 +1275,20 @@ define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8 %pad,
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i64) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 60
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 60
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 68
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD4]](p4) :: (dereferenceable invariant load (i64) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[C5:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](i32), [[C5]](p1) :: (volatile store (i32) into `ptr addrspace(1) null`, addrspace 1)
@@ -1315,20 +1315,20 @@ define amdgpu_kernel void @pointer_in_struct_argument({ptr addrspace(3), ptr add
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p3) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (p1) from constant-pool, addrspace 4)
- ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; HSA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; HSA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; HSA-VI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; HSA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](i64)
; HSA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (p3) from constant-pool, align 8, addrspace 4)
- ; HSA-VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; HSA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](s64)
+ ; HSA-VI-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; HSA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](i64)
; HSA-VI-NEXT: [[LOAD4:%[0-9]+]]:_(p1234) = G_LOAD [[PTR_ADD4]](p4) :: (dereferenceable invariant load (p1234) from constant-pool, addrspace 4)
; HSA-VI-NEXT: [[C5:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; HSA-VI-NEXT: G_STORE [[LOAD]](p3), [[C5]](p1) :: (volatile store (p3) into `ptr addrspace(1) null`, addrspace 1)
@@ -1343,20 +1343,20 @@ define amdgpu_kernel void @pointer_in_struct_argument({ptr addrspace(3), ptr add
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p3) from constant-pool, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i8) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 60
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 60
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (p3) from constant-pool, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 68
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD4:%[0-9]+]]:_(p1234) = G_LOAD [[PTR_ADD4]](p4) :: (dereferenceable invariant load (p1234) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[C5:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](p3), [[C5]](p1) :: (volatile store (p3) into `ptr addrspace(1) null`, addrspace 1)
@@ -1385,17 +1385,17 @@ define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0,
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i64) from constant-pool, align 4, addrspace 4)
- ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 13
- ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 13
+ ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; HSA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 1, addrspace 4)
- ; HSA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
- ; HSA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; HSA-VI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 17
+ ; HSA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](i64)
; HSA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (i64) from constant-pool, align 1, addrspace 4)
; HSA-VI-NEXT: [[C4:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; HSA-VI-NEXT: G_STORE [[LOAD]](i32), [[C4]](p1) :: (volatile store (i32) into `ptr addrspace(1) null`, addrspace 1)
@@ -1409,17 +1409,17 @@ define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0,
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i64) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 49
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 1, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 53
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 53
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (i64) from constant-pool, align 1, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[C4:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](i32), [[C4]](p1) :: (volatile store (i32) into `ptr addrspace(1) null`, addrspace 1)
@@ -1463,11 +1463,11 @@ define amdgpu_kernel void @byref_constant_i8_arg(ptr addrspace(1) nocapture %out
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i8) from %ir.in.byref, addrspace 4)
; HSA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i8)
; HSA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1478,11 +1478,11 @@ define amdgpu_kernel void @byref_constant_i8_arg(ptr addrspace(1) nocapture %out
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i8) from %ir.in.byref, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i8)
; LEGACY-MESA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1499,11 +1499,11 @@ define amdgpu_kernel void @byref_constant_i16_arg(ptr addrspace(1) nocapture %ou
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i16) from %ir.in.byref, addrspace 4)
; HSA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i16)
; HSA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1514,11 +1514,11 @@ define amdgpu_kernel void @byref_constant_i16_arg(ptr addrspace(1) nocapture %ou
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i16) from %ir.in.byref, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD1]](i16)
; LEGACY-MESA-VI-NEXT: G_STORE [[ZEXT]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1535,13 +1535,13 @@ define amdgpu_kernel void @byref_constant_i32_arg(ptr addrspace(1) nocapture %ou
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
; HSA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i32) from %ir.in.byref, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD2]](i32), [[LOAD]](p1) :: (volatile store (i32) into %ir.out, addrspace 1)
@@ -1553,13 +1553,13 @@ define amdgpu_kernel void @byref_constant_i32_arg(ptr addrspace(1) nocapture %ou
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 16, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i32) from %ir.in.byref, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD2]](i32), [[LOAD]](p1) :: (volatile store (i32) into %ir.out, addrspace 1)
@@ -1577,13 +1577,13 @@ define amdgpu_kernel void @byref_constant_v4i32_arg(ptr addrspace(1) nocapture %
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(<4 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x i32>) from %ir.in.byref, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD2]](<4 x i32>), [[LOAD]](p1) :: (volatile store (<4 x i32>) into %ir.out, align 4, addrspace 1)
@@ -1595,13 +1595,13 @@ define amdgpu_kernel void @byref_constant_v4i32_arg(ptr addrspace(1) nocapture %
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 68
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(<4 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<4 x i32>) from %ir.in.byref, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD2]](<4 x i32>), [[LOAD]](p1) :: (volatile store (<4 x i32>) into %ir.out, align 4, addrspace 1)
@@ -1619,13 +1619,13 @@ define amdgpu_kernel void @byref_align_constant_i32_arg(ptr addrspace(1) nocaptu
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 256
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 260
- ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 256
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 260
+ ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
; HSA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i32) from %ir.in.byref, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD2]](i32), [[LOAD]](p1) :: (volatile store (i32) into %ir.out, addrspace 1)
@@ -1637,13 +1637,13 @@ define amdgpu_kernel void @byref_align_constant_i32_arg(ptr addrspace(1) nocaptu
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 292
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 296
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 292
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 296
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 8, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i32) from %ir.in.byref, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD2]](i32), [[LOAD]](p1) :: (volatile store (i32) into %ir.out, addrspace 1)
@@ -1661,13 +1661,13 @@ define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(ptr addrspace
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 128
- ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 128
+ ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(<16 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x i32>) from %ir.in.byref, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD2]](<16 x i32>), [[LOAD]](p1) :: (volatile store (<16 x i32>) into %ir.out, align 4, addrspace 1)
@@ -1679,13 +1679,13 @@ define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(ptr addrspace
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 164
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 100
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 164
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(<16 x i32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<16 x i32>) from %ir.in.byref, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD2]](<16 x i32>), [[LOAD]](p1) :: (volatile store (<16 x i32>) into %ir.out, align 4, addrspace 1)
@@ -1704,11 +1704,11 @@ define amdgpu_kernel void @byref_global_i32_arg(ptr addrspace(1) nocapture %out,
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p1) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p1) :: (dereferenceable "amdgpu-noclobber" load (i32) from %ir.in.byref, addrspace 1)
; HSA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1719,11 +1719,11 @@ define amdgpu_kernel void @byref_global_i32_arg(ptr addrspace(1) nocapture %out,
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p1) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p1) :: (dereferenceable "amdgpu-noclobber" load (i32) from %ir.in.byref, addrspace 1)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1739,11 +1739,11 @@ define amdgpu_kernel void @byref_flat_i32_arg(ptr addrspace(1) nocapture %out, p
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p0) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p0) :: (dereferenceable load (i32) from %ir.in.byref)
; HSA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1754,11 +1754,11 @@ define amdgpu_kernel void @byref_flat_i32_arg(ptr addrspace(1) nocapture %out, p
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p0) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p0) :: (dereferenceable load (i32) from %ir.in.byref)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1774,11 +1774,11 @@ define amdgpu_kernel void @byref_constant_32bit_i32_arg(ptr addrspace(1) nocaptu
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p6) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p6) :: (dereferenceable invariant load (i32) from %ir.in.byref, addrspace 6)
; HSA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1789,11 +1789,11 @@ define amdgpu_kernel void @byref_constant_32bit_i32_arg(ptr addrspace(1) nocaptu
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p6) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p6) :: (dereferenceable invariant load (i32) from %ir.in.byref, addrspace 6)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1809,11 +1809,11 @@ define amdgpu_kernel void @byref_unknown_as_i32_arg(ptr addrspace(1) nocapture %
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p999) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p999) :: (dereferenceable load (i32) from %ir.in.byref, addrspace 999)
; HSA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1824,11 +1824,11 @@ define amdgpu_kernel void @byref_unknown_as_i32_arg(ptr addrspace(1) nocapture %
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p999) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p999) :: (dereferenceable load (i32) from %ir.in.byref, addrspace 999)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1845,11 +1845,11 @@ define amdgpu_kernel void @byref_local_i32_arg(ptr addrspace(1) nocapture %out,
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p3) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p3) :: (dereferenceable load (i32) from %ir.in.byref, addrspace 3)
; HSA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1860,11 +1860,11 @@ define amdgpu_kernel void @byref_local_i32_arg(ptr addrspace(1) nocapture %out,
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[ADDRSPACE_CAST:%[0-9]+]]:_(p3) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[ADDRSPACE_CAST]](p3) :: (dereferenceable load (i32) from %ir.in.byref, addrspace 3)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](i32), [[LOAD]](p1) :: (store (i32) into %ir.out, addrspace 1)
@@ -1880,15 +1880,15 @@ define amdgpu_kernel void @multi_byref_constant_i32_arg(ptr addrspace(1) nocaptu
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 16, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; HSA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
+ ; HSA-VI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (i32) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i32) from %ir.in0.byref, addrspace 4)
; HSA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from %ir.in1.byref, addrspace 4)
@@ -1902,15 +1902,15 @@ define amdgpu_kernel void @multi_byref_constant_i32_arg(ptr addrspace(1) nocaptu
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; LEGACY-MESA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](i64)
+ ; LEGACY-MESA-VI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (i32) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (i32) from %ir.in0.byref, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (i32) from %ir.in1.byref, addrspace 4)
@@ -1932,8 +1932,8 @@ define amdgpu_kernel void @byref_constant_i32_arg_offset0(ptr addrspace(4) byref
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from %ir.in.byref, addrspace 4)
; HSA-VI-NEXT: G_STORE [[LOAD]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1)
@@ -1944,8 +1944,8 @@ define amdgpu_kernel void @byref_constant_i32_arg_offset0(ptr addrspace(4) byref
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (i32) from %ir.in.byref, addrspace 4)
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1)
@@ -1961,8 +1961,8 @@ define amdgpu_kernel void @p3i8_arg(ptr addrspace(3) %arg) nounwind {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p3) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i8) = G_CONSTANT i8 9
; HSA-VI-NEXT: G_STORE [[C1]](i8), [[LOAD]](p3) :: (store (i8) into %ir.arg, align 4, addrspace 3)
@@ -1973,8 +1973,8 @@ define amdgpu_kernel void @p3i8_arg(ptr addrspace(3) %arg) nounwind {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p3) from constant-pool, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i8) = G_CONSTANT i8 9
; LEGACY-MESA-VI-NEXT: G_STORE [[C1]](i8), [[LOAD]](p3) :: (store (i8) into %ir.arg, align 4, addrspace 3)
@@ -2013,8 +2013,8 @@ define amdgpu_kernel void @v2p1i8_arg(<2 x ptr addrspace(1)> %arg) nounwind {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x p1>) from constant-pool, addrspace 4)
; HSA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; HSA-VI-NEXT: G_STORE [[LOAD]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) poison`, addrspace 1)
@@ -2025,8 +2025,8 @@ define amdgpu_kernel void @v2p1i8_arg(<2 x ptr addrspace(1)> %arg) nounwind {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x p1>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) poison`, addrspace 1)
@@ -2041,8 +2041,8 @@ define amdgpu_kernel void @v2p3i8_arg(<2 x ptr addrspace(3)> %arg) nounwind {
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x p3>) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; HSA-VI-NEXT: G_STORE [[LOAD]](<2 x p3>), [[DEF]](p1) :: (store (<2 x p3>) into `ptr addrspace(1) poison`, addrspace 1)
@@ -2053,8 +2053,8 @@ define amdgpu_kernel void @v2p3i8_arg(<2 x ptr addrspace(3)> %arg) nounwind {
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x p3>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](<2 x p3>), [[DEF]](p1) :: (store (<2 x p3>) into `ptr addrspace(1) poison`, addrspace 1)
@@ -2069,11 +2069,11 @@ define amdgpu_kernel void @v2p1i8_in_struct_arg({ <2 x ptr addrspace(1)>, <2 x p
; HSA-VI-NEXT: liveins: $sgpr8_sgpr9
; HSA-VI-NEXT: {{ $}}
; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x p1>) from constant-pool, addrspace 4)
- ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x p3>) from constant-pool, align 16, addrspace 4)
; HSA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; HSA-VI-NEXT: G_STORE [[LOAD]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) poison`, addrspace 1)
@@ -2087,11 +2087,11 @@ define amdgpu_kernel void @v2p1i8_in_struct_arg({ <2 x ptr addrspace(1)>, <2 x p
; LEGACY-MESA-VI-NEXT: liveins: $sgpr4_sgpr5
; LEGACY-MESA-VI-NEXT: {{ $}}
; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x p1>) from constant-pool, align 4, addrspace 4)
- ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](i64)
; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x p3>) from constant-pool, align 4, addrspace 4)
; LEGACY-MESA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) poison`, addrspace 1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
index 177b7b00b4ffe..4ba1b18ddf8e1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
@@ -116,9 +116,9 @@ define amdgpu_ps ptr addrspace(3) @sgpr_return_p3i8(ptr addrspace(3) %vgpr) {
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[PTRTOINT]](s32)
- ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY]](p3)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[PTRTOINT]](i32)
+ ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
ret ptr addrspace(3) %vgpr
}
@@ -146,9 +146,9 @@ define amdgpu_ps <2 x i16> @sgpr_return_v2i16(<2 x i16> %vgpr) {
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x i16>)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32)
- ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x i16>)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](i32)
+ ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
ret <2 x i16> %vgpr
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
index ac4d2123cc951..a9820d9b823cf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
@@ -25,7 +25,7 @@ define void @call_result_align_1() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -45,7 +45,7 @@ define void @call_result_align_1() {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
@@ -56,7 +56,7 @@ define void @call_result_align_1() {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @returns_ptr, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr0
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -74,7 +74,7 @@ define void @call_result_align_8() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -94,7 +94,7 @@ define void @call_result_align_8() {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
@@ -105,7 +105,7 @@ define void @call_result_align_8() {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @returns_ptr, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr0
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -124,7 +124,7 @@ define void @declaration_result_align_8() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -144,7 +144,7 @@ define void @declaration_result_align_8() {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
@@ -155,7 +155,7 @@ define void @declaration_result_align_8() {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @returns_ptr_align8, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr0
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -174,7 +174,7 @@ define ptr addrspace(1) @tail_call_assert_align() {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -192,7 +192,7 @@ define ptr addrspace(1) @tail_call_assert_align() {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
@@ -203,7 +203,7 @@ define ptr addrspace(1) @tail_call_assert_align() {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: SI_TCRETURN [[GV]](p0), @returns_ptr_align8, 0, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
entry:
%call = tail call ptr addrspace(1) @returns_ptr_align8()
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
index 1bf2a589cb597..dafb1364f9c34 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
@@ -68,15 +68,15 @@ define amdgpu_kernel void @kernel_call_no_workgroup_ids() {
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY9]], [[C]](s64)
; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY11]], [[SHL]]
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY12]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY11]], [[SHL]]
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY13]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY14]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY7]](p4)
@@ -84,7 +84,7 @@ define amdgpu_kernel void @kernel_call_no_workgroup_ids() {
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY10]](s64)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @extern, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -107,20 +107,20 @@ define amdgpu_kernel void @kernel_call_no_other_sgprs() {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY4]], [[C]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[SHL]]
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY6]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY5]], [[SHL]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY7]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY8]](<4 x s32>)
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @extern, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr8_sgpr9, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -173,7 +173,7 @@ define void @func_call_no_workgroup_ids() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
@@ -186,7 +186,7 @@ define void @func_call_no_workgroup_ids() {
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(p4) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY12]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY6]](p4)
@@ -194,7 +194,7 @@ define void @func_call_no_workgroup_ids() {
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY8]](p4)
; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY9]](s64)
; CHECK-NEXT: $sgpr15 = COPY [[COPY10]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY11]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY11]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @extern, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -207,19 +207,19 @@ define void @func_call_no_other_sgprs() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr15, $vgpr31, $sgpr8_sgpr9
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @extern
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p4) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY6]](<4 x s32>)
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY3]](p4)
; CHECK-NEXT: $sgpr15 = COPY [[COPY4]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY5]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY5]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @extern, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr8_sgpr9, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
index c110909ab2cfd..ea108eec2ed1e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
@@ -37,15 +37,15 @@ define amdgpu_kernel void @test_call_external_void_func_i32([17 x i8]) #0 {
; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX900-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX900-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; GFX900-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GFX900-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX900-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX900-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; GFX900-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX900-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; GFX900-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GFX900-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX900-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; GFX900-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GFX900-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX900-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX900-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -57,7 +57,7 @@ define amdgpu_kernel void @test_call_external_void_func_i32([17 x i8]) #0 {
; GFX900-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX900-NEXT: S_ENDPGM 0
@@ -90,15 +90,15 @@ define amdgpu_kernel void @test_call_external_void_func_i32([17 x i8]) #0 {
; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX908-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX908-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; GFX908-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GFX908-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX908-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX908-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; GFX908-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX908-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; GFX908-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GFX908-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX908-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; GFX908-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GFX908-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX908-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX908-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -110,7 +110,7 @@ define amdgpu_kernel void @test_call_external_void_func_i32([17 x i8]) #0 {
; GFX908-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX908-NEXT: S_ENDPGM 0
@@ -123,7 +123,7 @@ define void @test_func_call_external_void_func_i32() #0 {
; GFX900: bb.1 (%ir-block.0):
; GFX900-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GFX900-NEXT: {{ $}}
- ; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GFX900-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GFX900-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GFX900-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -143,7 +143,7 @@ define void @test_func_call_external_void_func_i32() #0 {
; GFX900-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GFX900-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GFX900-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
@@ -155,7 +155,7 @@ define void @test_func_call_external_void_func_i32() #0 {
; GFX900-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX900-NEXT: SI_RETURN
@@ -164,7 +164,7 @@ define void @test_func_call_external_void_func_i32() #0 {
; GFX908: bb.1 (%ir-block.0):
; GFX908-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GFX908-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GFX908-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GFX908-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -184,7 +184,7 @@ define void @test_func_call_external_void_func_i32() #0 {
; GFX908-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GFX908-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GFX908-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
@@ -196,7 +196,7 @@ define void @test_func_call_external_void_func_i32() #0 {
; GFX908-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX908-NEXT: SI_RETURN
@@ -236,19 +236,19 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX900-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX900-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; GFX900-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GFX900-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX900-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX900-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; GFX900-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX900-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; GFX900-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GFX900-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX900-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; GFX900-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GFX900-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32), [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32), [[UV18:%[0-9]+]]:_(i32), [[UV19:%[0-9]+]]:_(i32), [[UV20:%[0-9]+]]:_(i32), [[UV21:%[0-9]+]]:_(i32), [[UV22:%[0-9]+]]:_(i32), [[UV23:%[0-9]+]]:_(i32), [[UV24:%[0-9]+]]:_(i32), [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32), [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x i32>)
; GFX900-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; GFX900-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX900-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)
+ ; GFX900-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX900-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](i32)
; GFX900-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD1]](p5) :: (store (i32) into stack, align 16, addrspace 5)
; GFX900-NEXT: $vgpr0 = COPY [[UV]](i32)
; GFX900-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -291,7 +291,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 4, implicit-def $scc
; GFX900-NEXT: S_ENDPGM 0
@@ -325,19 +325,19 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX908-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX908-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; GFX908-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GFX908-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX908-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX908-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; GFX908-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX908-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; GFX908-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GFX908-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX908-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; GFX908-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GFX908-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32), [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32), [[UV18:%[0-9]+]]:_(i32), [[UV19:%[0-9]+]]:_(i32), [[UV20:%[0-9]+]]:_(i32), [[UV21:%[0-9]+]]:_(i32), [[UV22:%[0-9]+]]:_(i32), [[UV23:%[0-9]+]]:_(i32), [[UV24:%[0-9]+]]:_(i32), [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32), [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x i32>)
; GFX908-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; GFX908-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX908-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)
+ ; GFX908-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX908-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](i32)
; GFX908-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD1]](p5) :: (store (i32) into stack, align 16, addrspace 5)
; GFX908-NEXT: $vgpr0 = COPY [[UV]](i32)
; GFX908-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -380,7 +380,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 4, implicit-def $scc
; GFX908-NEXT: S_ENDPGM 0
@@ -393,7 +393,7 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900: bb.1 (%ir-block.1):
; GFX900-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GFX900-NEXT: {{ $}}
- ; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GFX900-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GFX900-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GFX900-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -402,56 +402,56 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
; GFX900-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GFX900-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
- ; GFX900-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX900-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX900-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX900-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX900-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC]](i16)
- ; GFX900-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX900-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX900-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX900-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX900-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC2]](i16)
- ; GFX900-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX900-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX900-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX900-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX900-NEXT: [[TRUNC5:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC4]](i16)
- ; GFX900-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX900-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
+ ; GFX900-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX900-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
; GFX900-NEXT: [[TRUNC7:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC6]](i16)
- ; GFX900-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX900-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](s32)
+ ; GFX900-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX900-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
; GFX900-NEXT: [[TRUNC9:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC8]](i16)
- ; GFX900-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX900-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](s32)
+ ; GFX900-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX900-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
; GFX900-NEXT: [[TRUNC11:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC10]](i16)
- ; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX900-NEXT: [[TRUNC12:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](s32)
+ ; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX900-NEXT: [[TRUNC12:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
; GFX900-NEXT: [[TRUNC13:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC12]](i16)
- ; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX900-NEXT: [[TRUNC14:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](s32)
+ ; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX900-NEXT: [[TRUNC14:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
; GFX900-NEXT: [[TRUNC15:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC14]](i16)
- ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX900-NEXT: [[TRUNC16:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](s32)
+ ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX900-NEXT: [[TRUNC16:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
; GFX900-NEXT: [[TRUNC17:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC16]](i16)
- ; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr9
- ; GFX900-NEXT: [[TRUNC18:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](s32)
+ ; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr9
+ ; GFX900-NEXT: [[TRUNC18:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
; GFX900-NEXT: [[TRUNC19:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC18]](i16)
- ; GFX900-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr10
- ; GFX900-NEXT: [[TRUNC20:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](s32)
+ ; GFX900-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr10
+ ; GFX900-NEXT: [[TRUNC20:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
; GFX900-NEXT: [[TRUNC21:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC20]](i16)
- ; GFX900-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr11
- ; GFX900-NEXT: [[TRUNC22:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](s32)
+ ; GFX900-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr11
+ ; GFX900-NEXT: [[TRUNC22:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
; GFX900-NEXT: [[TRUNC23:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC22]](i16)
- ; GFX900-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr12
- ; GFX900-NEXT: [[TRUNC24:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](s32)
+ ; GFX900-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr12
+ ; GFX900-NEXT: [[TRUNC24:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](i32)
; GFX900-NEXT: [[TRUNC25:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC24]](i16)
- ; GFX900-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr13
- ; GFX900-NEXT: [[TRUNC26:%[0-9]+]]:_(i16) = G_TRUNC [[COPY22]](s32)
+ ; GFX900-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr13
+ ; GFX900-NEXT: [[TRUNC26:%[0-9]+]]:_(i16) = G_TRUNC [[COPY22]](i32)
; GFX900-NEXT: [[TRUNC27:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC26]](i16)
- ; GFX900-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr14
- ; GFX900-NEXT: [[TRUNC28:%[0-9]+]]:_(i16) = G_TRUNC [[COPY23]](s32)
+ ; GFX900-NEXT: [[COPY23:%[0-9]+]]:_(i32) = COPY $vgpr14
+ ; GFX900-NEXT: [[TRUNC28:%[0-9]+]]:_(i16) = G_TRUNC [[COPY23]](i32)
; GFX900-NEXT: [[TRUNC29:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC28]](i16)
- ; GFX900-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr15
- ; GFX900-NEXT: [[TRUNC30:%[0-9]+]]:_(i16) = G_TRUNC [[COPY24]](s32)
+ ; GFX900-NEXT: [[COPY24:%[0-9]+]]:_(i32) = COPY $vgpr15
+ ; GFX900-NEXT: [[TRUNC30:%[0-9]+]]:_(i16) = G_TRUNC [[COPY24]](i32)
; GFX900-NEXT: [[TRUNC31:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC30]](i16)
- ; GFX900-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr16
- ; GFX900-NEXT: [[TRUNC32:%[0-9]+]]:_(i16) = G_TRUNC [[COPY25]](s32)
+ ; GFX900-NEXT: [[COPY25:%[0-9]+]]:_(i32) = COPY $vgpr16
+ ; GFX900-NEXT: [[TRUNC32:%[0-9]+]]:_(i16) = G_TRUNC [[COPY25]](i32)
; GFX900-NEXT: [[TRUNC33:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC32]](i16)
; GFX900-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; GFX900-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32)
@@ -465,11 +465,11 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX900-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX900-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; GFX900-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[COPY34:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GFX900-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32), [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32), [[UV18:%[0-9]+]]:_(i32), [[UV19:%[0-9]+]]:_(i32), [[UV20:%[0-9]+]]:_(i32), [[UV21:%[0-9]+]]:_(i32), [[UV22:%[0-9]+]]:_(i32), [[UV23:%[0-9]+]]:_(i32), [[UV24:%[0-9]+]]:_(i32), [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32), [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x i32>)
; GFX900-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; GFX900-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX900-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C1]](s32)
+ ; GFX900-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX900-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C1]](i32)
; GFX900-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD]](p5) :: (store (i32) into stack, align 16, addrspace 5)
; GFX900-NEXT: $vgpr0 = COPY [[UV]](i32)
; GFX900-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -512,7 +512,7 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900-NEXT: $sgpr13 = COPY [[COPY31]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY32]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[COPY33]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[COPY34]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[COPY34]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 4, implicit-def $scc
; GFX900-NEXT: SI_RETURN
@@ -521,7 +521,7 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908: bb.1 (%ir-block.1):
; GFX908-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GFX908-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GFX908-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GFX908-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -530,56 +530,56 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
; GFX908-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GFX908-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
- ; GFX908-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX908-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX908-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX908-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX908-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC]](i16)
- ; GFX908-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX908-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX908-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX908-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX908-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC2]](i16)
- ; GFX908-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX908-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX908-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX908-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX908-NEXT: [[TRUNC5:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC4]](i16)
- ; GFX908-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX908-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
+ ; GFX908-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX908-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
; GFX908-NEXT: [[TRUNC7:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC6]](i16)
- ; GFX908-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX908-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](s32)
+ ; GFX908-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX908-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
; GFX908-NEXT: [[TRUNC9:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC8]](i16)
- ; GFX908-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX908-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](s32)
+ ; GFX908-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX908-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
; GFX908-NEXT: [[TRUNC11:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC10]](i16)
- ; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX908-NEXT: [[TRUNC12:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](s32)
+ ; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX908-NEXT: [[TRUNC12:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
; GFX908-NEXT: [[TRUNC13:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC12]](i16)
- ; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX908-NEXT: [[TRUNC14:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](s32)
+ ; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX908-NEXT: [[TRUNC14:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
; GFX908-NEXT: [[TRUNC15:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC14]](i16)
- ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX908-NEXT: [[TRUNC16:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](s32)
+ ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX908-NEXT: [[TRUNC16:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
; GFX908-NEXT: [[TRUNC17:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC16]](i16)
- ; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr9
- ; GFX908-NEXT: [[TRUNC18:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](s32)
+ ; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr9
+ ; GFX908-NEXT: [[TRUNC18:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
; GFX908-NEXT: [[TRUNC19:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC18]](i16)
- ; GFX908-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr10
- ; GFX908-NEXT: [[TRUNC20:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](s32)
+ ; GFX908-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr10
+ ; GFX908-NEXT: [[TRUNC20:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
; GFX908-NEXT: [[TRUNC21:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC20]](i16)
- ; GFX908-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr11
- ; GFX908-NEXT: [[TRUNC22:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](s32)
+ ; GFX908-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr11
+ ; GFX908-NEXT: [[TRUNC22:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
; GFX908-NEXT: [[TRUNC23:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC22]](i16)
- ; GFX908-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr12
- ; GFX908-NEXT: [[TRUNC24:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](s32)
+ ; GFX908-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr12
+ ; GFX908-NEXT: [[TRUNC24:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](i32)
; GFX908-NEXT: [[TRUNC25:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC24]](i16)
- ; GFX908-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr13
- ; GFX908-NEXT: [[TRUNC26:%[0-9]+]]:_(i16) = G_TRUNC [[COPY22]](s32)
+ ; GFX908-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr13
+ ; GFX908-NEXT: [[TRUNC26:%[0-9]+]]:_(i16) = G_TRUNC [[COPY22]](i32)
; GFX908-NEXT: [[TRUNC27:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC26]](i16)
- ; GFX908-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr14
- ; GFX908-NEXT: [[TRUNC28:%[0-9]+]]:_(i16) = G_TRUNC [[COPY23]](s32)
+ ; GFX908-NEXT: [[COPY23:%[0-9]+]]:_(i32) = COPY $vgpr14
+ ; GFX908-NEXT: [[TRUNC28:%[0-9]+]]:_(i16) = G_TRUNC [[COPY23]](i32)
; GFX908-NEXT: [[TRUNC29:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC28]](i16)
- ; GFX908-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr15
- ; GFX908-NEXT: [[TRUNC30:%[0-9]+]]:_(i16) = G_TRUNC [[COPY24]](s32)
+ ; GFX908-NEXT: [[COPY24:%[0-9]+]]:_(i32) = COPY $vgpr15
+ ; GFX908-NEXT: [[TRUNC30:%[0-9]+]]:_(i16) = G_TRUNC [[COPY24]](i32)
; GFX908-NEXT: [[TRUNC31:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC30]](i16)
- ; GFX908-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr16
- ; GFX908-NEXT: [[TRUNC32:%[0-9]+]]:_(i16) = G_TRUNC [[COPY25]](s32)
+ ; GFX908-NEXT: [[COPY25:%[0-9]+]]:_(i32) = COPY $vgpr16
+ ; GFX908-NEXT: [[TRUNC32:%[0-9]+]]:_(i16) = G_TRUNC [[COPY25]](i32)
; GFX908-NEXT: [[TRUNC33:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC32]](i16)
; GFX908-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; GFX908-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32)
@@ -593,11 +593,11 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX908-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX908-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; GFX908-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[COPY34:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GFX908-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32), [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32), [[UV18:%[0-9]+]]:_(i32), [[UV19:%[0-9]+]]:_(i32), [[UV20:%[0-9]+]]:_(i32), [[UV21:%[0-9]+]]:_(i32), [[UV22:%[0-9]+]]:_(i32), [[UV23:%[0-9]+]]:_(i32), [[UV24:%[0-9]+]]:_(i32), [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32), [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x i32>)
; GFX908-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; GFX908-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX908-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C1]](s32)
+ ; GFX908-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX908-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C1]](i32)
; GFX908-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD]](p5) :: (store (i32) into stack, align 16, addrspace 5)
; GFX908-NEXT: $vgpr0 = COPY [[UV]](i32)
; GFX908-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -640,7 +640,7 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908-NEXT: $sgpr13 = COPY [[COPY31]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY32]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[COPY33]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[COPY34]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[COPY34]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 4, implicit-def $scc
; GFX908-NEXT: SI_RETURN
@@ -674,7 +674,7 @@ define amdgpu_kernel void @test_only_workitem_id_x() #0 !reqd_work_group_size !0
; GFX900-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX900-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; GFX900-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
; GFX900-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX900-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY16]](<4 x s32>)
@@ -686,7 +686,7 @@ define amdgpu_kernel void @test_only_workitem_id_x() #0 !reqd_work_group_size !0
; GFX900-NEXT: $sgpr13 = COPY [[COPY13]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY14]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[COPY15]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[COPY15]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX900-NEXT: S_ENDPGM 0
@@ -716,7 +716,7 @@ define amdgpu_kernel void @test_only_workitem_id_x() #0 !reqd_work_group_size !0
; GFX908-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX908-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; GFX908-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
; GFX908-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX908-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY16]](<4 x s32>)
@@ -728,7 +728,7 @@ define amdgpu_kernel void @test_only_workitem_id_x() #0 !reqd_work_group_size !0
; GFX908-NEXT: $sgpr13 = COPY [[COPY13]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY14]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[COPY15]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[COPY15]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX908-NEXT: S_ENDPGM 0
@@ -762,11 +762,11 @@ define amdgpu_kernel void @test_only_workitem_id_y() #0 !reqd_work_group_size !1
; GFX900-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX900-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; GFX900-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX900-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX900-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C3]](s32)
- ; GFX900-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
+ ; GFX900-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY15]], [[C3]](i32)
+ ; GFX900-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL]]
; GFX900-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX900-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY16]](<4 x s32>)
@@ -778,7 +778,7 @@ define amdgpu_kernel void @test_only_workitem_id_y() #0 !reqd_work_group_size !1
; GFX900-NEXT: $sgpr13 = COPY [[COPY13]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY14]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[OR]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[OR]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX900-NEXT: S_ENDPGM 0
@@ -808,11 +808,11 @@ define amdgpu_kernel void @test_only_workitem_id_y() #0 !reqd_work_group_size !1
; GFX908-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX908-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; GFX908-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX908-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX908-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C3]](s32)
- ; GFX908-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
+ ; GFX908-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY15]], [[C3]](i32)
+ ; GFX908-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL]]
; GFX908-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX908-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY16]](<4 x s32>)
@@ -824,7 +824,7 @@ define amdgpu_kernel void @test_only_workitem_id_y() #0 !reqd_work_group_size !1
; GFX908-NEXT: $sgpr13 = COPY [[COPY13]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY14]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[OR]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[OR]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX908-NEXT: S_ENDPGM 0
@@ -858,11 +858,11 @@ define amdgpu_kernel void @test_only_workitem_id_z() #0 !reqd_work_group_size !2
; GFX900-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX900-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; GFX900-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX900-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX900-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C3]](s32)
- ; GFX900-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
+ ; GFX900-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY15]], [[C3]](i32)
+ ; GFX900-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL]]
; GFX900-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX900-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY16]](<4 x s32>)
@@ -874,7 +874,7 @@ define amdgpu_kernel void @test_only_workitem_id_z() #0 !reqd_work_group_size !2
; GFX900-NEXT: $sgpr13 = COPY [[COPY13]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY14]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[OR]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[OR]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX900-NEXT: S_ENDPGM 0
@@ -904,11 +904,11 @@ define amdgpu_kernel void @test_only_workitem_id_z() #0 !reqd_work_group_size !2
; GFX908-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX908-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; GFX908-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX908-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX908-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C3]](s32)
- ; GFX908-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
+ ; GFX908-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY15]], [[C3]](i32)
+ ; GFX908-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL]]
; GFX908-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX908-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY16]](<4 x s32>)
@@ -920,7 +920,7 @@ define amdgpu_kernel void @test_only_workitem_id_z() #0 !reqd_work_group_size !2
; GFX908-NEXT: $sgpr13 = COPY [[COPY13]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY14]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[OR]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[OR]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX908-NEXT: S_ENDPGM 0
@@ -955,11 +955,11 @@ define amdgpu_kernel void @test_only_workitem_id_xy() #0 !reqd_work_group_size !
; GFX900-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX900-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX900-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C2]](s32)
- ; GFX900-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY16]], [[SHL]]
+ ; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY17]], [[C2]](i32)
+ ; GFX900-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY16]], [[SHL]]
; GFX900-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX900-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
@@ -971,7 +971,7 @@ define amdgpu_kernel void @test_only_workitem_id_xy() #0 !reqd_work_group_size !
; GFX900-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[OR]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[OR]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX900-NEXT: S_ENDPGM 0
@@ -1002,11 +1002,11 @@ define amdgpu_kernel void @test_only_workitem_id_xy() #0 !reqd_work_group_size !
; GFX908-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX908-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX908-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C2]](s32)
- ; GFX908-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY16]], [[SHL]]
+ ; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY17]], [[C2]](i32)
+ ; GFX908-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY16]], [[SHL]]
; GFX908-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX908-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
@@ -1018,7 +1018,7 @@ define amdgpu_kernel void @test_only_workitem_id_xy() #0 !reqd_work_group_size !
; GFX908-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[OR]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[OR]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX908-NEXT: S_ENDPGM 0
@@ -1053,15 +1053,15 @@ define amdgpu_kernel void @test_only_workitem_id_yz() #0 !reqd_work_group_size !
; GFX900-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX900-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX900-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX900-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C3]](s32)
- ; GFX900-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
- ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX900-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX900-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C4]](s32)
- ; GFX900-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GFX900-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX900-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY16]], [[C3]](i32)
+ ; GFX900-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL]]
+ ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX900-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY17]], [[C4]](i32)
+ ; GFX900-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GFX900-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX900-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
@@ -1073,7 +1073,7 @@ define amdgpu_kernel void @test_only_workitem_id_yz() #0 !reqd_work_group_size !
; GFX900-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX900-NEXT: S_ENDPGM 0
@@ -1104,15 +1104,15 @@ define amdgpu_kernel void @test_only_workitem_id_yz() #0 !reqd_work_group_size !
; GFX908-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX908-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX908-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX908-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C3]](s32)
- ; GFX908-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
- ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX908-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX908-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C4]](s32)
- ; GFX908-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GFX908-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX908-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY16]], [[C3]](i32)
+ ; GFX908-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL]]
+ ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX908-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY17]], [[C4]](i32)
+ ; GFX908-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GFX908-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX908-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
@@ -1124,7 +1124,7 @@ define amdgpu_kernel void @test_only_workitem_id_yz() #0 !reqd_work_group_size !
; GFX908-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX908-NEXT: S_ENDPGM 0
@@ -1159,11 +1159,11 @@ define amdgpu_kernel void @test_only_workitem_id_xz() #0 !reqd_work_group_size !
; GFX900-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX900-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX900-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX900-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C2]](s32)
- ; GFX900-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY16]], [[SHL]]
+ ; GFX900-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX900-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX900-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX900-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY17]], [[C2]](i32)
+ ; GFX900-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY16]], [[SHL]]
; GFX900-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX900-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX900-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
@@ -1175,7 +1175,7 @@ define amdgpu_kernel void @test_only_workitem_id_xz() #0 !reqd_work_group_size !
; GFX900-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; GFX900-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; GFX900-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX900-NEXT: $vgpr31 = COPY [[OR]](s32)
+ ; GFX900-NEXT: $vgpr31 = COPY [[OR]](i32)
; GFX900-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX900-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX900-NEXT: S_ENDPGM 0
@@ -1206,11 +1206,11 @@ define amdgpu_kernel void @test_only_workitem_id_xz() #0 !reqd_work_group_size !
; GFX908-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX908-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX908-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX908-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C2]](s32)
- ; GFX908-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY16]], [[SHL]]
+ ; GFX908-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GFX908-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GFX908-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GFX908-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY17]], [[C2]](i32)
+ ; GFX908-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY16]], [[SHL]]
; GFX908-NEXT: $vgpr0 = COPY [[C]](i32)
; GFX908-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX908-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
@@ -1222,7 +1222,7 @@ define amdgpu_kernel void @test_only_workitem_id_xz() #0 !reqd_work_group_size !
; GFX908-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; GFX908-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; GFX908-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GFX908-NEXT: $vgpr31 = COPY [[OR]](s32)
+ ; GFX908-NEXT: $vgpr31 = COPY [[OR]](i32)
; GFX908-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GFX908-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GFX908-NEXT: S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
index eff9273c3d5b6..4cee3d41d8a4c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
@@ -73,8 +73,8 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32() #0 {
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[LOAD1]](i8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[LOAD2]](i32)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
@@ -99,9 +99,9 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32_inreg() #
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32_inreg
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[LOAD1]](i8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT1]](s32)
- ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[LOAD2]](i32)
; CHECK-NEXT: $sgpr5 = COPY [[INTRINSIC_CONVERGENT1]](i32)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
index bc8819ab808e4..582ca77ad4dec 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
@@ -97,15 +97,15 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: $vgpr0 = COPY [[C]](i32)
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -117,7 +117,7 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i32_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
@@ -180,15 +180,15 @@ define amdgpu_kernel void @test_call_external_i1_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -199,7 +199,7 @@ define amdgpu_kernel void @test_call_external_i1_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i1_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[COPY21]](i32)
@@ -258,15 +258,15 @@ define amdgpu_kernel void @test_call_external_i1_zeroext_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -277,7 +277,7 @@ define amdgpu_kernel void @test_call_external_i1_zeroext_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i1_zeroext_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY21]], 1
@@ -320,15 +320,15 @@ define amdgpu_kernel void @test_call_external_i1_signext_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -339,7 +339,7 @@ define amdgpu_kernel void @test_call_external_i1_signext_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i1_signext_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY21]], 1
@@ -382,15 +382,15 @@ define amdgpu_kernel void @test_call_external_i8_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -401,10 +401,10 @@ define amdgpu_kernel void @test_call_external_i8_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i8_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
- ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](s32)
+ ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](i32)
; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC]](i16)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC1]](i8), [[DEF]](p1) :: (volatile store (i8) into `ptr addrspace(1) poison`, addrspace 1)
@@ -423,8 +423,8 @@ define amdgpu_gfx void @test_gfx_call_external_i8_func_void() #0 {
; GCN-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_i8_func_void, csr_amdgpu_si_gfx, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC]](i16)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC1]](i8), [[DEF]](p1) :: (volatile store (i8) into `ptr addrspace(1) poison`, addrspace 1)
@@ -462,15 +462,15 @@ define amdgpu_kernel void @test_call_external_i8_zeroext_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -481,7 +481,7 @@ define amdgpu_kernel void @test_call_external_i8_zeroext_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i8_zeroext_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY21]], 8
@@ -524,15 +524,15 @@ define amdgpu_kernel void @test_call_external_i8_signext_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -543,7 +543,7 @@ define amdgpu_kernel void @test_call_external_i8_signext_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i8_signext_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY21]], 8
@@ -586,15 +586,15 @@ define amdgpu_kernel void @test_call_external_i16_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -605,10 +605,10 @@ define amdgpu_kernel void @test_call_external_i16_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i16_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
- ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](s32)
+ ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](i32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC]](i16), [[DEF]](p1) :: (volatile store (i16) into `ptr addrspace(1) poison`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0
@@ -645,15 +645,15 @@ define amdgpu_kernel void @test_call_external_i16_zeroext_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -664,7 +664,7 @@ define amdgpu_kernel void @test_call_external_i16_zeroext_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i16_zeroext_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY21]], 16
@@ -707,15 +707,15 @@ define amdgpu_kernel void @test_call_external_i16_signext_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -726,7 +726,7 @@ define amdgpu_kernel void @test_call_external_i16_signext_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i16_signext_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY21]], 16
@@ -769,15 +769,15 @@ define amdgpu_kernel void @test_call_external_i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -788,7 +788,7 @@ define amdgpu_kernel void @test_call_external_i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
@@ -845,15 +845,15 @@ define amdgpu_kernel void @test_call_external_i48_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -864,7 +864,7 @@ define amdgpu_kernel void @test_call_external_i48_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i48_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -906,15 +906,15 @@ define amdgpu_kernel void @test_call_external_i48_zeroext_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -925,7 +925,7 @@ define amdgpu_kernel void @test_call_external_i48_zeroext_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i48_zeroext_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -969,15 +969,15 @@ define amdgpu_kernel void @test_call_external_i48_signext_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -988,7 +988,7 @@ define amdgpu_kernel void @test_call_external_i48_signext_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i48_signext_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1032,15 +1032,15 @@ define amdgpu_kernel void @test_call_external_i64_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1051,7 +1051,7 @@ define amdgpu_kernel void @test_call_external_i64_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i64_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1092,15 +1092,15 @@ define amdgpu_kernel void @test_call_external_p1_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1111,7 +1111,7 @@ define amdgpu_kernel void @test_call_external_p1_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_p1_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1152,15 +1152,15 @@ define amdgpu_kernel void @test_call_external_v2p1_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1171,7 +1171,7 @@ define amdgpu_kernel void @test_call_external_v2p1_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v2p1_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1216,15 +1216,15 @@ define amdgpu_kernel void @test_call_external_p3_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1235,7 +1235,7 @@ define amdgpu_kernel void @test_call_external_p3_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_p3_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(p3) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
@@ -1274,15 +1274,15 @@ define amdgpu_kernel void @test_call_external_v2p3_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1293,7 +1293,7 @@ define amdgpu_kernel void @test_call_external_v2p3_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v2p3_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(p3) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(p3) = COPY $vgpr1
@@ -1334,15 +1334,15 @@ define amdgpu_kernel void @test_call_external_f16_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1353,12 +1353,13 @@ define amdgpu_kernel void @test_call_external_f16_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_f16_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
- ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY21]](s32)
+ ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](i32)
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
- ; GCN-NEXT: G_STORE [[TRUNC]](f16), [[DEF]](p1) :: (volatile store (f16) into `ptr addrspace(1) poison`, addrspace 1)
+ ; GCN-NEXT: G_STORE [[BITCAST]](f16), [[DEF]](p1) :: (volatile store (f16) into `ptr addrspace(1) poison`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0
%val = call half @external_f16_func_void()
store volatile half %val, ptr addrspace(1) poison
@@ -1393,15 +1394,15 @@ define amdgpu_kernel void @test_call_external_f32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1412,7 +1413,7 @@ define amdgpu_kernel void @test_call_external_f32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_f32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(f32) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
@@ -1451,15 +1452,15 @@ define amdgpu_kernel void @test_call_external_f64_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1470,7 +1471,7 @@ define amdgpu_kernel void @test_call_external_f64_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_f64_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1511,15 +1512,15 @@ define amdgpu_kernel void @test_call_external_v2f64_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1530,7 +1531,7 @@ define amdgpu_kernel void @test_call_external_v2f64_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v2f64_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1575,15 +1576,15 @@ define amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1594,7 +1595,7 @@ define amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v2i32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1635,15 +1636,15 @@ define amdgpu_kernel void @test_call_external_v3i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1654,7 +1655,7 @@ define amdgpu_kernel void @test_call_external_v3i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v3i32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1696,15 +1697,15 @@ define amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1715,7 +1716,7 @@ define amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v4i32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1758,15 +1759,15 @@ define amdgpu_kernel void @test_call_external_v5i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1777,7 +1778,7 @@ define amdgpu_kernel void @test_call_external_v5i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v5i32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1821,15 +1822,15 @@ define amdgpu_kernel void @test_call_external_v8i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1840,7 +1841,7 @@ define amdgpu_kernel void @test_call_external_v8i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v8i32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1887,15 +1888,15 @@ define amdgpu_kernel void @test_call_external_v16i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1906,7 +1907,7 @@ define amdgpu_kernel void @test_call_external_v16i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v16i32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7, implicit-def $vgpr8, implicit-def $vgpr9, implicit-def $vgpr10, implicit-def $vgpr11, implicit-def $vgpr12, implicit-def $vgpr13, implicit-def $vgpr14, implicit-def $vgpr15
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -1961,15 +1962,15 @@ define amdgpu_kernel void @test_call_external_v32i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1980,7 +1981,7 @@ define amdgpu_kernel void @test_call_external_v32i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v32i32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7, implicit-def $vgpr8, implicit-def $vgpr9, implicit-def $vgpr10, implicit-def $vgpr11, implicit-def $vgpr12, implicit-def $vgpr13, implicit-def $vgpr14, implicit-def $vgpr15, implicit-def $vgpr16, implicit-def $vgpr17, implicit-def $vgpr18, implicit-def $vgpr19, implicit-def $vgpr20, implicit-def $vgpr21, implicit-def $vgpr22, implicit-def $vgpr23, implicit-def $vgpr24, implicit-def $vgpr25, implicit-def $vgpr26, implicit-def $vgpr27, implicit-def $vgpr28, implicit-def $vgpr29, implicit-def $vgpr30, implicit-def $vgpr31
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -2051,15 +2052,15 @@ define amdgpu_kernel void @test_call_external_v2i16_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2070,7 +2071,7 @@ define amdgpu_kernel void @test_call_external_v2i16_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v2i16_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
@@ -2109,15 +2110,15 @@ define amdgpu_kernel void @test_call_external_v3i16_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2128,7 +2129,7 @@ define amdgpu_kernel void @test_call_external_v3i16_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v3i16_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1
@@ -2171,15 +2172,15 @@ define amdgpu_kernel void @test_call_external_v4i16_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2190,7 +2191,7 @@ define amdgpu_kernel void @test_call_external_v4i16_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v4i16_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1
@@ -2231,15 +2232,15 @@ define amdgpu_kernel void @test_call_external_v2f16_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2250,7 +2251,7 @@ define amdgpu_kernel void @test_call_external_v2f16_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v2f16_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
@@ -2289,15 +2290,15 @@ define amdgpu_kernel void @test_call_external_v3f16_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2308,7 +2309,7 @@ define amdgpu_kernel void @test_call_external_v3f16_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v3f16_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
@@ -2351,15 +2352,15 @@ define amdgpu_kernel void @test_call_external_v4f16_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2370,7 +2371,7 @@ define amdgpu_kernel void @test_call_external_v4f16_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v4f16_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
@@ -2411,15 +2412,15 @@ define amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2430,7 +2431,7 @@ define amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v3f32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(f32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(f32) = COPY $vgpr1
@@ -2472,15 +2473,15 @@ define amdgpu_kernel void @test_call_external_v5f32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2491,7 +2492,7 @@ define amdgpu_kernel void @test_call_external_v5f32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v5f32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(f32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(f32) = COPY $vgpr1
@@ -2536,15 +2537,15 @@ define amdgpu_kernel void @test_call_external_i32_i64_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2555,7 +2556,7 @@ define amdgpu_kernel void @test_call_external_i32_i64_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i32_i64_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -2626,15 +2627,15 @@ define amdgpu_kernel void @test_call_external_a2i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2645,7 +2646,7 @@ define amdgpu_kernel void @test_call_external_a2i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_a2i32_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
@@ -2689,15 +2690,15 @@ define amdgpu_kernel void @test_call_external_a5i8_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -2708,22 +2709,22 @@ define amdgpu_kernel void @test_call_external_a5i8_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_a5i8_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4
- ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](s32)
+ ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY21]](i32)
; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC]](i16)
- ; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GCN-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY22]](s32)
+ ; GCN-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GCN-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY22]](i32)
; GCN-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC2]](i16)
- ; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GCN-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY23]](s32)
+ ; GCN-NEXT: [[COPY23:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GCN-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY23]](i32)
; GCN-NEXT: [[TRUNC5:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC4]](i16)
- ; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GCN-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY24]](s32)
+ ; GCN-NEXT: [[COPY24:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GCN-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY24]](i32)
; GCN-NEXT: [[TRUNC7:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC6]](i16)
- ; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GCN-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY25]](s32)
+ ; GCN-NEXT: [[COPY25:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GCN-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY25]](i32)
; GCN-NEXT: [[TRUNC9:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC8]](i16)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC1]](i8), [[DEF]](p1) :: (volatile store (i8) into `ptr addrspace(1) poison`, addrspace 1)
@@ -2775,15 +2776,15 @@ define amdgpu_kernel void @test_call_external_v32i32_i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -2795,7 +2796,7 @@ define amdgpu_kernel void @test_call_external_v32i32_i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v32i32_i32_func_void, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(<32 x i32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load (<32 x i32>) from %stack.0, addrspace 5)
@@ -2842,15 +2843,15 @@ define amdgpu_kernel void @test_call_external_i32_v32i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -2862,7 +2863,7 @@ define amdgpu_kernel void @test_call_external_i32_v32i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_i32_v32i32_func_void, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p5) :: (load (i32) from %stack.0, align 128, addrspace 5)
@@ -2909,15 +2910,15 @@ define amdgpu_kernel void @test_call_external_v33i32_func_void() #0 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -2929,7 +2930,7 @@ define amdgpu_kernel void @test_call_external_v33i32_func_void() #0 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v33i32_func_void, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(<33 x i32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load (<33 x i32>) from %stack.0, align 256, addrspace 5)
@@ -2974,15 +2975,15 @@ define amdgpu_kernel void @test_call_external_v33i32_func_v33i32_i32(ptr addrspa
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD]](p1)
; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN-NEXT: $vgpr1 = COPY [[UV]](i32)
@@ -2998,7 +2999,7 @@ define amdgpu_kernel void @test_call_external_v33i32_func_v33i32_i32(ptr addrspa
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_v33i32_func_v33i32_i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[LOAD2:%[0-9]+]]:_(<33 x i32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load (<33 x i32>) from %stack.0, align 256, addrspace 5)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
index 0b99826895228..4e4b3825ff8a4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
@@ -40,18 +40,18 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
- ; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; GCN-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; GCN-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C4]](i32)
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C5]](i32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; GCN-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GCN-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](s32)
+ ; GCN-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GCN-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](i32)
; GCN-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
; GCN-NEXT: G_MEMCPY [[PTR_ADD2]](p5), [[FRAME_INDEX]](p5), [[C7]](i32), 0 :: (dereferenceable store (s64) into stack, align 4, addrspace 5), (dereferenceable load (s64) from %ir.in.val, align 4, addrspace 5)
; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX1]](p5)
@@ -65,7 +65,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[OR1]](i32)
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GCN-NEXT: ADJCALLSTACKDOWN 0, 8, implicit-def $scc
; GCN-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = nuw nusw inbounds G_PTR_ADD [[FRAME_INDEX1]], [[C2]](i32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
index 4dd4ee0239021..cb223cecc3456 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
@@ -139,15 +139,15 @@ define amdgpu_kernel void @test_call_external_void_func_void() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -158,7 +158,7 @@ define amdgpu_kernel void @test_call_external_void_func_void() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -185,7 +185,7 @@ define void @test_func_call_external_void_func_void() #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -204,7 +204,7 @@ define void @test_func_call_external_void_func_void() #0 {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
@@ -215,7 +215,7 @@ define void @test_func_call_external_void_func_void() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -251,15 +251,15 @@ define amdgpu_kernel void @test_call_external_void_func_empty_struct() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: $vgpr0 = COPY [[C]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -271,7 +271,7 @@ define amdgpu_kernel void @test_call_external_void_func_empty_struct() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_empty_struct, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -307,15 +307,15 @@ define amdgpu_kernel void @test_call_external_void_func_empty_array() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: $vgpr0 = COPY [[C]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -327,7 +327,7 @@ define amdgpu_kernel void @test_call_external_void_func_empty_array() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_empty_array, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -363,15 +363,15 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[C]](i1)
; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
@@ -384,7 +384,7 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i1, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -422,15 +422,15 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD]](i1)
; CHECK-NEXT: $vgpr0 = COPY [[SEXT]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
@@ -443,7 +443,7 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i1_signext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -482,15 +482,15 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD]](i1)
; CHECK-NEXT: $vgpr0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
@@ -503,7 +503,7 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i1_zeroext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -541,18 +541,18 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[C]](i8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -563,7 +563,7 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i8, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -601,15 +601,15 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i16) = G_SEXT [[LOAD]](i8)
; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(i32) = G_SEXT [[SEXT]](i16)
; CHECK-NEXT: $vgpr0 = COPY [[SEXT1]](i32)
@@ -623,7 +623,7 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i8_signext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -662,15 +662,15 @@ define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i16) = G_ZEXT [[LOAD]](i8)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[ZEXT]](i16)
; CHECK-NEXT: $vgpr0 = COPY [[ZEXT1]](i32)
@@ -684,7 +684,7 @@ define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i8_zeroext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -721,17 +721,17 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[C]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -742,7 +742,7 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i16, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -780,15 +780,15 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD]](i16)
; CHECK-NEXT: $vgpr0 = COPY [[SEXT]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
@@ -801,7 +801,7 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i16_signext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -840,15 +840,15 @@ define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD]](i16)
; CHECK-NEXT: $vgpr0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
@@ -861,7 +861,7 @@ define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i16_zeroext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -899,15 +899,15 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: $vgpr0 = COPY [[C]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -919,7 +919,7 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -994,15 +994,15 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[C]](i64)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1016,7 +1016,7 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1053,15 +1053,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD]](<2 x i64>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1077,7 +1077,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1116,15 +1116,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x i64>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1140,7 +1140,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1178,15 +1178,15 @@ define amdgpu_kernel void @test_call_external_void_func_i48(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](i48)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
@@ -1201,7 +1201,7 @@ define amdgpu_kernel void @test_call_external_void_func_i48(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i48, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1240,15 +1240,15 @@ define amdgpu_kernel void @test_call_external_void_func_i48_signext(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](i48)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[SEXT]](s64)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
@@ -1263,7 +1263,7 @@ define amdgpu_kernel void @test_call_external_void_func_i48_signext(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i48_signext, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1302,15 +1302,15 @@ define amdgpu_kernel void @test_call_external_void_func_i48_zeroext(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](i48)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[ZEXT]](s64)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
@@ -1325,7 +1325,7 @@ define amdgpu_kernel void @test_call_external_void_func_i48_zeroext(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i48_zeroext, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1363,15 +1363,15 @@ define amdgpu_kernel void @test_call_external_void_func_p0_imm(ptr %arg) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD]](p0)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1385,7 +1385,7 @@ define amdgpu_kernel void @test_call_external_void_func_p0_imm(ptr %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_p0, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1422,15 +1422,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2p0() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD]](<2 x p0>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1446,7 +1446,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2p0() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2p0, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1488,15 +1488,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[SHUF]](<3 x i64>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1514,7 +1514,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1558,15 +1558,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C5]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[SHUF]](<4 x i64>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1586,7 +1586,7 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1624,17 +1624,17 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](f16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[C]](f16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1645,7 +1645,7 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f16, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1681,15 +1681,15 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: $vgpr0 = COPY [[C]](f32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -1701,7 +1701,7 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1739,15 +1739,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x f32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](f32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1761,7 +1761,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1800,15 +1800,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C5]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x f32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](f32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1823,7 +1823,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1864,15 +1864,15 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C6]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C7]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C6]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C7]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x f32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](f32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1889,7 +1889,7 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v5f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1925,15 +1925,15 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[C]](f64)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1947,7 +1947,7 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -1985,15 +1985,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x f64>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -2009,7 +2009,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2f64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2048,15 +2048,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C5]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x f64>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -2074,7 +2074,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3f64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2111,15 +2111,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: $vgpr0 = COPY [[LOAD]](<2 x i16>)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -2131,7 +2131,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i16, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2169,15 +2169,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[LOAD]](<3 x i16>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i16>) = G_BUILD_VECTOR [[UV]](i16), [[UV1]](i16), [[UV2]](i16), [[DEF2]](i16)
@@ -2194,7 +2194,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2232,15 +2232,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f16), [[UV1:%[0-9]+]]:_(f16), [[UV2:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[LOAD]](<3 x f16>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV]](f16), [[UV1]](f16), [[UV2]](f16), [[DEF2]](f16)
@@ -2257,7 +2257,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3f16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2295,15 +2295,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i16>), [[UV1:%[0-9]+]]:_(<2 x i16>) = G_UNMERGE_VALUES [[LOAD]](<4 x i16>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](<2 x i16>)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](<2 x i16>)
@@ -2317,7 +2317,7 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2358,15 +2358,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C5]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C6]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i16>), [[UV1:%[0-9]+]]:_(<2 x i16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i16>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](<2 x i16>)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](<2 x i16>)
@@ -2380,7 +2380,7 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2417,15 +2417,15 @@ define amdgpu_kernel void @test_call_external_void_func_v5i16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16), [[UV4:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[LOAD]](<5 x i16>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x i16>) = G_BUILD_VECTOR [[UV]](i16), [[UV1]](i16), [[UV2]](i16), [[UV3]](i16), [[UV4]](i16), [[DEF2]](i16)
@@ -2443,7 +2443,7 @@ define amdgpu_kernel void @test_call_external_void_func_v5i16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v5i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2481,15 +2481,15 @@ define amdgpu_kernel void @test_call_external_void_func_v7i16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16), [[UV4:%[0-9]+]]:_(i16), [[UV5:%[0-9]+]]:_(i16), [[UV6:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[LOAD]](<7 x i16>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i16>) = G_BUILD_VECTOR [[UV]](i16), [[UV1]](i16), [[UV2]](i16), [[UV3]](i16), [[UV4]](i16), [[UV5]](i16), [[UV6]](i16), [[DEF2]](i16)
@@ -2508,7 +2508,7 @@ define amdgpu_kernel void @test_call_external_void_func_v7i16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v7i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2546,22 +2546,22 @@ define amdgpu_kernel void @test_call_external_void_func_v63i16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16), [[UV4:%[0-9]+]]:_(i16), [[UV5:%[0-9]+]]:_(i16), [[UV6:%[0-9]+]]:_(i16), [[UV7:%[0-9]+]]:_(i16), [[UV8:%[0-9]+]]:_(i16), [[UV9:%[0-9]+]]:_(i16), [[UV10:%[0-9]+]]:_(i16), [[UV11:%[0-9]+]]:_(i16), [[UV12:%[0-9]+]]:_(i16), [[UV13:%[0-9]+]]:_(i16), [[UV14:%[0-9]+]]:_(i16), [[UV15:%[0-9]+]]:_(i16), [[UV16:%[0-9]+]]:_(i16), [[UV17:%[0-9]+]]:_(i16), [[UV18:%[0-9]+]]:_(i16), [[UV19:%[0-9]+]]:_(i16), [[UV20:%[0-9]+]]:_(i16), [[UV21:%[0-9]+]]:_(i16), [[UV22:%[0-9]+]]:_(i16), [[UV23:%[0-9]+]]:_(i16), [[UV24:%[0-9]+]]:_(i16), [[UV25:%[0-9]+]]:_(i16), [[UV26:%[0-9]+]]:_(i16), [[UV27:%[0-9]+]]:_(i16), [[UV28:%[0-9]+]]:_(i16), [[UV29:%[0-9]+]]:_(i16), [[UV30:%[0-9]+]]:_(i16), [[UV31:%[0-9]+]]:_(i16), [[UV32:%[0-9]+]]:_(i16), [[UV33:%[0-9]+]]:_(i16), [[UV34:%[0-9]+]]:_(i16), [[UV35:%[0-9]+]]:_(i16), [[UV36:%[0-9]+]]:_(i16), [[UV37:%[0-9]+]]:_(i16), [[UV38:%[0-9]+]]:_(i16), [[UV39:%[0-9]+]]:_(i16), [[UV40:%[0-9]+]]:_(i16), [[UV41:%[0-9]+]]:_(i16), [[UV42:%[0-9]+]]:_(i16), [[UV43:%[0-9]+]]:_(i16), [[UV44:%[0-9]+]]:_(i16), [[UV45:%[0-9]+]]:_(i16), [[UV46:%[0-9]+]]:_(i16), [[UV47:%[0-9]+]]:_(i16), [[UV48:%[0-9]+]]:_(i16), [[UV49:%[0-9]+]]:_(i16), [[UV50:%[0-9]+]]:_(i16), [[UV51:%[0-9]+]]:_(i16), [[UV52:%[0-9]+]]:_(i16), [[UV53:%[0-9]+]]:_(i16), [[UV54:%[0-9]+]]:_(i16), [[UV55:%[0-9]+]]:_(i16), [[UV56:%[0-9]+]]:_(i16), [[UV57:%[0-9]+]]:_(i16), [[UV58:%[0-9]+]]:_(i16), [[UV59:%[0-9]+]]:_(i16), [[UV60:%[0-9]+]]:_(i16), [[UV61:%[0-9]+]]:_(i16), [[UV62:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[LOAD]](<63 x i16>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<64 x i16>) = G_BUILD_VECTOR [[UV]](i16), [[UV1]](i16), [[UV2]](i16), [[UV3]](i16), [[UV4]](i16), [[UV5]](i16), [[UV6]](i16), [[UV7]](i16), [[UV8]](i16), [[UV9]](i16), [[UV10]](i16), [[UV11]](i16), [[UV12]](i16), [[UV13]](i16), [[UV14]](i16), [[UV15]](i16), [[UV16]](i16), [[UV17]](i16), [[UV18]](i16), [[UV19]](i16), [[UV20]](i16), [[UV21]](i16), [[UV22]](i16), [[UV23]](i16), [[UV24]](i16), [[UV25]](i16), [[UV26]](i16), [[UV27]](i16), [[UV28]](i16), [[UV29]](i16), [[UV30]](i16), [[UV31]](i16), [[UV32]](i16), [[UV33]](i16), [[UV34]](i16), [[UV35]](i16), [[UV36]](i16), [[UV37]](i16), [[UV38]](i16), [[UV39]](i16), [[UV40]](i16), [[UV41]](i16), [[UV42]](i16), [[UV43]](i16), [[UV44]](i16), [[UV45]](i16), [[UV46]](i16), [[UV47]](i16), [[UV48]](i16), [[UV49]](i16), [[UV50]](i16), [[UV51]](i16), [[UV52]](i16), [[UV53]](i16), [[UV54]](i16), [[UV55]](i16), [[UV56]](i16), [[UV57]](i16), [[UV58]](i16), [[UV59]](i16), [[UV60]](i16), [[UV61]](i16), [[UV62]](i16), [[DEF2]](i16)
; CHECK-NEXT: [[UV63:%[0-9]+]]:_(<2 x i16>), [[UV64:%[0-9]+]]:_(<2 x i16>), [[UV65:%[0-9]+]]:_(<2 x i16>), [[UV66:%[0-9]+]]:_(<2 x i16>), [[UV67:%[0-9]+]]:_(<2 x i16>), [[UV68:%[0-9]+]]:_(<2 x i16>), [[UV69:%[0-9]+]]:_(<2 x i16>), [[UV70:%[0-9]+]]:_(<2 x i16>), [[UV71:%[0-9]+]]:_(<2 x i16>), [[UV72:%[0-9]+]]:_(<2 x i16>), [[UV73:%[0-9]+]]:_(<2 x i16>), [[UV74:%[0-9]+]]:_(<2 x i16>), [[UV75:%[0-9]+]]:_(<2 x i16>), [[UV76:%[0-9]+]]:_(<2 x i16>), [[UV77:%[0-9]+]]:_(<2 x i16>), [[UV78:%[0-9]+]]:_(<2 x i16>), [[UV79:%[0-9]+]]:_(<2 x i16>), [[UV80:%[0-9]+]]:_(<2 x i16>), [[UV81:%[0-9]+]]:_(<2 x i16>), [[UV82:%[0-9]+]]:_(<2 x i16>), [[UV83:%[0-9]+]]:_(<2 x i16>), [[UV84:%[0-9]+]]:_(<2 x i16>), [[UV85:%[0-9]+]]:_(<2 x i16>), [[UV86:%[0-9]+]]:_(<2 x i16>), [[UV87:%[0-9]+]]:_(<2 x i16>), [[UV88:%[0-9]+]]:_(<2 x i16>), [[UV89:%[0-9]+]]:_(<2 x i16>), [[UV90:%[0-9]+]]:_(<2 x i16>), [[UV91:%[0-9]+]]:_(<2 x i16>), [[UV92:%[0-9]+]]:_(<2 x i16>), [[UV93:%[0-9]+]]:_(<2 x i16>), [[UV94:%[0-9]+]]:_(<2 x i16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<64 x i16>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](i32)
; CHECK-NEXT: G_STORE [[UV94]](<2 x i16>), [[PTR_ADD1]](p5) :: (store (<2 x i16>) into stack, align 16, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV63]](<2 x i16>)
; CHECK-NEXT: $vgpr1 = COPY [[UV64]](<2 x i16>)
@@ -2604,7 +2604,7 @@ define amdgpu_kernel void @test_call_external_void_func_v63i16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v63i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 4, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2642,25 +2642,25 @@ define amdgpu_kernel void @test_call_external_void_func_v65i16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16), [[UV4:%[0-9]+]]:_(i16), [[UV5:%[0-9]+]]:_(i16), [[UV6:%[0-9]+]]:_(i16), [[UV7:%[0-9]+]]:_(i16), [[UV8:%[0-9]+]]:_(i16), [[UV9:%[0-9]+]]:_(i16), [[UV10:%[0-9]+]]:_(i16), [[UV11:%[0-9]+]]:_(i16), [[UV12:%[0-9]+]]:_(i16), [[UV13:%[0-9]+]]:_(i16), [[UV14:%[0-9]+]]:_(i16), [[UV15:%[0-9]+]]:_(i16), [[UV16:%[0-9]+]]:_(i16), [[UV17:%[0-9]+]]:_(i16), [[UV18:%[0-9]+]]:_(i16), [[UV19:%[0-9]+]]:_(i16), [[UV20:%[0-9]+]]:_(i16), [[UV21:%[0-9]+]]:_(i16), [[UV22:%[0-9]+]]:_(i16), [[UV23:%[0-9]+]]:_(i16), [[UV24:%[0-9]+]]:_(i16), [[UV25:%[0-9]+]]:_(i16), [[UV26:%[0-9]+]]:_(i16), [[UV27:%[0-9]+]]:_(i16), [[UV28:%[0-9]+]]:_(i16), [[UV29:%[0-9]+]]:_(i16), [[UV30:%[0-9]+]]:_(i16), [[UV31:%[0-9]+]]:_(i16), [[UV32:%[0-9]+]]:_(i16), [[UV33:%[0-9]+]]:_(i16), [[UV34:%[0-9]+]]:_(i16), [[UV35:%[0-9]+]]:_(i16), [[UV36:%[0-9]+]]:_(i16), [[UV37:%[0-9]+]]:_(i16), [[UV38:%[0-9]+]]:_(i16), [[UV39:%[0-9]+]]:_(i16), [[UV40:%[0-9]+]]:_(i16), [[UV41:%[0-9]+]]:_(i16), [[UV42:%[0-9]+]]:_(i16), [[UV43:%[0-9]+]]:_(i16), [[UV44:%[0-9]+]]:_(i16), [[UV45:%[0-9]+]]:_(i16), [[UV46:%[0-9]+]]:_(i16), [[UV47:%[0-9]+]]:_(i16), [[UV48:%[0-9]+]]:_(i16), [[UV49:%[0-9]+]]:_(i16), [[UV50:%[0-9]+]]:_(i16), [[UV51:%[0-9]+]]:_(i16), [[UV52:%[0-9]+]]:_(i16), [[UV53:%[0-9]+]]:_(i16), [[UV54:%[0-9]+]]:_(i16), [[UV55:%[0-9]+]]:_(i16), [[UV56:%[0-9]+]]:_(i16), [[UV57:%[0-9]+]]:_(i16), [[UV58:%[0-9]+]]:_(i16), [[UV59:%[0-9]+]]:_(i16), [[UV60:%[0-9]+]]:_(i16), [[UV61:%[0-9]+]]:_(i16), [[UV62:%[0-9]+]]:_(i16), [[UV63:%[0-9]+]]:_(i16), [[UV64:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[LOAD]](<65 x i16>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<66 x i16>) = G_BUILD_VECTOR [[UV]](i16), [[UV1]](i16), [[UV2]](i16), [[UV3]](i16), [[UV4]](i16), [[UV5]](i16), [[UV6]](i16), [[UV7]](i16), [[UV8]](i16), [[UV9]](i16), [[UV10]](i16), [[UV11]](i16), [[UV12]](i16), [[UV13]](i16), [[UV14]](i16), [[UV15]](i16), [[UV16]](i16), [[UV17]](i16), [[UV18]](i16), [[UV19]](i16), [[UV20]](i16), [[UV21]](i16), [[UV22]](i16), [[UV23]](i16), [[UV24]](i16), [[UV25]](i16), [[UV26]](i16), [[UV27]](i16), [[UV28]](i16), [[UV29]](i16), [[UV30]](i16), [[UV31]](i16), [[UV32]](i16), [[UV33]](i16), [[UV34]](i16), [[UV35]](i16), [[UV36]](i16), [[UV37]](i16), [[UV38]](i16), [[UV39]](i16), [[UV40]](i16), [[UV41]](i16), [[UV42]](i16), [[UV43]](i16), [[UV44]](i16), [[UV45]](i16), [[UV46]](i16), [[UV47]](i16), [[UV48]](i16), [[UV49]](i16), [[UV50]](i16), [[UV51]](i16), [[UV52]](i16), [[UV53]](i16), [[UV54]](i16), [[UV55]](i16), [[UV56]](i16), [[UV57]](i16), [[UV58]](i16), [[UV59]](i16), [[UV60]](i16), [[UV61]](i16), [[UV62]](i16), [[UV63]](i16), [[UV64]](i16), [[DEF2]](i16)
; CHECK-NEXT: [[UV65:%[0-9]+]]:_(<2 x i16>), [[UV66:%[0-9]+]]:_(<2 x i16>), [[UV67:%[0-9]+]]:_(<2 x i16>), [[UV68:%[0-9]+]]:_(<2 x i16>), [[UV69:%[0-9]+]]:_(<2 x i16>), [[UV70:%[0-9]+]]:_(<2 x i16>), [[UV71:%[0-9]+]]:_(<2 x i16>), [[UV72:%[0-9]+]]:_(<2 x i16>), [[UV73:%[0-9]+]]:_(<2 x i16>), [[UV74:%[0-9]+]]:_(<2 x i16>), [[UV75:%[0-9]+]]:_(<2 x i16>), [[UV76:%[0-9]+]]:_(<2 x i16>), [[UV77:%[0-9]+]]:_(<2 x i16>), [[UV78:%[0-9]+]]:_(<2 x i16>), [[UV79:%[0-9]+]]:_(<2 x i16>), [[UV80:%[0-9]+]]:_(<2 x i16>), [[UV81:%[0-9]+]]:_(<2 x i16>), [[UV82:%[0-9]+]]:_(<2 x i16>), [[UV83:%[0-9]+]]:_(<2 x i16>), [[UV84:%[0-9]+]]:_(<2 x i16>), [[UV85:%[0-9]+]]:_(<2 x i16>), [[UV86:%[0-9]+]]:_(<2 x i16>), [[UV87:%[0-9]+]]:_(<2 x i16>), [[UV88:%[0-9]+]]:_(<2 x i16>), [[UV89:%[0-9]+]]:_(<2 x i16>), [[UV90:%[0-9]+]]:_(<2 x i16>), [[UV91:%[0-9]+]]:_(<2 x i16>), [[UV92:%[0-9]+]]:_(<2 x i16>), [[UV93:%[0-9]+]]:_(<2 x i16>), [[UV94:%[0-9]+]]:_(<2 x i16>), [[UV95:%[0-9]+]]:_(<2 x i16>), [[UV96:%[0-9]+]]:_(<2 x i16>), [[UV97:%[0-9]+]]:_(<2 x i16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<66 x i16>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](i32)
; CHECK-NEXT: G_STORE [[UV96]](<2 x i16>), [[PTR_ADD1]](p5) :: (store (<2 x i16>) into stack, align 16, addrspace 5)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](i32)
; CHECK-NEXT: G_STORE [[UV97]](<2 x i16>), [[PTR_ADD2]](p5) :: (store (<2 x i16>) into stack + 4, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV65]](<2 x i16>)
; CHECK-NEXT: $vgpr1 = COPY [[UV66]](<2 x i16>)
@@ -2703,7 +2703,7 @@ define amdgpu_kernel void @test_call_external_void_func_v65i16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v65i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 8, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2741,22 +2741,22 @@ define amdgpu_kernel void @test_call_external_void_func_v66i16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i16>), [[UV1:%[0-9]+]]:_(<2 x i16>), [[UV2:%[0-9]+]]:_(<2 x i16>), [[UV3:%[0-9]+]]:_(<2 x i16>), [[UV4:%[0-9]+]]:_(<2 x i16>), [[UV5:%[0-9]+]]:_(<2 x i16>), [[UV6:%[0-9]+]]:_(<2 x i16>), [[UV7:%[0-9]+]]:_(<2 x i16>), [[UV8:%[0-9]+]]:_(<2 x i16>), [[UV9:%[0-9]+]]:_(<2 x i16>), [[UV10:%[0-9]+]]:_(<2 x i16>), [[UV11:%[0-9]+]]:_(<2 x i16>), [[UV12:%[0-9]+]]:_(<2 x i16>), [[UV13:%[0-9]+]]:_(<2 x i16>), [[UV14:%[0-9]+]]:_(<2 x i16>), [[UV15:%[0-9]+]]:_(<2 x i16>), [[UV16:%[0-9]+]]:_(<2 x i16>), [[UV17:%[0-9]+]]:_(<2 x i16>), [[UV18:%[0-9]+]]:_(<2 x i16>), [[UV19:%[0-9]+]]:_(<2 x i16>), [[UV20:%[0-9]+]]:_(<2 x i16>), [[UV21:%[0-9]+]]:_(<2 x i16>), [[UV22:%[0-9]+]]:_(<2 x i16>), [[UV23:%[0-9]+]]:_(<2 x i16>), [[UV24:%[0-9]+]]:_(<2 x i16>), [[UV25:%[0-9]+]]:_(<2 x i16>), [[UV26:%[0-9]+]]:_(<2 x i16>), [[UV27:%[0-9]+]]:_(<2 x i16>), [[UV28:%[0-9]+]]:_(<2 x i16>), [[UV29:%[0-9]+]]:_(<2 x i16>), [[UV30:%[0-9]+]]:_(<2 x i16>), [[UV31:%[0-9]+]]:_(<2 x i16>), [[UV32:%[0-9]+]]:_(<2 x i16>) = G_UNMERGE_VALUES [[LOAD]](<66 x i16>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](i32)
; CHECK-NEXT: G_STORE [[UV31]](<2 x i16>), [[PTR_ADD1]](p5) :: (store (<2 x i16>) into stack, align 16, addrspace 5)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](i32)
; CHECK-NEXT: G_STORE [[UV32]](<2 x i16>), [[PTR_ADD2]](p5) :: (store (<2 x i16>) into stack + 4, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](<2 x i16>)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](<2 x i16>)
@@ -2799,7 +2799,7 @@ define amdgpu_kernel void @test_call_external_void_func_v66i16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v66i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 8, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2837,15 +2837,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: $vgpr0 = COPY [[LOAD]](<2 x f16>)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -2857,7 +2857,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2f16, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2895,15 +2895,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD]](<2 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -2917,7 +2917,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -2956,15 +2956,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -2978,7 +2978,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3018,15 +3018,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C5]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3041,7 +3041,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3082,15 +3082,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C5]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C6]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3106,7 +3106,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i32_i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3143,15 +3143,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD]](<4 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3167,7 +3167,7 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3208,15 +3208,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C5]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C6]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3232,7 +3232,7 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3273,15 +3273,15 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C6]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C7]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C6]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C7]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3298,7 +3298,7 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v5i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3336,15 +3336,15 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD1]](<8 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3364,7 +3364,7 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v8i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3410,15 +3410,15 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C9]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C10]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C9]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C10]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3438,7 +3438,7 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v8i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3476,15 +3476,15 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD1]](<16 x i32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3512,7 +3512,7 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v16i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3552,19 +3552,19 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32), [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32), [[UV18:%[0-9]+]]:_(i32), [[UV19:%[0-9]+]]:_(i32), [[UV20:%[0-9]+]]:_(i32), [[UV21:%[0-9]+]]:_(i32), [[UV22:%[0-9]+]]:_(i32), [[UV23:%[0-9]+]]:_(i32), [[UV24:%[0-9]+]]:_(i32), [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32), [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD1]](<32 x i32>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](i32)
; CHECK-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD1]](p5) :: (store (i32) into stack, align 16, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3607,7 +3607,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 4, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3650,22 +3650,22 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32), [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32), [[UV18:%[0-9]+]]:_(i32), [[UV19:%[0-9]+]]:_(i32), [[UV20:%[0-9]+]]:_(i32), [[UV21:%[0-9]+]]:_(i32), [[UV22:%[0-9]+]]:_(i32), [[UV23:%[0-9]+]]:_(i32), [[UV24:%[0-9]+]]:_(i32), [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32), [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD1]](<32 x i32>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](i32)
; CHECK-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD1]](p5) :: (store (i32) into stack, align 16, addrspace 5)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](i32)
; CHECK-NEXT: G_STORE [[LOAD2]](i32), [[PTR_ADD2]](p5) :: (store (i32) into stack + 4, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3708,7 +3708,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF2]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32_i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 8, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3752,30 +3752,30 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i8_i8_i16() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32), [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32), [[UV18:%[0-9]+]]:_(i32), [[UV19:%[0-9]+]]:_(i32), [[UV20:%[0-9]+]]:_(i32), [[UV21:%[0-9]+]]:_(i32), [[UV22:%[0-9]+]]:_(i32), [[UV23:%[0-9]+]]:_(i32), [[UV24:%[0-9]+]]:_(i32), [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32), [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD1]](<32 x i32>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](i32)
; CHECK-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD1]](p5) :: (store (i32) into stack, align 16, addrspace 5)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[LOAD2]](i8)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](i32)
; CHECK-NEXT: G_STORE [[ANYEXT]](i16), [[PTR_ADD2]](p5) :: (store (i16) into stack + 4, align 4, addrspace 5)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(i16) = COPY [[ANYEXT]](i16)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C5]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C5]](i32)
; CHECK-NEXT: G_STORE [[COPY20]](i16), [[PTR_ADD3]](p5) :: (store (i16) into stack + 8, align 8, addrspace 5)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](i32)
; CHECK-NEXT: G_STORE [[LOAD3]](i16), [[PTR_ADD4]](p5) :: (store (i16) into stack + 12, align 4, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3818,7 +3818,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i8_i8_i16() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF2]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32_i8_i8_i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 16, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3865,25 +3865,25 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_p3_p5() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32), [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32), [[UV18:%[0-9]+]]:_(i32), [[UV19:%[0-9]+]]:_(i32), [[UV20:%[0-9]+]]:_(i32), [[UV21:%[0-9]+]]:_(i32), [[UV22:%[0-9]+]]:_(i32), [[UV23:%[0-9]+]]:_(i32), [[UV24:%[0-9]+]]:_(i32), [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32), [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD1]](<32 x i32>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](i32)
; CHECK-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD1]](p5) :: (store (i32) into stack, align 16, addrspace 5)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](i32)
; CHECK-NEXT: G_STORE [[INTTOPTR]](p3), [[PTR_ADD2]](p5) :: (store (p3) into stack + 4, addrspace 5)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C5]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C5]](i32)
; CHECK-NEXT: G_STORE [[INTTOPTR1]](p5), [[PTR_ADD3]](p5) :: (store (p5) into stack + 8, align 8, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -3926,7 +3926,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_p3_p5() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF2]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32_p3_p5, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 12, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -3971,18 +3971,18 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[LOAD1]](i8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[LOAD2]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
@@ -3994,7 +3994,7 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_struct_i8_i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -4016,8 +4016,8 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32() #0 {
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[LOAD1]](i8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[LOAD2]](i32)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
@@ -4042,9 +4042,9 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32_inreg() #
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32_inreg
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[LOAD1]](i8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT1]](s32)
- ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[LOAD2]](i32)
; CHECK-NEXT: $sgpr5 = COPY [[INTRINSIC_CONVERGENT1]](i32)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
@@ -4092,18 +4092,18 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C4]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C5]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](i32)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
; CHECK-NEXT: G_MEMCPY [[PTR_ADD2]](p5), [[FRAME_INDEX]](p5), [[C7]](i32), 0 :: (dereferenceable store (s64) into stack, align 4, addrspace 5), (dereferenceable load (s64) from %ir.val, align 4, addrspace 5)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
@@ -4116,7 +4116,7 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_byval_struct_i8_i32, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 8, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -4136,7 +4136,7 @@ define void @call_byval_3ai32_byval_i8_align32(ptr addrspace(5) %incoming0, ptr
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -4158,14 +4158,14 @@ define void @call_byval_3ai32_byval_i8_align32(ptr addrspace(5) %incoming0, ptr
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C1]](i32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
; CHECK-NEXT: G_MEMCPY [[PTR_ADD]](p5), [[COPY9]](p5), [[C2]](i32), 0 :: (dereferenceable store (s96) into stack, align 4, addrspace 5), (dereferenceable load (s96) from %ir.incoming0, align 4, addrspace 5)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](i32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: G_MEMCPY [[PTR_ADD1]](p5), [[COPY10]](p5), [[C4]](i32), 0 :: (dereferenceable store (s8) into stack + 32, align 32, addrspace 5), (dereferenceable load (s8) from %ir.incoming1, align 32, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[C]](i32)
@@ -4179,7 +4179,7 @@ define void @call_byval_3ai32_byval_i8_align32(ptr addrspace(5) %incoming0, ptr
; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @void_func_byval_a3i32_byval_i8_align32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 36, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -4196,7 +4196,7 @@ define void @call_byval_a4i64_align4_higher_source_align(ptr addrspace(5) align
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -4216,10 +4216,10 @@ define void @call_byval_a4i64_align4_higher_source_align(ptr addrspace(5) align
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
; CHECK-NEXT: G_MEMCPY [[PTR_ADD]](p5), [[COPY9]](p5), [[C1]](i32), 0 :: (dereferenceable store (s256) into stack, align 4, addrspace 5), (dereferenceable load (s256) from %ir.incoming_high_align, align 256, addrspace 5)
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
@@ -4232,7 +4232,7 @@ define void @call_byval_a4i64_align4_higher_source_align(ptr addrspace(5) align
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @void_func_byval_a4i64_align4, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 32, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -4270,22 +4270,22 @@ define amdgpu_kernel void @test_call_external_void_func_v2i8() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[LOAD1]](<2 x i8>)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[UV]](i8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[UV1]](i8)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT2]](s32)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](i16)
- ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT3]](s32)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT2]](i32)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT1]](i16)
+ ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT3]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -4296,7 +4296,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2i8() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -4336,25 +4336,25 @@ define amdgpu_kernel void @test_call_external_void_func_v3i8() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[LOAD1]](<3 x i8>)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[UV]](i8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[UV1]](i8)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i16) = G_ANYEXT [[UV2]](i8)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT3]](s32)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](i16)
- ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT4]](s32)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](i16)
- ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT5]](s32)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT3]](i32)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT1]](i16)
+ ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT4]](i32)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT2]](i16)
+ ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT5]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -4365,7 +4365,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i8() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -4405,28 +4405,28 @@ define amdgpu_kernel void @test_call_external_void_func_v4i8() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[LOAD1]](<4 x i8>)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[UV]](i8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[UV1]](i8)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i16) = G_ANYEXT [[UV2]](i8)
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i16) = G_ANYEXT [[UV3]](i8)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT4]](s32)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](i16)
- ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT5]](s32)
- ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](i16)
- ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT6]](s32)
- ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](i16)
- ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT7]](s32)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT4]](i32)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT1]](i16)
+ ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT5]](i32)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT2]](i16)
+ ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT6]](i32)
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT3]](i16)
+ ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT7]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -4437,7 +4437,7 @@ define amdgpu_kernel void @test_call_external_void_func_v4i8() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -4477,15 +4477,15 @@ define amdgpu_kernel void @test_call_external_void_func_v8i8() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8), [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8), [[UV6:%[0-9]+]]:_(i8), [[UV7:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[LOAD1]](<8 x i8>)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[UV]](i8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[UV1]](i8)
@@ -4495,22 +4495,22 @@ define amdgpu_kernel void @test_call_external_void_func_v8i8() #0 {
; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i16) = G_ANYEXT [[UV5]](i8)
; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i16) = G_ANYEXT [[UV6]](i8)
; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(i16) = G_ANYEXT [[UV7]](i8)
- ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT8]](s32)
- ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](i16)
- ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT9]](s32)
- ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](i16)
- ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT10]](s32)
- ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](i16)
- ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT11]](s32)
- ; CHECK-NEXT: [[ANYEXT12:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT4]](i16)
- ; CHECK-NEXT: $vgpr4 = COPY [[ANYEXT12]](s32)
- ; CHECK-NEXT: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT5]](i16)
- ; CHECK-NEXT: $vgpr5 = COPY [[ANYEXT13]](s32)
- ; CHECK-NEXT: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT6]](i16)
- ; CHECK-NEXT: $vgpr6 = COPY [[ANYEXT14]](s32)
- ; CHECK-NEXT: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT7]](i16)
- ; CHECK-NEXT: $vgpr7 = COPY [[ANYEXT15]](s32)
+ ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT8]](i32)
+ ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT1]](i16)
+ ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT9]](i32)
+ ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT2]](i16)
+ ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT10]](i32)
+ ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT3]](i16)
+ ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT11]](i32)
+ ; CHECK-NEXT: [[ANYEXT12:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT4]](i16)
+ ; CHECK-NEXT: $vgpr4 = COPY [[ANYEXT12]](i32)
+ ; CHECK-NEXT: [[ANYEXT13:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT5]](i16)
+ ; CHECK-NEXT: $vgpr5 = COPY [[ANYEXT13]](i32)
+ ; CHECK-NEXT: [[ANYEXT14:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT6]](i16)
+ ; CHECK-NEXT: $vgpr6 = COPY [[ANYEXT14]](i32)
+ ; CHECK-NEXT: [[ANYEXT15:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT7]](i16)
+ ; CHECK-NEXT: $vgpr7 = COPY [[ANYEXT15]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -4521,7 +4521,7 @@ define amdgpu_kernel void @test_call_external_void_func_v8i8() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v8i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -4561,15 +4561,15 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8), [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8), [[UV6:%[0-9]+]]:_(i8), [[UV7:%[0-9]+]]:_(i8), [[UV8:%[0-9]+]]:_(i8), [[UV9:%[0-9]+]]:_(i8), [[UV10:%[0-9]+]]:_(i8), [[UV11:%[0-9]+]]:_(i8), [[UV12:%[0-9]+]]:_(i8), [[UV13:%[0-9]+]]:_(i8), [[UV14:%[0-9]+]]:_(i8), [[UV15:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[LOAD1]](<16 x i8>)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[UV]](i8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[UV1]](i8)
@@ -4587,38 +4587,38 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
; CHECK-NEXT: [[ANYEXT13:%[0-9]+]]:_(i16) = G_ANYEXT [[UV13]](i8)
; CHECK-NEXT: [[ANYEXT14:%[0-9]+]]:_(i16) = G_ANYEXT [[UV14]](i8)
; CHECK-NEXT: [[ANYEXT15:%[0-9]+]]:_(i16) = G_ANYEXT [[UV15]](i8)
- ; CHECK-NEXT: [[ANYEXT16:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](i16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT16]](s32)
- ; CHECK-NEXT: [[ANYEXT17:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](i16)
- ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT17]](s32)
- ; CHECK-NEXT: [[ANYEXT18:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](i16)
- ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT18]](s32)
- ; CHECK-NEXT: [[ANYEXT19:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](i16)
- ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT19]](s32)
- ; CHECK-NEXT: [[ANYEXT20:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT4]](i16)
- ; CHECK-NEXT: $vgpr4 = COPY [[ANYEXT20]](s32)
- ; CHECK-NEXT: [[ANYEXT21:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT5]](i16)
- ; CHECK-NEXT: $vgpr5 = COPY [[ANYEXT21]](s32)
- ; CHECK-NEXT: [[ANYEXT22:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT6]](i16)
- ; CHECK-NEXT: $vgpr6 = COPY [[ANYEXT22]](s32)
- ; CHECK-NEXT: [[ANYEXT23:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT7]](i16)
- ; CHECK-NEXT: $vgpr7 = COPY [[ANYEXT23]](s32)
- ; CHECK-NEXT: [[ANYEXT24:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT8]](i16)
- ; CHECK-NEXT: $vgpr8 = COPY [[ANYEXT24]](s32)
- ; CHECK-NEXT: [[ANYEXT25:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT9]](i16)
- ; CHECK-NEXT: $vgpr9 = COPY [[ANYEXT25]](s32)
- ; CHECK-NEXT: [[ANYEXT26:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT10]](i16)
- ; CHECK-NEXT: $vgpr10 = COPY [[ANYEXT26]](s32)
- ; CHECK-NEXT: [[ANYEXT27:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT11]](i16)
- ; CHECK-NEXT: $vgpr11 = COPY [[ANYEXT27]](s32)
- ; CHECK-NEXT: [[ANYEXT28:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT12]](i16)
- ; CHECK-NEXT: $vgpr12 = COPY [[ANYEXT28]](s32)
- ; CHECK-NEXT: [[ANYEXT29:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT13]](i16)
- ; CHECK-NEXT: $vgpr13 = COPY [[ANYEXT29]](s32)
- ; CHECK-NEXT: [[ANYEXT30:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT14]](i16)
- ; CHECK-NEXT: $vgpr14 = COPY [[ANYEXT30]](s32)
- ; CHECK-NEXT: [[ANYEXT31:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT15]](i16)
- ; CHECK-NEXT: $vgpr15 = COPY [[ANYEXT31]](s32)
+ ; CHECK-NEXT: [[ANYEXT16:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT]](i16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT16]](i32)
+ ; CHECK-NEXT: [[ANYEXT17:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT1]](i16)
+ ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT17]](i32)
+ ; CHECK-NEXT: [[ANYEXT18:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT2]](i16)
+ ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT18]](i32)
+ ; CHECK-NEXT: [[ANYEXT19:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT3]](i16)
+ ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT19]](i32)
+ ; CHECK-NEXT: [[ANYEXT20:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT4]](i16)
+ ; CHECK-NEXT: $vgpr4 = COPY [[ANYEXT20]](i32)
+ ; CHECK-NEXT: [[ANYEXT21:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT5]](i16)
+ ; CHECK-NEXT: $vgpr5 = COPY [[ANYEXT21]](i32)
+ ; CHECK-NEXT: [[ANYEXT22:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT6]](i16)
+ ; CHECK-NEXT: $vgpr6 = COPY [[ANYEXT22]](i32)
+ ; CHECK-NEXT: [[ANYEXT23:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT7]](i16)
+ ; CHECK-NEXT: $vgpr7 = COPY [[ANYEXT23]](i32)
+ ; CHECK-NEXT: [[ANYEXT24:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT8]](i16)
+ ; CHECK-NEXT: $vgpr8 = COPY [[ANYEXT24]](i32)
+ ; CHECK-NEXT: [[ANYEXT25:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT9]](i16)
+ ; CHECK-NEXT: $vgpr9 = COPY [[ANYEXT25]](i32)
+ ; CHECK-NEXT: [[ANYEXT26:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT10]](i16)
+ ; CHECK-NEXT: $vgpr10 = COPY [[ANYEXT26]](i32)
+ ; CHECK-NEXT: [[ANYEXT27:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT11]](i16)
+ ; CHECK-NEXT: $vgpr11 = COPY [[ANYEXT27]](i32)
+ ; CHECK-NEXT: [[ANYEXT28:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT12]](i16)
+ ; CHECK-NEXT: $vgpr12 = COPY [[ANYEXT28]](i32)
+ ; CHECK-NEXT: [[ANYEXT29:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT13]](i16)
+ ; CHECK-NEXT: $vgpr13 = COPY [[ANYEXT29]](i32)
+ ; CHECK-NEXT: [[ANYEXT30:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT14]](i16)
+ ; CHECK-NEXT: $vgpr14 = COPY [[ANYEXT30]](i32)
+ ; CHECK-NEXT: [[ANYEXT31:%[0-9]+]]:_(i32) = G_ANYEXT [[ANYEXT15]](i16)
+ ; CHECK-NEXT: $vgpr15 = COPY [[ANYEXT31]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -4629,7 +4629,7 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v16i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -4671,26 +4671,26 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C3]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32), [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32), [[UV18:%[0-9]+]]:_(i32), [[UV19:%[0-9]+]]:_(i32), [[UV20:%[0-9]+]]:_(i32), [[UV21:%[0-9]+]]:_(i32), [[UV22:%[0-9]+]]:_(i32), [[UV23:%[0-9]+]]:_(i32), [[UV24:%[0-9]+]]:_(i32), [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32), [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD]](<32 x i32>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](i32)
; CHECK-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD2]](p5) :: (store (i32) into stack, align 16, addrspace 5)
; CHECK-NEXT: [[UV32:%[0-9]+]]:_(i32), [[UV33:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[LOAD1]](f64)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C5]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C5]](i32)
; CHECK-NEXT: G_STORE [[UV32]](i32), [[PTR_ADD3]](p5) :: (store (i32) into stack + 4, addrspace 5)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](i32)
; CHECK-NEXT: G_STORE [[UV33]](i32), [[PTR_ADD4]](p5) :: (store (i32) into stack + 8, align 8, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -4733,7 +4733,7 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @stack_passed_f64_arg, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 12, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -4747,7 +4747,7 @@ define void @stack_12xv3i32() #0 {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -4794,7 +4794,7 @@ define void @stack_12xv3i32() #0 {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x i32>)
; CHECK-NEXT: [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<3 x i32>)
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<3 x i32>)
@@ -4807,21 +4807,21 @@ define void @stack_12xv3i32() #0 {
; CHECK-NEXT: [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR9]](<3 x i32>)
; CHECK-NEXT: [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32), [[UV32:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR10]](<3 x i32>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](s32)
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](i32)
; CHECK-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD]](p5) :: (store (i32) into stack, align 16, addrspace 5)
- ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](s32)
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](i32)
; CHECK-NEXT: G_STORE [[UV32]](i32), [[PTR_ADD1]](p5) :: (store (i32) into stack + 4, addrspace 5)
; CHECK-NEXT: [[UV33:%[0-9]+]]:_(i32), [[UV34:%[0-9]+]]:_(i32), [[UV35:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR11]](<3 x i32>)
- ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](s32)
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](i32)
; CHECK-NEXT: G_STORE [[UV33]](i32), [[PTR_ADD2]](p5) :: (store (i32) into stack + 8, align 8, addrspace 5)
- ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](s32)
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](i32)
; CHECK-NEXT: G_STORE [[UV34]](i32), [[PTR_ADD3]](p5) :: (store (i32) into stack + 12, addrspace 5)
- ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](s32)
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](i32)
; CHECK-NEXT: G_STORE [[UV35]](i32), [[PTR_ADD4]](p5) :: (store (i32) into stack + 16, align 16, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -4864,7 +4864,7 @@ define void @stack_12xv3i32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_12xv3i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 20, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -4890,7 +4890,7 @@ define void @stack_12xv3f32() #0 {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -4937,7 +4937,7 @@ define void @stack_12xv3f32() #0 {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x f32>)
; CHECK-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<3 x f32>)
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<3 x f32>)
@@ -4950,21 +4950,21 @@ define void @stack_12xv3f32() #0 {
; CHECK-NEXT: [[UV27:%[0-9]+]]:_(f32), [[UV28:%[0-9]+]]:_(f32), [[UV29:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR9]](<3 x f32>)
; CHECK-NEXT: [[UV30:%[0-9]+]]:_(f32), [[UV31:%[0-9]+]]:_(f32), [[UV32:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR10]](<3 x f32>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](s32)
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](i32)
; CHECK-NEXT: G_STORE [[UV31]](f32), [[PTR_ADD]](p5) :: (store (f32) into stack, align 16, addrspace 5)
- ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](s32)
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](i32)
; CHECK-NEXT: G_STORE [[UV32]](f32), [[PTR_ADD1]](p5) :: (store (f32) into stack + 4, addrspace 5)
; CHECK-NEXT: [[UV33:%[0-9]+]]:_(f32), [[UV34:%[0-9]+]]:_(f32), [[UV35:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR11]](<3 x f32>)
- ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](s32)
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](i32)
; CHECK-NEXT: G_STORE [[UV33]](f32), [[PTR_ADD2]](p5) :: (store (f32) into stack + 8, align 8, addrspace 5)
- ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](s32)
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](i32)
; CHECK-NEXT: G_STORE [[UV34]](f32), [[PTR_ADD3]](p5) :: (store (f32) into stack + 12, addrspace 5)
- ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](s32)
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](i32)
; CHECK-NEXT: G_STORE [[UV35]](f32), [[PTR_ADD4]](p5) :: (store (f32) into stack + 16, align 16, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](f32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5007,7 +5007,7 @@ define void @stack_12xv3f32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_12xv3f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 20, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5033,7 +5033,7 @@ define void @stack_8xv5i32() #0 {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5076,7 +5076,7 @@ define void @stack_8xv5i32() #0 {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x i32>)
; CHECK-NEXT: [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32), [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<5 x i32>)
; CHECK-NEXT: [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32), [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<5 x i32>)
@@ -5085,33 +5085,33 @@ define void @stack_8xv5i32() #0 {
; CHECK-NEXT: [[UV25:%[0-9]+]]:_(i32), [[UV26:%[0-9]+]]:_(i32), [[UV27:%[0-9]+]]:_(i32), [[UV28:%[0-9]+]]:_(i32), [[UV29:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<5 x i32>)
; CHECK-NEXT: [[UV30:%[0-9]+]]:_(i32), [[UV31:%[0-9]+]]:_(i32), [[UV32:%[0-9]+]]:_(i32), [[UV33:%[0-9]+]]:_(i32), [[UV34:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<5 x i32>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](s32)
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](i32)
; CHECK-NEXT: G_STORE [[UV31]](i32), [[PTR_ADD]](p5) :: (store (i32) into stack, align 16, addrspace 5)
- ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](s32)
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](i32)
; CHECK-NEXT: G_STORE [[UV32]](i32), [[PTR_ADD1]](p5) :: (store (i32) into stack + 4, addrspace 5)
- ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](s32)
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](i32)
; CHECK-NEXT: G_STORE [[UV33]](i32), [[PTR_ADD2]](p5) :: (store (i32) into stack + 8, align 8, addrspace 5)
- ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](s32)
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](i32)
; CHECK-NEXT: G_STORE [[UV34]](i32), [[PTR_ADD3]](p5) :: (store (i32) into stack + 12, addrspace 5)
; CHECK-NEXT: [[UV35:%[0-9]+]]:_(i32), [[UV36:%[0-9]+]]:_(i32), [[UV37:%[0-9]+]]:_(i32), [[UV38:%[0-9]+]]:_(i32), [[UV39:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<5 x i32>)
- ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](s32)
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](i32)
; CHECK-NEXT: G_STORE [[UV35]](i32), [[PTR_ADD4]](p5) :: (store (i32) into stack + 16, align 16, addrspace 5)
- ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C21]](s32)
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C21]](i32)
; CHECK-NEXT: G_STORE [[UV36]](i32), [[PTR_ADD5]](p5) :: (store (i32) into stack + 20, addrspace 5)
- ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C22]](s32)
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(i32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C22]](i32)
; CHECK-NEXT: G_STORE [[UV37]](i32), [[PTR_ADD6]](p5) :: (store (i32) into stack + 24, align 8, addrspace 5)
- ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C23]](s32)
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(i32) = G_CONSTANT i32 28
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C23]](i32)
; CHECK-NEXT: G_STORE [[UV38]](i32), [[PTR_ADD7]](p5) :: (store (i32) into stack + 28, addrspace 5)
- ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C24]](s32)
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C24]](i32)
; CHECK-NEXT: G_STORE [[UV39]](i32), [[PTR_ADD8]](p5) :: (store (i32) into stack + 32, align 16, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -5154,7 +5154,7 @@ define void @stack_8xv5i32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_8xv5i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 36, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5176,7 +5176,7 @@ define void @stack_8xv5f32() #0 {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5219,7 +5219,7 @@ define void @stack_8xv5f32() #0 {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x f32>)
; CHECK-NEXT: [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32), [[UV9:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<5 x f32>)
; CHECK-NEXT: [[UV10:%[0-9]+]]:_(f32), [[UV11:%[0-9]+]]:_(f32), [[UV12:%[0-9]+]]:_(f32), [[UV13:%[0-9]+]]:_(f32), [[UV14:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<5 x f32>)
@@ -5228,33 +5228,33 @@ define void @stack_8xv5f32() #0 {
; CHECK-NEXT: [[UV25:%[0-9]+]]:_(f32), [[UV26:%[0-9]+]]:_(f32), [[UV27:%[0-9]+]]:_(f32), [[UV28:%[0-9]+]]:_(f32), [[UV29:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<5 x f32>)
; CHECK-NEXT: [[UV30:%[0-9]+]]:_(f32), [[UV31:%[0-9]+]]:_(f32), [[UV32:%[0-9]+]]:_(f32), [[UV33:%[0-9]+]]:_(f32), [[UV34:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<5 x f32>)
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](s32)
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](i32)
; CHECK-NEXT: G_STORE [[UV31]](f32), [[PTR_ADD]](p5) :: (store (f32) into stack, align 16, addrspace 5)
- ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](s32)
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](i32)
; CHECK-NEXT: G_STORE [[UV32]](f32), [[PTR_ADD1]](p5) :: (store (f32) into stack + 4, addrspace 5)
- ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](s32)
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](i32)
; CHECK-NEXT: G_STORE [[UV33]](f32), [[PTR_ADD2]](p5) :: (store (f32) into stack + 8, align 8, addrspace 5)
- ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](s32)
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](i32)
; CHECK-NEXT: G_STORE [[UV34]](f32), [[PTR_ADD3]](p5) :: (store (f32) into stack + 12, addrspace 5)
; CHECK-NEXT: [[UV35:%[0-9]+]]:_(f32), [[UV36:%[0-9]+]]:_(f32), [[UV37:%[0-9]+]]:_(f32), [[UV38:%[0-9]+]]:_(f32), [[UV39:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<5 x f32>)
- ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](s32)
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](i32)
; CHECK-NEXT: G_STORE [[UV35]](f32), [[PTR_ADD4]](p5) :: (store (f32) into stack + 16, align 16, addrspace 5)
- ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C21]](s32)
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C21]](i32)
; CHECK-NEXT: G_STORE [[UV36]](f32), [[PTR_ADD5]](p5) :: (store (f32) into stack + 20, addrspace 5)
- ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C22]](s32)
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(i32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C22]](i32)
; CHECK-NEXT: G_STORE [[UV37]](f32), [[PTR_ADD6]](p5) :: (store (f32) into stack + 24, align 8, addrspace 5)
- ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C23]](s32)
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(i32) = G_CONSTANT i32 28
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C23]](i32)
; CHECK-NEXT: G_STORE [[UV38]](f32), [[PTR_ADD7]](p5) :: (store (f32) into stack + 28, addrspace 5)
- ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C24]](s32)
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C24]](i32)
; CHECK-NEXT: G_STORE [[UV39]](f32), [[PTR_ADD8]](p5) :: (store (f32) into stack + 32, align 16, addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](f32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5297,7 +5297,7 @@ define void @stack_8xv5f32() #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_8xv5f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 36, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5329,9 +5329,9 @@ define amdgpu_ps void @amdgpu_ps_call_default_cc() {
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF2]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF2]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF2]](s32)
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[DEF2]](s32)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
- ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY6]](<4 x s32>)
+ ; CHECK-NEXT: [[DEF3:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
+ ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY5]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[DEF]](p4)
; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY]](p4)
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY1]](p4)
@@ -5340,7 +5340,7 @@ define amdgpu_ps void @amdgpu_ps_call_default_cc() {
; CHECK-NEXT: $sgpr13 = COPY [[COPY2]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY3]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY4]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY5]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[DEF3]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[C]](p0), 0, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
@@ -5354,7 +5354,7 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5363,8 +5363,8 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 {
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i16_inreg
; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
@@ -5375,10 +5375,10 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](i16)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](s32)
- ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](i32)
+ ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -5389,7 +5389,7 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i16_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5402,7 +5402,7 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5422,7 +5422,7 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](i32)
; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
@@ -5435,7 +5435,7 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5448,7 +5448,7 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5470,7 +5470,7 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 {
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[MV]](i64)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32)
; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
@@ -5486,7 +5486,7 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i64_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr17, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5499,7 +5499,7 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5521,7 +5521,7 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 {
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x i32>)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32)
; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
@@ -5537,7 +5537,7 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i32_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr17, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5550,7 +5550,7 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5559,8 +5559,9 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY9]](s32)
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_f16_inreg
; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
@@ -5571,10 +5572,10 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](f16)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](s32)
- ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](f16)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](i32)
+ ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -5585,7 +5586,7 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f16_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5598,7 +5599,7 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5607,8 +5608,9 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 {
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(bf16) = G_TRUNC [[COPY9]](s32)
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(bf16) = G_BITCAST [[TRUNC]](i16)
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_bf16_inreg
; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
@@ -5619,10 +5621,10 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](bf16)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](s32)
- ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](bf16)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](i32)
+ ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -5633,7 +5635,7 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_bf16_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5646,7 +5648,7 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5666,7 +5668,7 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(f32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](f32)
; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](f32)
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
@@ -5679,7 +5681,7 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f32_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5692,7 +5694,7 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5714,7 +5716,7 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 {
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[MV]](f64)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32)
; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
@@ -5730,7 +5732,7 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f64_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr17, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5743,7 +5745,7 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5763,10 +5765,10 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x f16>)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32)
- ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x f16>)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](i32)
+ ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -5777,7 +5779,7 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2f16_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5790,7 +5792,7 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5814,17 +5816,17 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(f16), [[UV5:%[0-9]+]]:_(f16), [[UV6:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x f16>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV4]](f16), [[UV5]](f16), [[UV6]](f16), [[DEF]](f16)
; CHECK-NEXT: [[UV7:%[0-9]+]]:_(<2 x f16>), [[UV8:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x f16>)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x f16>)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32)
- ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](s32)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x f16>)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST1]](s32)
- ; CHECK-NEXT: $sgpr17 = COPY [[INTRINSIC_CONVERGENT1]](s32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV7]](<2 x f16>)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](i32)
+ ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV8]](<2 x f16>)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST1]](i32)
+ ; CHECK-NEXT: $sgpr17 = COPY [[INTRINSIC_CONVERGENT1]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
@@ -5835,7 +5837,7 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0
; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3f16_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr17, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5848,7 +5850,7 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5870,14 +5872,14 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x f16>)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x f16>)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32)
- ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](s32)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x f16>)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST1]](s32)
- ; CHECK-NEXT: $sgpr17 = COPY [[INTRINSIC_CONVERGENT1]](s32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](i32)
+ ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST1]](i32)
+ ; CHECK-NEXT: $sgpr17 = COPY [[INTRINSIC_CONVERGENT1]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
@@ -5888,7 +5890,7 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0
; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4f16_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr17, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5901,7 +5903,7 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5923,7 +5925,7 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 {
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[MV]](p0)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32)
; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
@@ -5939,7 +5941,7 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 {
; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_p0_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr17, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -5952,7 +5954,7 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg)
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -5974,7 +5976,7 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg)
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[MV]](p1)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32)
; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
@@ -5990,7 +5992,7 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg)
; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_p1_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr17, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -6003,7 +6005,7 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg)
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -6023,10 +6025,10 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg)
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY9]](p3)
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[PTRTOINT]](s32)
- ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY9]](p3)
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[PTRTOINT]](i32)
+ ; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -6037,7 +6039,7 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg)
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_p3_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -6050,7 +6052,7 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -6076,7 +6078,7 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x p1>)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32)
; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
@@ -6096,7 +6098,7 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre
; CHECK-NEXT: $sgpr13 = COPY [[COPY18]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY19]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY20]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY21]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY21]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2p1_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
@@ -6109,7 +6111,7 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -6131,7 +6133,7 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x p5>)
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32)
; CHECK-NEXT: $sgpr16 = COPY [[INTRINSIC_CONVERGENT]](i32)
@@ -6147,7 +6149,7 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre
; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2p5_inreg, csr_amdgpu, implicit $sgpr16, implicit $sgpr17, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: SI_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
index f927b72e7d780..f9ee0e3cfc25a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
@@ -126,8 +126,8 @@ define void @void_func_i8(i8 %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC]](i16)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK-NEXT: G_STORE [[TRUNC1]](i8), [[DEF]](p1) :: (store (i8) into `ptr addrspace(1) poison`, addrspace 1)
@@ -181,8 +181,8 @@ define void @void_func_i16(i16 %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK-NEXT: G_STORE [[TRUNC]](i16), [[DEF]](p1) :: (store (i16) into `ptr addrspace(1) poison`, addrspace 1)
; CHECK-NEXT: SI_RETURN
@@ -513,10 +513,11 @@ define void @void_func_f16(half %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[TRUNC]](f16), [[DEF]](p1) :: (store (f16) into `ptr addrspace(1) poison`, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](f16), [[DEF]](p1) :: (store (f16) into `ptr addrspace(1) poison`, addrspace 1)
; CHECK-NEXT: SI_RETURN
store half %arg0, ptr addrspace(1) poison
ret void
@@ -603,10 +604,10 @@ define void @void_func_v2i8(<2 x i8> %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<2 x i8>) = G_TRUNC [[BUILD_VECTOR]](<2 x i16>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
@@ -621,12 +622,12 @@ define void @void_func_v3i8(<3 x i8> %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY2]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16), [[TRUNC2]](i16)
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(<3 x i8>) = G_TRUNC [[BUILD_VECTOR]](<3 x i16>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
@@ -641,14 +642,14 @@ define void @void_func_v4i8(<4 x i8> %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY3]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY2]](i32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY3]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16), [[TRUNC2]](i16), [[TRUNC3]](i16)
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(<4 x i8>) = G_TRUNC [[BUILD_VECTOR]](<4 x i16>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
@@ -1639,8 +1640,8 @@ define void @void_func_struct_i8_i32({ i8, i32 } %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC]](i16)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
@@ -2593,38 +2594,38 @@ define void @void_func_v16i8(<16 x i8> %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY3]](s32)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](s32)
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY5]](s32)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY6]](s32)
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[COPY7]](s32)
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY8]](s32)
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9
- ; CHECK-NEXT: [[TRUNC9:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10
- ; CHECK-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11
- ; CHECK-NEXT: [[TRUNC11:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12
- ; CHECK-NEXT: [[TRUNC12:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
- ; CHECK-NEXT: [[TRUNC13:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](s32)
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
- ; CHECK-NEXT: [[TRUNC14:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](s32)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
- ; CHECK-NEXT: [[TRUNC15:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY2]](i32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY3]](i32)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY5]](i32)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY6]](i32)
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[COPY7]](i32)
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY8]](i32)
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr9
+ ; CHECK-NEXT: [[TRUNC9:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr10
+ ; CHECK-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr11
+ ; CHECK-NEXT: [[TRUNC11:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr12
+ ; CHECK-NEXT: [[TRUNC12:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr13
+ ; CHECK-NEXT: [[TRUNC13:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr14
+ ; CHECK-NEXT: [[TRUNC14:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr15
+ ; CHECK-NEXT: [[TRUNC15:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16), [[TRUNC2]](i16), [[TRUNC3]](i16), [[TRUNC4]](i16), [[TRUNC5]](i16), [[TRUNC6]](i16), [[TRUNC7]](i16), [[TRUNC8]](i16), [[TRUNC9]](i16), [[TRUNC10]](i16), [[TRUNC11]](i16), [[TRUNC12]](i16), [[TRUNC13]](i16), [[TRUNC14]](i16), [[TRUNC15]](i16)
; CHECK-NEXT: [[TRUNC16:%[0-9]+]]:_(<16 x i8>) = G_TRUNC [[BUILD_VECTOR]](<16 x i16>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
@@ -2726,8 +2727,8 @@ define void @pointer_in_struct_argument({ptr addrspace(3), ptr addrspace(1)} %ar
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY3]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY3]](i32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC]](i16)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p3) = COPY $vgpr4
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
@@ -2796,8 +2797,8 @@ define void @void_func_i8_inreg(i8 inreg %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr16
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[TRUNC]](i16)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK-NEXT: G_STORE [[TRUNC1]](i8), [[DEF]](p1) :: (store (i8) into `ptr addrspace(1) poison`, addrspace 1)
@@ -2811,8 +2812,8 @@ define void @void_func_i16_inreg(i16 inreg %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr16
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK-NEXT: G_STORE [[TRUNC]](i16), [[DEF]](p1) :: (store (i16) into `ptr addrspace(1) poison`, addrspace 1)
; CHECK-NEXT: SI_RETURN
@@ -2902,10 +2903,11 @@ define void @void_func_f16_inreg(half inreg %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr16
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[TRUNC]](f16), [[DEF]](p1) :: (store (f16) into `ptr addrspace(1) poison`, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](f16), [[DEF]](p1) :: (store (f16) into `ptr addrspace(1) poison`, addrspace 1)
; CHECK-NEXT: SI_RETURN
store half %arg0, ptr addrspace(1) poison
ret void
@@ -2916,10 +2918,11 @@ define void @void_func_bf16_inreg(bfloat inreg %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr16
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(bf16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(bf16) = G_BITCAST [[TRUNC]](i16)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[TRUNC]](bf16), [[DEF]](p1) :: (store (bf16) into `ptr addrspace(1) poison`, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](bf16), [[DEF]](p1) :: (store (bf16) into `ptr addrspace(1) poison`, addrspace 1)
; CHECK-NEXT: SI_RETURN
store bfloat %arg0, ptr addrspace(1) poison
ret void
@@ -2958,10 +2961,10 @@ define void @void_func_v2i1_inreg(<2 x i1> inreg %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr16, $sgpr17
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr17
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr17
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<2 x i1>) = G_TRUNC [[BUILD_VECTOR]](<2 x i16>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
@@ -2977,10 +2980,10 @@ define void @void_func_v2i8_inreg(<2 x i8> inreg %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr16, $sgpr17
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr17
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr17
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<2 x i8>) = G_TRUNC [[BUILD_VECTOR]](<2 x i16>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
@@ -3251,11 +3254,11 @@ define void @void_readlane_i1_signext_inreg(<15 x i32> inreg %arg1, i1 inreg sig
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr27
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $sgpr28
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $sgpr29
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<15 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32), [[COPY12]](i32), [[COPY13]](i32), [[INTRINSIC_CONVERGENT]](i32)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[INTRINSIC_CONVERGENT1]], 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_SEXT]](i32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
@@ -3289,11 +3292,11 @@ define void @void_readlane_i1_zeroext_inreg(<15 x i32> inreg %arg1, i1 inreg zer
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr27
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $sgpr28
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $sgpr29
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<15 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32), [[COPY12]](i32), [[COPY13]](i32), [[INTRINSIC_CONVERGENT]](i32)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[INTRINSIC_CONVERGENT1]], 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_ZEXT]](i32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
@@ -3328,11 +3331,11 @@ define void @void_readlane_i8_signext_inreg(<15 x i32> inreg %arg1, i8 inreg sig
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr27
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $sgpr28
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $sgpr29
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<15 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32), [[COPY12]](i32), [[COPY13]](i32), [[INTRINSIC_CONVERGENT]](i32)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[INTRINSIC_CONVERGENT1]], 8
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT]](i32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
@@ -3366,11 +3369,11 @@ define void @void_readlane_i8_zeroext_inreg(<15 x i32> inreg %arg1, i8 inreg zer
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr27
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $sgpr28
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $sgpr29
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<15 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32), [[COPY12]](i32), [[COPY13]](i32), [[INTRINSIC_CONVERGENT]](i32)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[INTRINSIC_CONVERGENT1]], 8
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_ZEXT]](i32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
@@ -3405,11 +3408,11 @@ define void @void_readlane_i16_signext_inreg(<15 x i32> inreg %arg1, i16 inreg s
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr27
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $sgpr28
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $sgpr29
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<15 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32), [[COPY12]](i32), [[COPY13]](i32), [[INTRINSIC_CONVERGENT]](i32)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[INTRINSIC_CONVERGENT1]], 16
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_SEXT]](i32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
@@ -3443,11 +3446,11 @@ define void @void_readlane_i16_zeroext_inreg(<15 x i32> inreg %arg1, i16 inreg z
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr27
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $sgpr28
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $sgpr29
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<15 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32), [[COPY12]](i32), [[COPY13]](i32), [[INTRINSIC_CONVERGENT]](i32)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[INTRINSIC_CONVERGENT1]], 16
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_ZEXT]](i32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
@@ -3481,16 +3484,17 @@ define void @void_readlane_halfinreg_bitcast_inreg(<15 x i32> inreg %arg1, half
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr27
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $sgpr28
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $sgpr29
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<15 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32), [[COPY12]](i32), [[COPY13]](i32), [[INTRINSIC_CONVERGENT]](i32)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[INTRINSIC_CONVERGENT1]](s32)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[INTRINSIC_CONVERGENT1]](i32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i16) = G_BITCAST [[TRUNC]](f16)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[BITCAST]](i16)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST]](f16)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[BITCAST1]](i16)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[ZEXT]], [[C]]
; CHECK-NEXT: G_STORE [[ADD]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1)
; CHECK-NEXT: SI_RETURN
@@ -3520,16 +3524,17 @@ define void @void_readlane_bfloat_inreg_bitcast_zext(<15 x i32> inreg %arg1, bfl
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr27
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $sgpr28
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $sgpr29
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32)
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<15 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32), [[COPY12]](i32), [[COPY13]](i32), [[INTRINSIC_CONVERGENT]](i32)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(bf16) = G_TRUNC [[INTRINSIC_CONVERGENT1]](s32)
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[INTRINSIC_CONVERGENT1]](i32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(bf16) = G_BITCAST [[TRUNC]](i16)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i16) = G_BITCAST [[TRUNC]](bf16)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[BITCAST]](i16)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST]](bf16)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[BITCAST1]](i16)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[ZEXT]], [[C]]
; CHECK-NEXT: G_STORE [[ADD]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1)
; CHECK-NEXT: SI_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
index 6e5ab6dc5663d..c21c5ecea2f7d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
@@ -29,15 +29,15 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr(ptr %fptr) {
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY18]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY17]], [[SHL]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -48,7 +48,7 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr(ptr %fptr) {
; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[LOAD]](p0), 0, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
index 02a1e973a2193..ad0e90b12aef0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
@@ -371,8 +371,8 @@ define void @test_indirectify_i16_value(i16 %val) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[TRUNC]](i16), [[FRAME_INDEX]](p5) :: (store (i16) into %stack.0, addrspace 5)
; CHECK-NEXT: INLINEASM &"", sideeffect mayload maystore attdialect, mem:m, [[FRAME_INDEX]](p5)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
index ff133ca760055..beff4b73cc437 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
@@ -188,8 +188,8 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, pt
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_fastcc_i32_byval_i32
; GCN-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C]](s32)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C]](i32)
; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
; GCN-NEXT: G_MEMCPY [[PTR_ADD]](p5), [[COPY1]](p5), [[C1]](i32), 0 :: (dereferenceable store (s32) into stack, addrspace 5), (dereferenceable load (s32) from %ir.b.byval, addrspace 5)
; GCN-NEXT: $vgpr0 = COPY [[COPY]](i32)
@@ -516,14 +516,14 @@ define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 {
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_fastcc_i32_i32_a32i32
; GCN-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C1]](s32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C1]](i32)
; GCN-NEXT: G_STORE [[C]](i32), [[PTR_ADD]](p5) :: (store (i32) into stack, align 16, addrspace 5)
- ; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; GCN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C2]](s32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; GCN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C2]](i32)
; GCN-NEXT: G_STORE [[C]](i32), [[PTR_ADD1]](p5) :: (store (i32) into stack + 4, addrspace 5)
- ; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; GCN-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)
+ ; GCN-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; GCN-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](i32)
; GCN-NEXT: G_STORE [[C]](i32), [[PTR_ADD2]](p5) :: (store (i32) into stack + 8, align 8, addrspace 5)
; GCN-NEXT: $vgpr0 = COPY [[COPY]](i32)
; GCN-NEXT: $vgpr1 = COPY [[COPY1]](i32)
@@ -809,7 +809,7 @@ define fastcc void @sibling_call_fastcc_multi_byval(i32 %a, [64 x i32]) #1 {
; GCN: bb.1.entry:
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr15
; GCN-NEXT: [[COPY2:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr14
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr13
@@ -940,7 +940,7 @@ define fastcc void @sibling_call_fastcc_multi_byval(i32 %a, [64 x i32]) #1 {
; GCN-NEXT: [[COPY45:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GCN-NEXT: [[COPY46:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY47:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[COPY48:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[COPY48:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GCN-NEXT: [[FRAME_INDEX36:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; GCN-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
; GCN-NEXT: G_MEMCPY [[FRAME_INDEX36]](p5), [[FRAME_INDEX34]](p5), [[C4]](i32), 0 :: (dereferenceable store (s96) into %fixed-stack.1, align 16, addrspace 5), (dereferenceable load (s96) from %ir.alloca0, align 16, addrspace 5)
@@ -958,7 +958,7 @@ define fastcc void @sibling_call_fastcc_multi_byval(i32 %a, [64 x i32]) #1 {
; GCN-NEXT: $sgpr13 = COPY [[COPY45]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY46]](s32)
; GCN-NEXT: $sgpr15 = COPY [[COPY47]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[COPY48]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[COPY48]](i32)
; GCN-NEXT: SI_TCRETURN [[GV]](p0), @void_fastcc_multi_byval, 0, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
entry:
%alloca0 = alloca [3 x i32], align 16, addrspace(5)
@@ -977,7 +977,7 @@ define fastcc void @sibling_call_byval_and_stack_passed(i32 %stack.out.arg, [64
; GCN: bb.1.entry:
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr15
; GCN-NEXT: [[COPY2:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr14
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr13
@@ -1104,7 +1104,7 @@ define fastcc void @sibling_call_byval_and_stack_passed(i32 %stack.out.arg, [64
; GCN-NEXT: [[COPY45:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GCN-NEXT: [[COPY46:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY47:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[COPY48:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[COPY48:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GCN-NEXT: [[FRAME_INDEX35:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; GCN-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
; GCN-NEXT: G_MEMCPY [[FRAME_INDEX35]](p5), [[FRAME_INDEX34]](p5), [[C4]](i32), 0 :: (dereferenceable store (s96) into %fixed-stack.2, align 16, addrspace 5), (dereferenceable load (s96) from %ir.alloca, align 16, addrspace 5)
@@ -1153,7 +1153,7 @@ define fastcc void @sibling_call_byval_and_stack_passed(i32 %stack.out.arg, [64
; GCN-NEXT: $sgpr13 = COPY [[COPY45]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY46]](s32)
; GCN-NEXT: $sgpr15 = COPY [[COPY47]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[COPY48]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[COPY48]](i32)
; GCN-NEXT: SI_TCRETURN [[GV]](p0), @void_fastcc_byval_and_stack_passed, 0, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
entry:
%alloca = alloca [3 x i32], align 16, addrspace(5)
@@ -1169,7 +1169,7 @@ define hidden fastcc i64 @sibling_call_i64_fastcc_i64(i64 %a) #1 {
; GCN: bb.1.entry:
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr15
; GCN-NEXT: [[COPY2:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr14
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr13
@@ -1190,7 +1190,7 @@ define hidden fastcc i64 @sibling_call_i64_fastcc_i64(i64 %a) #1 {
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GCN-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[MV]](i64)
; GCN-NEXT: $vgpr0 = COPY [[UV]](i32)
; GCN-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1204,7 +1204,7 @@ define hidden fastcc i64 @sibling_call_i64_fastcc_i64(i64 %a) #1 {
; GCN-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; GCN-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; GCN-NEXT: SI_TCRETURN [[GV]](p0), @i64_fastcc_i64, 0, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
entry:
%ret = tail call fastcc i64 @i64_fastcc_i64(i64 %a)
@@ -1240,7 +1240,7 @@ define hidden fastcc i16 @sibling_call_i16_fastcc_i16(i16 %a) #1 {
; GCN: bb.1.entry:
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr15
; GCN-NEXT: [[COPY2:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr14
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr13
@@ -1249,8 +1249,8 @@ define hidden fastcc i16 @sibling_call_i16_fastcc_i16(i16 %a) #1 {
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GCN-NEXT: [[GV:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @i16_fastcc_i16
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]](p4)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]](p4)
@@ -1260,9 +1260,9 @@ define hidden fastcc i16 @sibling_call_i16_fastcc_i16(i16 %a) #1 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](i16)
- ; GCN-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
+ ; GCN-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
+ ; GCN-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1273,7 +1273,7 @@ define hidden fastcc i16 @sibling_call_i16_fastcc_i16(i16 %a) #1 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; GCN-NEXT: SI_TCRETURN [[GV]](p0), @i16_fastcc_i16, 0, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
entry:
%ret = tail call fastcc i16 @i16_fastcc_i16(i16 %a)
@@ -1287,7 +1287,7 @@ define hidden fastcc half @sibling_call_f16_fastcc_f16(half %a) #1 {
; GCN: bb.1.entry:
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr15
; GCN-NEXT: [[COPY2:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr14
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr13
@@ -1296,8 +1296,9 @@ define hidden fastcc half @sibling_call_f16_fastcc_f16(half %a) #1 {
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY9]](s32)
+ ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GCN-NEXT: [[GV:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @f16_fastcc_f16
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]](p4)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]](p4)
@@ -1307,9 +1308,9 @@ define hidden fastcc half @sibling_call_f16_fastcc_f16(half %a) #1 {
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](f16)
- ; GCN-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GCN-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
+ ; GCN-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](f16)
+ ; GCN-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
@@ -1320,7 +1321,7 @@ define hidden fastcc half @sibling_call_f16_fastcc_f16(half %a) #1 {
; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr15 = COPY [[COPY17]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[COPY18]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[COPY18]](i32)
; GCN-NEXT: SI_TCRETURN [[GV]](p0), @f16_fastcc_f16, 0, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
entry:
%ret = tail call fastcc half @f16_fastcc_f16(half %a)
@@ -1334,7 +1335,7 @@ define hidden fastcc <3 x i16> @sibling_call_v3i16_fastcc_v3i16(<3 x i16> %a) #1
; GCN: bb.1.entry:
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr15
; GCN-NEXT: [[COPY2:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr14
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr13
@@ -1357,7 +1358,7 @@ define hidden fastcc <3 x i16> @sibling_call_v3i16_fastcc_v3i16(<3 x i16> %a) #1
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GCN-NEXT: [[UV4:%[0-9]+]]:_(i16), [[UV5:%[0-9]+]]:_(i16), [[UV6:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x i16>)
; GCN-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i16>) = G_BUILD_VECTOR [[UV4]](i16), [[UV5]](i16), [[UV6]](i16), [[DEF]](i16)
@@ -1374,7 +1375,7 @@ define hidden fastcc <3 x i16> @sibling_call_v3i16_fastcc_v3i16(<3 x i16> %a) #1
; GCN-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; GCN-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; GCN-NEXT: SI_TCRETURN [[GV]](p0), @v3i16_fastcc_v3i16, 0, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
entry:
%ret = tail call fastcc <3 x i16> @v3i16_fastcc_v3i16(<3 x i16> %a)
@@ -1388,7 +1389,7 @@ define hidden fastcc <4 x i16> @sibling_call_v4i16_fastcc_v4i16(<4 x i16> %a) #1
; GCN: bb.1.entry:
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr15
; GCN-NEXT: [[COPY2:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr14
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr13
@@ -1409,7 +1410,7 @@ define hidden fastcc <4 x i16> @sibling_call_v4i16_fastcc_v4i16(<4 x i16> %a) #1
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GCN-NEXT: [[UV:%[0-9]+]]:_(<2 x i16>), [[UV1:%[0-9]+]]:_(<2 x i16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x i16>)
; GCN-NEXT: $vgpr0 = COPY [[UV]](<2 x i16>)
; GCN-NEXT: $vgpr1 = COPY [[UV1]](<2 x i16>)
@@ -1423,7 +1424,7 @@ define hidden fastcc <4 x i16> @sibling_call_v4i16_fastcc_v4i16(<4 x i16> %a) #1
; GCN-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; GCN-NEXT: $sgpr15 = COPY [[COPY18]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[COPY19]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[COPY19]](i32)
; GCN-NEXT: SI_TCRETURN [[GV]](p0), @v4i16_fastcc_v4i16, 0, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
entry:
%ret = tail call fastcc <4 x i16> @v4i16_fastcc_v4i16(<4 x i16> %a)
@@ -1437,7 +1438,7 @@ define hidden fastcc <2 x i64> @sibling_call_v2i64_fastcc_v2i64(<2 x i64> %a) #1
; GCN: bb.1.entry:
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr15
; GCN-NEXT: [[COPY2:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr14
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32(s32) = COPY $sgpr13
@@ -1462,7 +1463,7 @@ define hidden fastcc <2 x i64> @sibling_call_v2i64_fastcc_v2i64(<2 x i64> %a) #1
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; GCN-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x i64>)
; GCN-NEXT: $vgpr0 = COPY [[UV]](i32)
; GCN-NEXT: $vgpr1 = COPY [[UV1]](i32)
@@ -1478,7 +1479,7 @@ define hidden fastcc <2 x i64> @sibling_call_v2i64_fastcc_v2i64(<2 x i64> %a) #1
; GCN-NEXT: $sgpr13 = COPY [[COPY18]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY19]](s32)
; GCN-NEXT: $sgpr15 = COPY [[COPY20]](s32)
- ; GCN-NEXT: $vgpr31 = COPY [[COPY21]](s32)
+ ; GCN-NEXT: $vgpr31 = COPY [[COPY21]](i32)
; GCN-NEXT: SI_TCRETURN [[GV]](p0), @v2i64_fastcc_v2i64, 0, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
entry:
%ret = tail call fastcc <2 x i64> @v2i64_fastcc_v2i64(<2 x i64> %a)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
index 477fcec51886c..c168682bd5618 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
@@ -8,7 +8,7 @@ define void @tail_call_void_func_void() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13
@@ -26,7 +26,7 @@ define void @tail_call_void_func_void() {
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
@@ -37,7 +37,7 @@ define void @tail_call_void_func_void() {
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](i32)
; CHECK-NEXT: SI_TCRETURN [[GV]](p0), @external_void_func_void, 0, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
tail call void @external_void_func_void()
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
index 3022dab3814f7..e1af252a14b1c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
@@ -19,8 +19,8 @@ define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -42,8 +42,8 @@ define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -65,8 +65,8 @@ define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -94,8 +94,8 @@ define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -117,8 +117,8 @@ define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -140,8 +140,8 @@ define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -169,8 +169,8 @@ define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -192,8 +192,8 @@ define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -215,8 +215,8 @@ define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -244,8 +244,8 @@ define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -267,8 +267,8 @@ define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -290,8 +290,8 @@ define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -320,8 +320,8 @@ define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -343,8 +343,8 @@ define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -366,8 +366,8 @@ define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -395,8 +395,8 @@ define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -418,8 +418,8 @@ define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -441,8 +441,8 @@ define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -470,8 +470,8 @@ define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -493,8 +493,8 @@ define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -516,8 +516,8 @@ define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -545,8 +545,8 @@ define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -568,8 +568,8 @@ define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -591,8 +591,8 @@ define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -620,8 +620,8 @@ define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -643,8 +643,8 @@ define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -666,8 +666,8 @@ define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -695,8 +695,8 @@ define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -718,8 +718,8 @@ define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -741,8 +741,8 @@ define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -770,8 +770,8 @@ define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -793,8 +793,8 @@ define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -816,8 +816,8 @@ define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -845,8 +845,8 @@ define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -868,8 +868,8 @@ define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -891,8 +891,8 @@ define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -921,8 +921,8 @@ define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
@@ -946,8 +946,8 @@ define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
@@ -971,8 +971,8 @@ define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
@@ -1001,10 +1001,10 @@ define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32)
@@ -1025,10 +1025,10 @@ define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32)
@@ -1049,10 +1049,10 @@ define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32)
@@ -1079,12 +1079,12 @@ define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1108,12 +1108,12 @@ define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1136,12 +1136,12 @@ define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1170,12 +1170,12 @@ define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i16 %s
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1199,12 +1199,12 @@ define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i16 %s
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1227,12 +1227,12 @@ define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i16 %s
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1261,10 +1261,10 @@ define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32)
@@ -1285,10 +1285,10 @@ define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32)
@@ -1309,10 +1309,10 @@ define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32)
@@ -1339,12 +1339,12 @@ define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1368,12 +1368,12 @@ define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1396,12 +1396,12 @@ define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1430,12 +1430,12 @@ define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1459,12 +1459,12 @@ define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1487,12 +1487,12 @@ define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](s16)
@@ -1521,14 +1521,14 @@ define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data,
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
@@ -1551,14 +1551,14 @@ define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data,
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; GFX10NSA-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; GFX10NSA-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -1580,14 +1580,14 @@ define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data,
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -1615,8 +1615,8 @@ define amdgpu_ps float @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX9-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 2, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -1638,8 +1638,8 @@ define amdgpu_ps float @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10NSA-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 2, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -1661,8 +1661,8 @@ define amdgpu_ps float @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), 0, 2, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -1691,10 +1691,10 @@ define amdgpu_ps float @atomic_cmpswap_2d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -1717,10 +1717,10 @@ define amdgpu_ps float @atomic_cmpswap_2d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -1743,10 +1743,10 @@ define amdgpu_ps float @atomic_cmpswap_2d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8)
@@ -1775,12 +1775,12 @@ define amdgpu_ps float @atomic_cmpswap_3d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -1806,12 +1806,12 @@ define amdgpu_ps float @atomic_cmpswap_3d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; GFX10NSA-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; GFX10NSA-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -1836,12 +1836,12 @@ define amdgpu_ps float @atomic_cmpswap_3d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -1872,14 +1872,14 @@ define amdgpu_ps float @atomic_cmpswap_2darraymsaa(<8 x i32> inreg %rsrc, i32 %c
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](s32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16)
@@ -1904,14 +1904,14 @@ define amdgpu_ps float @atomic_cmpswap_2darraymsaa(<8 x i32> inreg %rsrc, i32 %c
; GFX10NSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10NSA-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX10NSA-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; GFX10NSA-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
- ; GFX10NSA-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](s32)
+ ; GFX10NSA-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX10NSA-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; GFX10NSA-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10NSA-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX10NSA-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16)
@@ -1935,14 +1935,14 @@ define amdgpu_ps float @atomic_cmpswap_2darraymsaa(<8 x i32> inreg %rsrc, i32 %c
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](s32)
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](s32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](s32)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16)
; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
index a2b86d2dad385..ecad137573523 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
@@ -20,8 +20,8 @@ define amdgpu_ps half @image_load_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; UNPACKED-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD_D16_:%[0-9]+]]:_(f16) = G_AMDGPU_INTRIN_IMAGE_LOAD_D16 intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable load (f16), addrspace 8)
- ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD_D16_]](f16)
- ; UNPACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD_D16_]](f16)
+ ; UNPACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
;
; PACKED-LABEL: name: image_load_f16
@@ -41,8 +41,8 @@ define amdgpu_ps half @image_load_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; PACKED-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; PACKED-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD_D16_:%[0-9]+]]:_(f16) = G_AMDGPU_INTRIN_IMAGE_LOAD_D16 intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable load (f16), addrspace 8)
- ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD_D16_]](f16)
- ; PACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD_D16_]](f16)
+ ; PACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
ret half %tex
@@ -488,8 +488,8 @@ define amdgpu_ps half @image_load_f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s,
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; UNPACKED-NEXT: $vgpr0 = COPY [[DEF]](s32)
+ ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; UNPACKED-NEXT: $vgpr0 = COPY [[DEF]](i32)
; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
;
; PACKED-LABEL: name: image_load_f16_dmask_0000
@@ -498,8 +498,8 @@ define amdgpu_ps half @image_load_f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s,
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; PACKED-NEXT: $vgpr0 = COPY [[DEF]](s32)
+ ; PACKED-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; PACKED-NEXT: $vgpr0 = COPY [[DEF]](i32)
; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
ret half %tex
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
index 0a559b4809543..895a50b06d71e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX12 %s
@@ -23,10 +23,11 @@ define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -53,10 +54,11 @@ define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -83,10 +85,11 @@ define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -113,10 +116,11 @@ define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -148,11 +152,13 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -179,11 +185,13 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -210,11 +218,13 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -241,11 +251,13 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -277,15 +289,18 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -313,15 +328,18 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -348,15 +366,18 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -383,15 +404,18 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -423,15 +447,18 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -459,15 +486,18 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -494,15 +524,18 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -529,15 +562,18 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -569,11 +605,13 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -600,11 +638,13 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -631,11 +671,13 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -662,11 +704,13 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -698,15 +742,18 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -734,15 +781,18 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -769,15 +819,18 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -804,15 +857,18 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -845,12 +901,13 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -878,12 +935,13 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -910,12 +968,13 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -942,12 +1001,13 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -979,13 +1039,15 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1013,13 +1075,15 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1046,13 +1110,15 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1079,13 +1145,15 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1116,11 +1184,13 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1147,11 +1217,13 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1178,11 +1250,13 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1209,11 +1283,13 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1245,15 +1321,18 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -1281,15 +1360,18 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1316,15 +1398,18 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1351,15 +1436,18 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1392,13 +1480,15 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1426,13 +1516,15 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1459,13 +1551,15 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1492,13 +1586,15 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1530,17 +1626,20 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1568,17 +1667,20 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1605,17 +1707,20 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1642,17 +1747,20 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1683,13 +1791,15 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -1717,13 +1827,15 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1750,13 +1862,15 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1783,13 +1897,15 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1821,15 +1937,18 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -1857,15 +1976,18 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1892,15 +2014,18 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1927,15 +2052,18 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1967,16 +2095,18 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2003,16 +2133,18 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2038,16 +2170,18 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2073,16 +2207,18 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2113,18 +2249,21 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2151,18 +2290,21 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2188,18 +2330,21 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2225,18 +2370,21 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2267,15 +2415,18 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -2303,15 +2454,18 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2338,15 +2492,18 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2373,15 +2530,18 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2413,18 +2573,22 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -2452,18 +2616,22 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2490,18 +2658,22 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2528,18 +2700,22 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2571,18 +2747,21 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2609,18 +2788,21 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2646,18 +2828,21 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2683,18 +2868,21 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2725,21 +2913,25 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2766,21 +2958,25 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2806,21 +3002,25 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2846,21 +3046,25 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[TRUNC2]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[BITCAST2]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2891,16 +3095,19 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -2928,16 +3135,19 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2964,16 +3174,19 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3000,16 +3213,19 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3041,21 +3257,27 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -3083,21 +3305,27 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3124,21 +3352,27 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3165,21 +3399,27 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3211,31 +3451,40 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX9-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX9-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX9-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX9-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC7]](i16)
+ ; GFX9-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX9-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX9-NEXT: [[BITCAST8:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC8]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[TRUNC7]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC8]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[BITCAST7]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST8]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), [[BUILD_VECTOR6]](<2 x s16>), [[BUILD_VECTOR7]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -3263,31 +3512,40 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC7]](i16)
+ ; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX10-NEXT: [[BITCAST8:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC8]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[TRUNC7]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC8]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[BITCAST7]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST8]](f16), [[DEF]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), [[BUILD_VECTOR6]](<2 x s16>), [[BUILD_VECTOR7]](<2 x s16>)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -3315,31 +3573,40 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX11-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX11-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX11-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC7]](i16)
+ ; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX11-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX11-NEXT: [[BITCAST8:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC8]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[TRUNC7]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC8]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[BITCAST7]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST8]](f16), [[DEF]](s16)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR6]](<2 x s16>), [[BUILD_VECTOR7]](<2 x s16>)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -3367,31 +3634,40 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX12-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX12-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX12-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC7]](i16)
+ ; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX12-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX12-NEXT: [[BITCAST8:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC8]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[TRUNC7]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC8]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[BITCAST7]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST8]](f16), [[DEF]](s16)
; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR5]](<2 x s16>), [[BUILD_VECTOR6]](<2 x s16>), [[BUILD_VECTOR7]](<2 x s16>)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -3425,18 +3701,21 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3464,18 +3743,21 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -3502,18 +3784,21 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -3540,18 +3825,21 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -3583,23 +3871,29 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3627,23 +3921,29 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST6]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -3670,23 +3970,29 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST6]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -3713,23 +4019,29 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST6]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -3760,18 +4072,22 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -3799,18 +4115,22 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3837,18 +4157,22 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3875,18 +4199,22 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -3918,25 +4246,32 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -3964,25 +4299,32 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4009,25 +4351,32 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4054,25 +4403,32 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4105,20 +4461,24 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4146,20 +4506,24 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -4186,20 +4550,24 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -4226,20 +4594,24 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -4271,27 +4643,34 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BITCAST7]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[CONCAT_VECTORS]](<10 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4319,27 +4698,34 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST7]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -4366,27 +4752,34 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST7]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -4413,28 +4806,35 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST7]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -4465,16 +4865,19 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -4502,16 +4905,19 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4538,16 +4944,19 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4574,16 +4983,19 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4615,21 +5027,27 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -4657,21 +5075,27 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4698,21 +5122,27 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4739,21 +5169,27 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4786,18 +5222,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4825,18 +5264,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -4863,18 +5305,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -4901,18 +5346,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -4944,23 +5392,29 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -4988,23 +5442,29 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST6]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5031,23 +5491,29 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST6]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5074,23 +5540,29 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST6]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5121,18 +5593,22 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -5160,18 +5636,22 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5198,18 +5678,22 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5236,18 +5720,22 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5279,25 +5767,32 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -5325,25 +5820,32 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5370,25 +5872,32 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5415,25 +5924,32 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5466,20 +5982,24 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5507,20 +6027,24 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5547,20 +6071,24 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5587,20 +6115,24 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5632,27 +6164,34 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BITCAST7]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[CONCAT_VECTORS]](<10 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5680,27 +6219,34 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST7]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5727,27 +6273,34 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST7]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5774,28 +6327,35 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST7]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -5826,11 +6386,13 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5857,11 +6419,13 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5888,11 +6452,13 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5919,11 +6485,13 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -5955,15 +6523,18 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -5991,15 +6562,18 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6026,15 +6600,18 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6061,15 +6638,18 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6102,13 +6682,15 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6136,13 +6718,15 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6169,13 +6753,15 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6202,13 +6788,15 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6240,17 +6828,20 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6278,17 +6869,20 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6315,17 +6909,20 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6352,17 +6949,20 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6393,10 +6993,11 @@ define amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6423,10 +7024,11 @@ define amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6453,10 +7055,11 @@ define amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6483,10 +7086,11 @@ define amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6518,11 +7122,13 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6549,11 +7155,13 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6580,11 +7188,13 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6611,11 +7221,13 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6648,12 +7260,13 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6681,12 +7294,13 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6713,12 +7327,13 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6745,12 +7360,13 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6782,13 +7398,15 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
+ ; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -6816,13 +7434,15 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6849,13 +7469,15 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6882,13 +7504,15 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -6921,28 +7545,35 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX9-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (f32), addrspace 8)
; GFX9-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32)
; GFX9-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -6967,28 +7598,35 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
+ ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (f32), addrspace 8)
; GFX10-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32)
; GFX10-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -7013,29 +7651,36 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (f32), addrspace 8)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (f32), addrspace 8)
; GFX11-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32)
; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
;
@@ -7059,29 +7704,36 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (f32), addrspace 8)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (f32), addrspace 8)
; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32)
; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
main_body:
@@ -7110,28 +7762,35 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX9-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX9-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX9-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX9-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX9-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX9-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX9-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX9-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX9-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX9-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX9-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
+ ; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<2 x f32>), addrspace 8)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x f32>)
; GFX9-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -7158,28 +7817,35 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
+ ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<2 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -7206,29 +7872,36 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<2 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<2 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -7254,29 +7927,36 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[DEF]](s16)
; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<2 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<2 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
index 29efa58467b08..334aaad9df958 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX12 %s
@@ -22,16 +22,19 @@ define amdgpu_ps <4 x float> @sample_d_1d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -58,16 +61,19 @@ define amdgpu_ps <4 x float> @sample_d_1d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -94,16 +100,19 @@ define amdgpu_ps <4 x float> @sample_d_1d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -135,21 +144,27 @@ define amdgpu_ps <4 x float> @sample_d_2d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -176,21 +191,27 @@ define amdgpu_ps <4 x float> @sample_d_2d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -217,21 +238,27 @@ define amdgpu_ps <4 x float> @sample_d_2d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](f16), [[TRUNC5]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST4]](f16), [[BITCAST5]](f16)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -263,31 +290,40 @@ define amdgpu_ps <4 x float> @sample_d_3d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC7]](i16)
+ ; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX10-NEXT: [[BITCAST8:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC8]](i16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[TRUNC7]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC8]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[BITCAST7]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST8]](f16), [[DEF]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), [[BUILD_VECTOR6]](<2 x s16>), [[BUILD_VECTOR7]](<2 x s16>)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -315,31 +351,40 @@ define amdgpu_ps <4 x float> @sample_d_3d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX11-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX11-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX11-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX11-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC7]](i16)
+ ; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX11-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX11-NEXT: [[BITCAST8:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC8]](i16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[TRUNC7]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC8]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[BITCAST7]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST8]](f16), [[DEF]](s16)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR6]](<2 x s16>), [[BUILD_VECTOR7]](<2 x s16>)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
@@ -367,31 +412,40 @@ define amdgpu_ps <4 x float> @sample_d_3d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
- ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[COPY18]](s32)
- ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX12-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[COPY19]](s32)
- ; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX12-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[COPY20]](s32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
+ ; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[COPY18]](i32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC6]](i16)
+ ; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY $vgpr7
+ ; GFX12-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[COPY19]](i32)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC7]](i16)
+ ; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY $vgpr8
+ ; GFX12-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[COPY20]](i32)
+ ; GFX12-NEXT: [[BITCAST8:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC8]](i16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC6]](f16), [[TRUNC7]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC8]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST6]](f16), [[BITCAST7]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST8]](f16), [[DEF]](s16)
; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR5]](<2 x s16>), [[BUILD_VECTOR6]](<2 x s16>), [[BUILD_VECTOR7]](<2 x s16>)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
index f75197c8b61bf..fe11d92cf51d4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX12 %s
@@ -22,16 +22,18 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -57,16 +59,18 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -92,16 +96,18 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -132,21 +138,25 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -172,21 +182,25 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -212,21 +226,25 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -257,30 +275,36 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(f32) = COPY $vgpr8
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX10-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[CONCAT_VECTORS]](<14 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -307,30 +331,36 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(f32) = COPY $vgpr8
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
- ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX11-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
+ ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -357,30 +387,36 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC4]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC5]](i16)
; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(f32) = COPY $vgpr8
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](f16), [[TRUNC4]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR5]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST3]](f16), [[BITCAST4]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST5]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX12-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -413,17 +449,19 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -450,17 +488,19 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -487,17 +527,19 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -529,22 +571,26 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -571,22 +617,26 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -613,23 +663,27 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -660,18 +714,20 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -697,18 +753,20 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -734,18 +792,20 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -776,23 +836,27 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -818,23 +882,27 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -860,24 +928,28 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -909,19 +981,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -948,19 +1022,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -987,20 +1063,22 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1032,24 +1110,28 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -1077,25 +1159,29 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1122,25 +1208,29 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1171,16 +1261,18 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1206,16 +1298,18 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1241,16 +1335,18 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1281,21 +1377,25 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1321,21 +1421,25 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1361,21 +1465,25 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1407,17 +1515,19 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1444,17 +1554,19 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1481,17 +1593,19 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1523,22 +1637,26 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1565,22 +1683,26 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1607,23 +1729,27 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1654,18 +1780,20 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1691,18 +1819,20 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1728,18 +1858,20 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $vgpr2
; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](f32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1770,23 +1902,27 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1812,23 +1948,27 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1854,24 +1994,28 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY12]](s32)
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1903,19 +2047,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1942,19 +2088,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -1981,20 +2129,22 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $vgpr3
; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(f32) = COPY $vgpr4
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](f16), [[DEF]](s16)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST1]](f16), [[DEF]](s16)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](f32)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2026,24 +2176,28 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2071,25 +2225,29 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2116,25 +2274,29 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY13]](s32)
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
+ ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(f32) = COPY $vgpr5
; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](f32)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST4]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2167,25 +2329,29 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(f32) = COPY $vgpr8
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX10-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[CONCAT_VECTORS]](<14 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (f32), addrspace 8)
; GFX10-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32)
; GFX10-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -2210,26 +2376,30 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(f32) = COPY $vgpr8
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
- ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (f32), addrspace 8)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX11-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
+ ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (f32), addrspace 8)
; GFX11-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32)
; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
;
@@ -2253,26 +2423,30 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(f32) = COPY $vgpr8
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (f32), addrspace 8)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX12-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (f32), addrspace 8)
; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32)
; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
main_body:
@@ -2301,25 +2475,29 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX10-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX10-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
+ ; GFX10-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX10-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX10-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX10-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX10-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
; GFX10-NEXT: [[COPY20:%[0-9]+]]:_(f32) = COPY $vgpr8
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX10-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX10-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; GFX10-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[CONCAT_VECTORS]](<14 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<2 x f32>), addrspace 8)
; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x f32>)
; GFX10-NEXT: $vgpr0 = COPY [[UV]](f32)
@@ -2346,26 +2524,30 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX11-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX11-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX11-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
; GFX11-NEXT: [[COPY20:%[0-9]+]]:_(f32) = COPY $vgpr8
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
- ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
- ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<2 x f32>), addrspace 8)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX11-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
+ ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
+ ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<2 x f32>), addrspace 8)
; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x f32>)
; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32)
@@ -2391,26 +2573,30 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32)
; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY14]](s32)
- ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY15]](s32)
- ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY16]](s32)
- ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[COPY17]](s32)
+ ; GFX12-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY14]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY15]](i32)
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX12-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY16]](i32)
+ ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC2]](i16)
+ ; GFX12-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY17]](i32)
+ ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC3]](i16)
; GFX12-NEXT: [[COPY18:%[0-9]+]]:_(f32) = COPY $vgpr6
; GFX12-NEXT: [[COPY19:%[0-9]+]]:_(f32) = COPY $vgpr7
; GFX12-NEXT: [[COPY20:%[0-9]+]]:_(f32) = COPY $vgpr8
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
- ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
- ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[TRUNC3]](f16)
- ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
- ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
- ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
- ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
- ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<2 x f32>), addrspace 8)
+ ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](i32)
+ ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](f32)
+ ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST]](f16), [[BITCAST1]](f16)
+ ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[BITCAST2]](f16), [[BITCAST3]](f16)
+ ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](f32)
+ ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](f32)
+ ; GFX12-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](f32)
+ ; GFX12-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR3]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
+ ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), [[BUILD_VECTOR1]](<4 x i32>), 0, 0, 0, 2 :: (dereferenceable load (<2 x f32>), addrspace 8)
; GFX12-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x f32>)
; GFX12-NEXT: $vgpr0 = COPY [[UV]](f32)
; GFX12-NEXT: $vgpr1 = COPY [[UV1]](f32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
index dc9405772b64c..4ed737c603dc3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=legalizer -o - %s | FileCheck -check-prefix=UNPACKED %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX81 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=legalizer -o - %s | FileCheck -check-prefix=UNPACKED %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX81 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX12 %s
define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, half %data) {
; UNPACKED-LABEL: name: image_store_f16
@@ -22,10 +22,11 @@ define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ha
; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY10]](s32)
+ ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
- ; UNPACKED-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](f16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
+ ; UNPACKED-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[BITCAST]](f16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; GFX81-LABEL: name: image_store_f16
@@ -43,10 +44,11 @@ define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ha
; GFX81-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX81-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX81-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX81-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX81-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY10]](s32)
+ ; GFX81-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX81-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX81-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX81-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
- ; GFX81-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](f16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
+ ; GFX81-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[BITCAST]](f16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
; GFX81-NEXT: S_ENDPGM 0
;
; GFX9-LABEL: name: image_store_f16
@@ -64,10 +66,11 @@ define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ha
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX9-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX9-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY10]](s32)
+ ; GFX9-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
- ; GFX9-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](f16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
+ ; GFX9-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[BITCAST]](f16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
; GFX9-NEXT: S_ENDPGM 0
;
; GFX10-LABEL: name: image_store_f16
@@ -85,9 +88,10 @@ define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ha
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX10-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX10-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY10]](s32)
- ; GFX10-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](f16), 1, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
+ ; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX10-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[BITCAST]](f16), 1, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
; GFX10-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: image_store_f16
@@ -105,9 +109,10 @@ define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ha
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY10]](s32)
- ; GFX12-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](f16), 1, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX12-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[BITCAST]](f16), 1, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.image.store.2d.f16.i32(half %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
index 11d2e4d5b0134..99202ff7fe326 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
@@ -271,58 +271,21 @@ define <4 x i32> @abs_vgpr_v4i32(<4 x i32> %arg) {
}
define amdgpu_cs <2 x i8> @abs_sgpr_v2i8(<2 x i8> inreg %arg) {
-; GFX6-LABEL: abs_sgpr_v2i8:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_sext_i32_i8 s0, s0
-; GFX6-NEXT: s_sext_i32_i8 s1, s1
-; GFX6-NEXT: s_abs_i32 s0, s0
-; GFX6-NEXT: s_abs_i32 s1, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: abs_sgpr_v2i8:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_sext_i32_i8 s1, s1
-; GFX8-NEXT: s_abs_i32 s1, s1
-; GFX8-NEXT: s_sext_i32_i8 s0, s0
-; GFX8-NEXT: s_lshl_b32 s1, s1, 8
-; GFX8-NEXT: s_abs_i32 s0, s0
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: s_bfe_u32 s1, s0, 0x80008
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: abs_sgpr_v2i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_i32 s1, s1, 0x80000
-; GFX10-NEXT: s_bfe_i32 s0, s0, 0x80000
-; GFX10-NEXT: s_sub_i32 s3, 0, s1
-; GFX10-NEXT: s_sub_i32 s2, 0, s0
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_max_i32 s1, s1, s3
-; GFX10-NEXT: s_max_i32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s2, s1, 8
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: ; return to shader part epilog
+; GFX-LABEL: abs_sgpr_v2i8:
+; GFX: ; %bb.0:
+; GFX-NEXT: s_sext_i32_i8 s0, s0
+; GFX-NEXT: s_sext_i32_i8 s1, s1
+; GFX-NEXT: s_abs_i32 s0, s0
+; GFX-NEXT: s_abs_i32 s1, s1
+; GFX-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: abs_sgpr_v2i8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_bfe_i32 s1, s1, 0x80000
-; GFX1250-NEXT: s_bfe_i32 s0, s0, 0x80000
-; GFX1250-NEXT: s_sub_co_i32 s3, 0, s1
-; GFX1250-NEXT: s_sub_co_i32 s2, 0, s0
-; GFX1250-NEXT: s_sext_i32_i16 s3, s3
-; GFX1250-NEXT: s_sext_i32_i16 s1, s1
-; GFX1250-NEXT: s_sext_i32_i16 s2, s2
-; GFX1250-NEXT: s_sext_i32_i16 s0, s0
-; GFX1250-NEXT: s_max_i32 s1, s1, s3
-; GFX1250-NEXT: s_max_i32 s0, s0, s2
-; GFX1250-NEXT: s_lshl_b32 s2, s1, 8
-; GFX1250-NEXT: s_and_b32 s1, s1, 0xff
-; GFX1250-NEXT: s_or_b32 s0, s0, s2
+; GFX1250-NEXT: s_sext_i32_i8 s0, s0
+; GFX1250-NEXT: s_sext_i32_i8 s1, s1
+; GFX1250-NEXT: s_abs_i32 s0, s0
+; GFX1250-NEXT: s_abs_i32 s1, s1
; GFX1250-NEXT: ; return to shader part epilog
%res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
ret <2 x i8> %res
@@ -393,76 +356,25 @@ define <2 x i8> @abs_vgpr_v2i8(<2 x i8> %arg) {
}
define amdgpu_cs <3 x i8> @abs_sgpr_v3i8(<3 x i8> inreg %arg) {
-; GFX6-LABEL: abs_sgpr_v3i8:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_sext_i32_i8 s0, s0
-; GFX6-NEXT: s_sext_i32_i8 s1, s1
-; GFX6-NEXT: s_sext_i32_i8 s2, s2
-; GFX6-NEXT: s_abs_i32 s0, s0
-; GFX6-NEXT: s_abs_i32 s1, s1
-; GFX6-NEXT: s_abs_i32 s2, s2
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: abs_sgpr_v3i8:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_sext_i32_i8 s2, s2
-; GFX8-NEXT: s_sext_i32_i8 s1, s1
-; GFX8-NEXT: s_sext_i32_i8 s0, s0
-; GFX8-NEXT: s_abs_i32 s2, s2
-; GFX8-NEXT: s_abs_i32 s1, s1
-; GFX8-NEXT: s_abs_i32 s0, s0
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: abs_sgpr_v3i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_i32 s0, s0, 0x80000
-; GFX10-NEXT: s_bfe_i32 s1, s1, 0x80000
-; GFX10-NEXT: s_sub_i32 s3, 0, s0
-; GFX10-NEXT: s_sub_i32 s4, 0, s1
-; GFX10-NEXT: s_bfe_i32 s2, s2, 0x80000
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_sext_i32_i16 s4, s4
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_max_i32 s0, s0, s3
-; GFX10-NEXT: s_max_i32 s1, s1, s4
-; GFX10-NEXT: s_sub_i32 s3, 0, s2
-; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: s_max_i32 s2, s2, s3
-; GFX10-NEXT: s_and_b32 s1, s0, 0xffff
-; GFX10-NEXT: s_lshl_b32 s3, s2, 16
-; GFX10-NEXT: s_or_b32 s1, s1, s3
-; GFX10-NEXT: s_lshr_b32 s1, s1, 8
-; GFX10-NEXT: ; return to shader part epilog
+; GFX-LABEL: abs_sgpr_v3i8:
+; GFX: ; %bb.0:
+; GFX-NEXT: s_sext_i32_i8 s0, s0
+; GFX-NEXT: s_sext_i32_i8 s1, s1
+; GFX-NEXT: s_sext_i32_i8 s2, s2
+; GFX-NEXT: s_abs_i32 s0, s0
+; GFX-NEXT: s_abs_i32 s1, s1
+; GFX-NEXT: s_abs_i32 s2, s2
+; GFX-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: abs_sgpr_v3i8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_bfe_i32 s0, s0, 0x80000
-; GFX1250-NEXT: s_bfe_i32 s1, s1, 0x80000
-; GFX1250-NEXT: s_sub_co_i32 s3, 0, s0
-; GFX1250-NEXT: s_sub_co_i32 s4, 0, s1
-; GFX1250-NEXT: s_bfe_i32 s2, s2, 0x80000
-; GFX1250-NEXT: s_sext_i32_i16 s3, s3
-; GFX1250-NEXT: s_sext_i32_i16 s0, s0
-; GFX1250-NEXT: s_sext_i32_i16 s4, s4
-; GFX1250-NEXT: s_sext_i32_i16 s1, s1
-; GFX1250-NEXT: s_max_i32 s0, s0, s3
-; GFX1250-NEXT: s_max_i32 s1, s1, s4
-; GFX1250-NEXT: s_sub_co_i32 s3, 0, s2
-; GFX1250-NEXT: s_lshl_b32 s1, s1, 8
-; GFX1250-NEXT: s_sext_i32_i16 s3, s3
-; GFX1250-NEXT: s_sext_i32_i16 s2, s2
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_max_i32 s2, s2, s3
-; GFX1250-NEXT: s_and_b32 s1, s0, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s3, s2, 16
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_or_b32 s1, s1, s3
-; GFX1250-NEXT: s_lshr_b32 s1, s1, 8
+; GFX1250-NEXT: s_sext_i32_i8 s0, s0
+; GFX1250-NEXT: s_sext_i32_i8 s1, s1
+; GFX1250-NEXT: s_sext_i32_i8 s2, s2
+; GFX1250-NEXT: s_abs_i32 s0, s0
+; GFX1250-NEXT: s_abs_i32 s1, s1
+; GFX1250-NEXT: s_abs_i32 s2, s2
; GFX1250-NEXT: ; return to shader part epilog
%res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
ret <3 x i8> %res
@@ -531,21 +443,18 @@ define <3 x i8> @abs_vgpr_v3i8(<3 x i8> %arg) {
; GFX1250-REAL16: ; %bb.0:
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT: v_bfe_i32 v5, v2, 0, 8
; GFX1250-REAL16-NEXT: v_bfe_i32 v3, v0, 0, 8
-; GFX1250-REAL16-NEXT: v_bfe_i32 v4, v1, 0, 8
+; GFX1250-REAL16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX1250-REAL16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-REAL16-NEXT: v_sub_nc_u16 v1.l, 0, v5.l
; GFX1250-REAL16-NEXT: v_sub_nc_u16 v0.l, 0, v3.l
+; GFX1250-REAL16-NEXT: v_sub_nc_u16 v0.h, 0, v1.l
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-REAL16-NEXT: v_sub_nc_u16 v0.h, 0, v4.l
-; GFX1250-REAL16-NEXT: v_max_i16 v1.l, v5.l, v1.l
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-REAL16-NEXT: v_sub_nc_u16 v1.h, 0, v2.l
; GFX1250-REAL16-NEXT: v_max_i16 v0.l, v3.l, v0.l
-; GFX1250-REAL16-NEXT: v_max_i16 v2.l, v4.l, v0.h
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX1250-REAL16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-REAL16-NEXT: v_max_i16 v1.l, v1.l, v0.h
+; GFX1250-REAL16-NEXT: v_max_i16 v2.l, v2.l, v1.h
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
ret <3 x i8> %res
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
index afb7733b79352..35f23d338a4e0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
declare half @llvm.amdgcn.fract.f16(half)
declare float @llvm.amdgcn.fract.f32(float)
@@ -9,11 +9,8 @@ define amdgpu_ps half @s_fract_f16(half inreg %src) {
; GFX12-LABEL: s_fract_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_fract_f16_e32 v0.l, s0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_2)
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_add_f16 s0, s0, s0
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.l
; GFX12-NEXT: ; return to shader part epilog
%fract = call half @llvm.amdgcn.fract.f16(half %src)
%res = fadd half %fract, %fract
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
index 62ef7581508e9..ae5983798bd51 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
@@ -1,76 +1,74 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10NSA %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX10NSA %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10NSA %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX10NSA %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12 %s
define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
; GFX9-LABEL: gather4_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v0, v1, v0, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4 v[0:3], v0, s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4 v[0:3], v0, s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4 v[0:3], v0, s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -81,76 +79,68 @@ main_body:
define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {
; GFX9-LABEL: gather4_cube:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16 da
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v1, v1, v0, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4 v[0:3], v[1:2], s[4:11], s[12:15] dmask:0x1 a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_cube:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4 v[0:3], [v0, v2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_cube:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4 v[0:3], [v0, v2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -161,76 +151,68 @@ main_body:
define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {
; GFX9-LABEL: gather4_2darray:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16 da
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v1, v1, v0, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4 v[0:3], v[1:2], s[4:11], s[12:15] dmask:0x1 a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_2darray:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4 v[0:3], [v0, v2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_2darray:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4 v[0:3], [v0, v2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -241,70 +223,68 @@ main_body:
define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {
; GFX9-LABEL: gather4_c_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v1, v2, v1, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4_c v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_c_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4_c v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_c_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4_c v[0:3], [v0, v1], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -315,76 +295,68 @@ main_body:
define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %clamp) {
; GFX9-LABEL: gather4_cl_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v1, v1, v0, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4_cl v[0:3], v[1:2], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_cl_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4_cl v[0:3], [v0, v2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_cl_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4_cl v[0:3], [v0, v2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -395,76 +367,70 @@ main_body:
define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %clamp) {
; GFX9-LABEL: gather4_c_cl_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v2, s0, 16, v2
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4_c_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: v_mov_b32_e32 v5, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, v0
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v4, v2, v1, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4_c_cl v[0:3], v[3:5], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_c_cl_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10NSA-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10NSA-NEXT: v_lshl_or_b32 v2, s0, 16, v3
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4_c_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_c_cl_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT: v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -475,76 +441,68 @@ main_body:
define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, half %s, half %t) {
; GFX9-LABEL: gather4_b_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v1, v2, v1, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4_b v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_b_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4_b v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_b_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4_b v[0:3], [v0, v1], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -555,76 +513,68 @@ main_body:
define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, float %zcompare, half %s, half %t) {
; GFX9-LABEL: gather4_c_b_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v2, v3, v2, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4_c_b v[0:3], v[0:2], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_c_b_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10NSA-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4_c_b v[0:3], v[0:2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_c_b_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -635,82 +585,70 @@ main_body:
define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, half %s, half %t, half %clamp) {
; GFX9-LABEL: gather4_b_cl_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v2, s0, 16, v2
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: v_mov_b32_e32 v5, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, v0
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v4, v2, v1, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4_b_cl v[0:3], v[3:5], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_b_cl_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10NSA-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10NSA-NEXT: v_lshl_or_b32 v2, s0, 16, v3
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v3], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_b_cl_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT: v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v3], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -721,82 +659,71 @@ main_body:
define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, float %zcompare, half %s, half %t, half %clamp) {
; GFX9-LABEL: gather4_c_b_cl_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: s_mov_b64 s[14:15], exec
-; GFX9-NEXT: s_mov_b32 s0, s2
+; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v4
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v3, s0, 16, v3
-; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
-; GFX9-NEXT: image_gather4_c_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s2, 0x5040100
+; GFX9-NEXT: v_mov_b32_e32 v7, v4
+; GFX9-NEXT: v_mov_b32_e32 v5, v1
+; GFX9-NEXT: v_mov_b32_e32 v4, v0
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: v_perm_b32 v6, v3, v2, s2
+; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX9-NEXT: image_gather4_c_b_cl v[0:3], v[4:7], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_c_b_cl_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
+; GFX10NSA-NEXT: s_mov_b32 s0, exec_lo
; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10NSA-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10NSA-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX10NSA-NEXT: v_lshl_or_b32 v3, s0, 16, v4
-; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX10NSA-NEXT: image_gather4_c_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10NSA-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_c_b_cl_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_mov_b32 s0, s2
+; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT: v_lshl_or_b32 v3, s0, 16, v4
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX12-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -807,67 +734,59 @@ main_body:
define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %lod) {
; GFX9-LABEL: gather4_l_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: s_mov_b32 s0, s2
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX9-NEXT: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s0, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: v_perm_b32 v1, v1, v0, s0
+; GFX9-NEXT: image_gather4_l v[0:3], v[1:2], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_l_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: image_gather4_l v[0:3], [v0, v2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_l_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: s_mov_b32 s0, s2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: image_gather4_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: image_gather4_l v[0:3], [v0, v2], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -878,67 +797,61 @@ main_body:
define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %lod) {
; GFX9-LABEL: gather4_c_l_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: s_mov_b32 s0, s2
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v2, s0, 16, v2
-; GFX9-NEXT: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s0, 0x5040100
+; GFX9-NEXT: v_mov_b32_e32 v5, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, v0
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: v_perm_b32 v4, v2, v1, s0
+; GFX9-NEXT: image_gather4_c_l v[0:3], v[3:5], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_c_l_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10NSA-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10NSA-NEXT: v_lshl_or_b32 v2, s0, 16, v3
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_c_l_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT: s_mov_b32 s0, s2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT: v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: image_gather4_c_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -949,61 +862,59 @@ main_body:
define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
; GFX9-LABEL: gather4_lz_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: s_mov_b32 s0, s2
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s0, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: v_perm_b32 v0, v1, v0, s0
+; GFX9-NEXT: image_gather4_lz v[0:3], v0, s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_lz_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: image_gather4_lz v[0:3], v0, s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_lz_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: s_mov_b32 s0, s2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: image_gather4_lz v[0:3], v0, s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -1014,61 +925,59 @@ main_body:
define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {
; GFX9-LABEL: gather4_c_lz_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: s_mov_b32 s0, s2
-; GFX9-NEXT: s_mov_b32 s1, s3
-; GFX9-NEXT: s_mov_b32 s2, s4
-; GFX9-NEXT: s_mov_b32 s3, s5
-; GFX9-NEXT: s_mov_b32 s4, s6
-; GFX9-NEXT: s_mov_b32 s5, s7
-; GFX9-NEXT: s_mov_b32 s6, s8
-; GFX9-NEXT: s_mov_b32 s7, s9
-; GFX9-NEXT: s_mov_b32 s8, s10
-; GFX9-NEXT: s_mov_b32 s9, s11
-; GFX9-NEXT: s_mov_b32 s10, s12
-; GFX9-NEXT: s_mov_b32 s11, s13
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16
+; GFX9-NEXT: s_mov_b32 s0, 0x5040100
+; GFX9-NEXT: s_mov_b32 s15, s13
+; GFX9-NEXT: s_mov_b32 s14, s12
+; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: s_mov_b32 s12, s10
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s9, s7
+; GFX9-NEXT: s_mov_b32 s8, s6
+; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s6, s4
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: v_perm_b32 v1, v2, v1, s0
+; GFX9-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10NSA-LABEL: gather4_c_lz_2d:
; GFX10NSA: ; %bb.0: ; %main_body
-; GFX10NSA-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10NSA-NEXT: s_mov_b32 s0, s2
-; GFX10NSA-NEXT: s_mov_b32 s1, s3
-; GFX10NSA-NEXT: s_mov_b32 s2, s4
-; GFX10NSA-NEXT: s_mov_b32 s3, s5
-; GFX10NSA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10NSA-NEXT: s_mov_b32 s4, s6
-; GFX10NSA-NEXT: s_mov_b32 s5, s7
-; GFX10NSA-NEXT: s_mov_b32 s6, s8
-; GFX10NSA-NEXT: s_mov_b32 s7, s9
-; GFX10NSA-NEXT: s_mov_b32 s8, s10
-; GFX10NSA-NEXT: s_mov_b32 s9, s11
-; GFX10NSA-NEXT: s_mov_b32 s10, s12
-; GFX10NSA-NEXT: s_mov_b32 s11, s13
-; GFX10NSA-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX10NSA-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10NSA-NEXT: s_mov_b32 s15, s13
+; GFX10NSA-NEXT: s_mov_b32 s14, s12
+; GFX10NSA-NEXT: s_mov_b32 s13, s11
+; GFX10NSA-NEXT: s_mov_b32 s12, s10
+; GFX10NSA-NEXT: s_mov_b32 s11, s9
+; GFX10NSA-NEXT: s_mov_b32 s10, s8
+; GFX10NSA-NEXT: s_mov_b32 s9, s7
+; GFX10NSA-NEXT: s_mov_b32 s8, s6
+; GFX10NSA-NEXT: s_mov_b32 s7, s5
+; GFX10NSA-NEXT: s_mov_b32 s6, s4
+; GFX10NSA-NEXT: s_mov_b32 s5, s3
+; GFX10NSA-NEXT: s_mov_b32 s4, s2
+; GFX10NSA-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: gather4_c_lz_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: s_mov_b32 s0, s2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: s_mov_b32 s8, s10
-; GFX12-NEXT: s_mov_b32 s9, s11
-; GFX12-NEXT: s_mov_b32 s10, s12
-; GFX12-NEXT: s_mov_b32 s11, s13
-; GFX12-NEXT: image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-NEXT: s_mov_b32 s15, s13
+; GFX12-NEXT: s_mov_b32 s14, s12
+; GFX12-NEXT: s_mov_b32 s13, s11
+; GFX12-NEXT: s_mov_b32 s12, s10
+; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: s_mov_b32 s10, s8
+; GFX12-NEXT: s_mov_b32 s9, s7
+; GFX12-NEXT: s_mov_b32 s8, s6
+; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s6, s4
+; GFX12-NEXT: s_mov_b32 s5, s3
+; GFX12-NEXT: s_mov_b32 s4, s2
+; GFX12-NEXT: image_gather4_c_lz v[0:3], [v0, v1], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
index d45bf78d4e904..679fb242cc9fc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga < %s | FileCheck -check-prefix=GFX8-UNPACKED %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 < %s | FileCheck -check-prefix=GFX8-PACKED %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
define amdgpu_ps half @load_1d_f16_x(<8 x i32> inreg %rsrc, i32 %s) {
; GFX8-UNPACKED-LABEL: load_1d_f16_x:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
index d5cbd6d651481..76b4dedc76200 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
@@ -1,13 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
; GFX10-LABEL: sample_cd_1d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX10-NEXT: image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
@@ -19,11 +15,9 @@ main_body:
define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
; GFX10-LABEL: sample_cd_2d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX10-NEXT: image_sample_cd_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10-NEXT: image_sample_cd_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
main_body:
@@ -34,10 +28,6 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
; GFX10-LABEL: sample_c_cd_1d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
@@ -49,11 +39,9 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
; GFX10-LABEL: sample_c_cd_2d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
main_body:
@@ -64,10 +52,6 @@ main_body:
define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
; GFX10-LABEL: sample_cd_cl_1d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
@@ -79,11 +63,9 @@ main_body:
define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
; GFX10-LABEL: sample_cd_cl_2d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
main_body:
@@ -94,10 +76,6 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
; GFX10-LABEL: sample_c_cd_cl_1d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
@@ -111,10 +89,8 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v8, v2
; GFX10-NEXT: v_mov_b32_e32 v2, v0
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX10-NEXT: v_lshl_or_b32 v3, v8, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v4, v4, 16, v1
+; GFX10-NEXT: v_perm_b32 v4, v4, v3, 0x5040100
+; GFX10-NEXT: v_perm_b32 v3, v8, v1, 0x5040100
; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
index fb054e2fed32f..2cadc2cb17f4c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
@@ -1,35 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12 %s
define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
; GFX10-LABEL: sample_d_1d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX10-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_d_1d:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX11-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_d_1d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX12-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
@@ -41,31 +29,25 @@ main_body:
define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
; GFX10-LABEL: sample_d_2d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX10-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_d_2d:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_d_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX12-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -76,43 +58,27 @@ main_body:
define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) {
; GFX10-LABEL: sample_d_3d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_and_b32_e32 v9, 0xffff, v2
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff, v3
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX10-NEXT: v_lshl_or_b32 v2, v1, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v3, s0, 16, v9
-; GFX10-NEXT: v_lshl_or_b32 v4, v4, 16, v10
-; GFX10-NEXT: v_lshl_or_b32 v5, s0, 16, v5
+; GFX10-NEXT: v_mov_b32_e32 v9, v3
+; GFX10-NEXT: v_mov_b32_e32 v3, v2
+; GFX10-NEXT: v_perm_b32 v2, v1, v0, 0x5040100
+; GFX10-NEXT: v_perm_b32 v4, v4, v9, 0x5040100
; GFX10-NEXT: image_sample_d_g16 v[0:3], v[2:8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_d_3d:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v3, s0, 16, v5
-; GFX11-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2, v3, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX11-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_d_3d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX12-NEXT: v_lshl_or_b32 v5, s0, 16, v5
-; GFX12-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -123,30 +89,18 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
; GFX10-LABEL: sample_c_d_1d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_c_d_1d:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX11-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_c_d_1d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX12-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
@@ -158,31 +112,25 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
; GFX10-LABEL: sample_c_d_2d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX10-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_c_d_2d:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_c_d_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX12-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -193,30 +141,18 @@ main_body:
define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
; GFX10-LABEL: sample_d_cl_1d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_d_cl_1d:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX11-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_d_cl_1d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX12-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
@@ -228,31 +164,25 @@ main_body:
define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
; GFX10-LABEL: sample_d_cl_2d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_d_cl_2d:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_d_cl_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX12-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -263,30 +193,18 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
; GFX10-LABEL: sample_c_d_cl_1d:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_c_d_cl_1d:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX11-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_c_d_cl_1d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX12-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
@@ -300,31 +218,25 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v8, v2
; GFX10-NEXT: v_mov_b32_e32 v2, v0
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX10-NEXT: v_lshl_or_b32 v3, v8, 16, v0
-; GFX10-NEXT: v_lshl_or_b32 v4, v4, 16, v1
+; GFX10-NEXT: v_perm_b32 v4, v4, v3, 0x5040100
+; GFX10-NEXT: v_perm_b32 v3, v8, v1, 0x5040100
; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_c_d_cl_2d:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_c_d_cl_2d:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX12-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
@@ -335,34 +247,28 @@ main_body:
define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
; GFX10-LABEL: sample_c_d_o_2darray_V1:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_mov_b32_e32 v9, v2
-; GFX10-NEXT: v_mov_b32_e32 v10, v3
-; GFX10-NEXT: v_mov_b32_e32 v2, v0
+; GFX10-NEXT: v_mov_b32_e32 v9, v3
+; GFX10-NEXT: v_mov_b32_e32 v10, v2
; GFX10-NEXT: v_mov_b32_e32 v3, v1
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v9
-; GFX10-NEXT: v_lshl_or_b32 v5, v5, 16, v1
-; GFX10-NEXT: v_lshl_or_b32 v4, v10, 16, v0
+; GFX10-NEXT: v_mov_b32_e32 v2, v0
+; GFX10-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
+; GFX10-NEXT: v_perm_b32 v4, v9, v10, 0x5040100
; GFX10-NEXT: image_sample_c_d_o_g16 v0, v[2:8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_c_d_o_2darray_V1:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v3, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_c_d_o_2darray_V1:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT: v_lshl_or_b32 v5, v5, 16, v4
+; GFX12-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
+; GFX12-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX12-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
@@ -374,34 +280,28 @@ main_body:
define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
; GFX10-LABEL: sample_c_d_o_2darray_V2:
; GFX10: ; %bb.0: ; %main_body
-; GFX10-NEXT: v_mov_b32_e32 v9, v2
-; GFX10-NEXT: v_mov_b32_e32 v10, v3
-; GFX10-NEXT: v_mov_b32_e32 v2, v0
+; GFX10-NEXT: v_mov_b32_e32 v9, v3
+; GFX10-NEXT: v_mov_b32_e32 v10, v2
; GFX10-NEXT: v_mov_b32_e32 v3, v1
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v9
-; GFX10-NEXT: v_lshl_or_b32 v5, v5, 16, v1
-; GFX10-NEXT: v_lshl_or_b32 v4, v10, 16, v0
+; GFX10-NEXT: v_mov_b32_e32 v2, v0
+; GFX10-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
+; GFX10-NEXT: v_perm_b32 v4, v9, v10, 0x5040100
; GFX10-NEXT: image_sample_c_d_o_g16 v[0:1], v[2:8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: sample_c_d_o_2darray_V2:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v3, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_c_d_o_2darray_V2:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT: v_lshl_or_b32 v5, v5, 16, v4
+; GFX12-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
+; GFX12-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX12-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
index d1b327ca3a1e0..affc5f07d6861 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
@@ -9,28 +9,28 @@
define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, half %data) {
; UNPACKED-LABEL: image_store_f16:
; UNPACKED: ; %bb.0:
-; UNPACKED-NEXT: s_mov_b32 s0, s2
-; UNPACKED-NEXT: s_mov_b32 s1, s3
-; UNPACKED-NEXT: s_mov_b32 s2, s4
-; UNPACKED-NEXT: s_mov_b32 s3, s5
-; UNPACKED-NEXT: s_mov_b32 s4, s6
-; UNPACKED-NEXT: s_mov_b32 s5, s7
-; UNPACKED-NEXT: s_mov_b32 s6, s8
-; UNPACKED-NEXT: s_mov_b32 s7, s9
-; UNPACKED-NEXT: image_store v2, v[0:1], s[0:7] dmask:0x1 unorm d16
+; UNPACKED-NEXT: s_mov_b32 s11, s9
+; UNPACKED-NEXT: s_mov_b32 s10, s8
+; UNPACKED-NEXT: s_mov_b32 s9, s7
+; UNPACKED-NEXT: s_mov_b32 s8, s6
+; UNPACKED-NEXT: s_mov_b32 s7, s5
+; UNPACKED-NEXT: s_mov_b32 s6, s4
+; UNPACKED-NEXT: s_mov_b32 s5, s3
+; UNPACKED-NEXT: s_mov_b32 s4, s2
+; UNPACKED-NEXT: image_store v2, v[0:1], s[4:11] dmask:0x1 unorm d16
; UNPACKED-NEXT: s_endpgm
;
; GFX81-LABEL: image_store_f16:
; GFX81: ; %bb.0:
-; GFX81-NEXT: s_mov_b32 s0, s2
-; GFX81-NEXT: s_mov_b32 s1, s3
-; GFX81-NEXT: s_mov_b32 s2, s4
-; GFX81-NEXT: s_mov_b32 s3, s5
-; GFX81-NEXT: s_mov_b32 s4, s6
-; GFX81-NEXT: s_mov_b32 s5, s7
-; GFX81-NEXT: s_mov_b32 s6, s8
-; GFX81-NEXT: s_mov_b32 s7, s9
-; GFX81-NEXT: image_store v2, v[0:1], s[0:7] dmask:0x1 unorm d16
+; GFX81-NEXT: s_mov_b32 s11, s9
+; GFX81-NEXT: s_mov_b32 s10, s8
+; GFX81-NEXT: s_mov_b32 s9, s7
+; GFX81-NEXT: s_mov_b32 s8, s6
+; GFX81-NEXT: s_mov_b32 s7, s5
+; GFX81-NEXT: s_mov_b32 s6, s4
+; GFX81-NEXT: s_mov_b32 s5, s3
+; GFX81-NEXT: s_mov_b32 s4, s2
+; GFX81-NEXT: image_store v2, v[0:1], s[4:11] dmask:0x1 unorm d16
; GFX81-NEXT: s_endpgm
call void @llvm.amdgcn.image.store.2d.f16.i32(half %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
index 4f8f3239c0c2d..72253efefbc7f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
; GFX11-LABEL: v_interp_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index eec4337a1cd48..74eeb339a4fc8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1030 %s
; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1013 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1013 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
; RUN: not --crash llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1012 < %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
index 149e6473e51fd..116eae345a64d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
@@ -245,7 +245,7 @@ define amdgpu_ps ptr addrspace(8) @general_case(ptr inreg %p, i16 inreg %stride,
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32(i32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32(i32) = COPY $sgpr3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(i32) = COPY $sgpr5
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
@@ -274,7 +274,7 @@ define amdgpu_ps ptr addrspace(8) @general_case(ptr inreg %p, i16 inreg %stride,
; CHECK45-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0
; CHECK45-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1
; CHECK45-NEXT: [[MV:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32)
- ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; CHECK45-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK45-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
; CHECK45-NEXT: [[MV1:%[0-9]+]]:sgpr(i64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
@@ -324,7 +324,7 @@ define amdgpu_ps float @general_case_load(ptr inreg %p, i16 inreg %stride, i64 i
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32(i32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32(i32) = COPY $sgpr3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(i32) = COPY $sgpr5
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
@@ -346,7 +346,7 @@ define amdgpu_ps float @general_case_load(ptr inreg %p, i16 inreg %stride, i64 i
; CHECK45-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0
; CHECK45-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1
; CHECK45-NEXT: [[MV:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32)
- ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; CHECK45-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK45-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
; CHECK45-NEXT: [[MV1:%[0-9]+]]:sgpr(i64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
@@ -392,7 +392,7 @@ define amdgpu_ps float @general_case_load_with_waterfall(ptr %p, i16 %stride, i6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
@@ -452,7 +452,7 @@ define amdgpu_ps float @general_case_load_with_waterfall(ptr %p, i16 %stride, i6
; CHECK45-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
; CHECK45-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; CHECK45-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32)
- ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
+ ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
; CHECK45-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; CHECK45-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
; CHECK45-NEXT: [[MV1:%[0-9]+]]:vgpr(i64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
index 639ced6f19c73..18a343d4882e6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
@@ -8,34 +8,38 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
@@ -47,12 +51,15 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY4]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void
@@ -63,34 +70,36 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_409
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY6]](s32), [[COPY7]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[C]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY6]](s32), [[COPY7]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[C]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16
@@ -102,12 +111,15 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_409
; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY4]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY6]](s32), [[COPY7]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY6]](s32), [[COPY7]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
index a010f580bcd17..0f27a9ddfa3da 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1200 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1250 %s
; FIXME: Test with SI when argument lowering not broken for f16
@@ -947,15 +947,19 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
; GFX8: bb.1 (%ir-block.0):
; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
- ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
- ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
- ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
- ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
- ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX8-NEXT: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; GFX8-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX8-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX8-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX8-NEXT: G_AMDGPU_BUFFER_STORE_SHORT [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX8-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
@@ -968,9 +972,11 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_16 = COPY [[COPY4]].lo16
+ ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
+ ; GFX12-NEXT: BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
index e3b002bbc7abb..beb8801ca6718 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
@@ -7,34 +7,42 @@ define amdgpu_ps void @raw_ptr_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_vo
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_ptr_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.buffer.store.format.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void
@@ -45,34 +53,40 @@ define amdgpu_ps void @raw_ptr_buffer_store_format__sgpr_rsrc__vgpr_val__voffset
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY6]](s32), [[COPY7]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[C]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_ptr_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY4]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY6]](s32), [[COPY7]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[C]], [[COPY5]], 4095, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.buffer.store.format.f16(half %val, ptr addrspace(8) %rsrc, i32 4095, i32 %soffset, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
index c917e5bf21bcb..0ee3a7fbad8d0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
@@ -465,15 +465,21 @@ define amdgpu_ps void @raw_ptr_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
- ; CHECK-NEXT: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY4]](i32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: G_AMDGPU_BUFFER_STORE_SHORT [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; CHECK-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.buffer.store.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
index 987c04d9583be..9df8f392b8d3f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
@@ -7,34 +7,42 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
ret void
@@ -177,100 +185,44 @@ define amdgpu_ps void @raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_so
define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset
; UNPACKED: bb.1 (%ir-block.0):
- ; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.2:
- ; UNPACKED-NEXT: successors: %bb.3(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT4]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.3:
- ; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
- ; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.4:
- ; UNPACKED-NEXT: successors: %bb.5(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.5:
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
- ; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.2:
- ; PACKED-NEXT: successors: %bb.3(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT4]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.3:
- ; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
- ; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.4:
- ; PACKED-NEXT: successors: %bb.5(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.5:
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
ret void
@@ -280,106 +232,44 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soffset(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset) {
; UNPACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soffset
; UNPACKED: bb.1 (%ir-block.0):
- ; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.2:
- ; UNPACKED-NEXT: successors: %bb.3(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.3:
- ; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
- ; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.4:
- ; UNPACKED-NEXT: successors: %bb.5(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.5:
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soffset
; PACKED: bb.1 (%ir-block.0):
- ; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.2:
- ; PACKED-NEXT: successors: %bb.3(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.3:
- ; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
- ; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.4:
- ; PACKED-NEXT: successors: %bb.5(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.5:
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
ret void
@@ -389,108 +279,44 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset(half %val, ptr addrspace(8) %rsrc, i32 inreg %voffset, i32 %soffset) {
; UNPACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset
; UNPACKED: bb.1 (%ir-block.0):
- ; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.2:
- ; UNPACKED-NEXT: successors: %bb.3(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.3:
- ; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
- ; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.4:
- ; UNPACKED-NEXT: successors: %bb.5(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.5:
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset
; PACKED: bb.1 (%ir-block.0):
- ; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.2:
- ; PACKED-NEXT: successors: %bb.3(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.3:
- ; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
- ; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.4:
- ; PACKED-NEXT: successors: %bb.5(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.5:
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
ret void
@@ -501,34 +327,42 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)
ret void
@@ -539,34 +373,42 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)
ret void
@@ -577,34 +419,42 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)
ret void
@@ -615,34 +465,42 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
index 767d6f22d4ab5..63edcf12d4e08 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
@@ -7,34 +7,30 @@ define amdgpu_ps void @raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffs
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; PACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.ptr.tbuffer.store.i8(i8 %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
ret void
@@ -47,14 +43,14 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr5
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vreg_128(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
@@ -63,23 +59,25 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
; UNPACKED-NEXT: bb.2:
; UNPACKED-NEXT: successors: %bb.3(0x80000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT4]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128(<4 x s32>) = REG_SEQUENCE [[INTRINSIC_CONVERGENT]](s32), %subreg.sub0, [[INTRINSIC_CONVERGENT1]](s32), %subreg.sub1, [[INTRINSIC_CONVERGENT2]](s32), %subreg.sub2, [[INTRINSIC_CONVERGENT3]](s32), %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub0_sub1(<4 x s32>)
+ ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub2_sub3(<4 x s32>)
+ ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub0_sub1(<4 x s32>)
+ ; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub2_sub3(<4 x s32>)
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY10]](s64), [[COPY8]](s64), implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY11]](s64), [[COPY9]](s64), implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[V_CMP_EQ_U64_e64_]](s1), [[V_CMP_EQ_U64_e64_1]](s1), implicit-def dead $scc
+ ; UNPACKED-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[S_AND_B64_]](s1)
+ ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[COPY12]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.3:
; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
+ ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]](i32), [[COPY5]](i32), [[REG_SEQUENCE]](<4 x s32>), [[COPY6]](i32), 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; UNPACKED-NEXT: {{ $}}
@@ -96,14 +94,14 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr5
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vreg_128(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
@@ -112,23 +110,25 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
; PACKED-NEXT: bb.2:
; PACKED-NEXT: successors: %bb.3(0x80000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT4]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128(<4 x s32>) = REG_SEQUENCE [[INTRINSIC_CONVERGENT]](s32), %subreg.sub0, [[INTRINSIC_CONVERGENT1]](s32), %subreg.sub1, [[INTRINSIC_CONVERGENT2]](s32), %subreg.sub2, [[INTRINSIC_CONVERGENT3]](s32), %subreg.sub3
+ ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub0_sub1(<4 x s32>)
+ ; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub2_sub3(<4 x s32>)
+ ; PACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub0_sub1(<4 x s32>)
+ ; PACKED-NEXT: [[COPY11:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub2_sub3(<4 x s32>)
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY10]](s64), [[COPY8]](s64), implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY11]](s64), [[COPY9]](s64), implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[V_CMP_EQ_U64_e64_]](s1), [[V_CMP_EQ_U64_e64_1]](s1), implicit-def dead $scc
+ ; PACKED-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[S_AND_B64_]](s1)
+ ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[COPY12]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.3:
; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
+ ; PACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]](i32), [[COPY5]](i32), [[REG_SEQUENCE]](<4 x s32>), [[COPY6]](i32), 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; PACKED-NEXT: {{ $}}
@@ -150,14 +150,14 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr5
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr6
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vreg_128(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
@@ -166,26 +166,28 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
; UNPACKED-NEXT: bb.2:
; UNPACKED-NEXT: successors: %bb.3(0x80000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128(<4 x s32>) = REG_SEQUENCE [[INTRINSIC_CONVERGENT]](s32), %subreg.sub0, [[INTRINSIC_CONVERGENT1]](s32), %subreg.sub1, [[INTRINSIC_CONVERGENT2]](s32), %subreg.sub2, [[INTRINSIC_CONVERGENT3]](s32), %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub0_sub1(<4 x s32>)
+ ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub2_sub3(<4 x s32>)
+ ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub0_sub1(<4 x s32>)
+ ; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub2_sub3(<4 x s32>)
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY10]](s64), [[COPY8]](s64), implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY11]](s64), [[COPY9]](s64), implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[V_CMP_EQ_U64_e64_]](s1), [[V_CMP_EQ_U64_e64_1]](s1), implicit-def dead $scc
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(i32) = V_READFIRSTLANE_B32 [[COPY6]](i32), implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](i32), [[COPY6]](i32), implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[S_AND_B64_]](s1), [[V_CMP_EQ_U32_e64_]](s1), implicit-def dead $scc
+ ; UNPACKED-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[S_AND_B64_1]](s1)
+ ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[COPY12]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.3:
; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
+ ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]](i32), [[COPY5]](i32), [[REG_SEQUENCE]](<4 x s32>), [[V_READFIRSTLANE_B32_]](i32), 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; UNPACKED-NEXT: {{ $}}
@@ -202,14 +204,14 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr5
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr6
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vreg_128(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
@@ -218,26 +220,28 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
; PACKED-NEXT: bb.2:
; PACKED-NEXT: successors: %bb.3(0x80000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128(<4 x s32>) = REG_SEQUENCE [[INTRINSIC_CONVERGENT]](s32), %subreg.sub0, [[INTRINSIC_CONVERGENT1]](s32), %subreg.sub1, [[INTRINSIC_CONVERGENT2]](s32), %subreg.sub2, [[INTRINSIC_CONVERGENT3]](s32), %subreg.sub3
+ ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub0_sub1(<4 x s32>)
+ ; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub2_sub3(<4 x s32>)
+ ; PACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub0_sub1(<4 x s32>)
+ ; PACKED-NEXT: [[COPY11:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub2_sub3(<4 x s32>)
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY10]](s64), [[COPY8]](s64), implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY11]](s64), [[COPY9]](s64), implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[V_CMP_EQ_U64_e64_]](s1), [[V_CMP_EQ_U64_e64_1]](s1), implicit-def dead $scc
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(i32) = V_READFIRSTLANE_B32 [[COPY6]](i32), implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](i32), [[COPY6]](i32), implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[S_AND_B64_]](s1), [[V_CMP_EQ_U32_e64_]](s1), implicit-def dead $scc
+ ; PACKED-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[S_AND_B64_1]](s1)
+ ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[COPY12]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.3:
; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
+ ; PACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]](i32), [[COPY5]](i32), [[REG_SEQUENCE]](<4 x s32>), [[V_READFIRSTLANE_B32_]](i32), 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; PACKED-NEXT: {{ $}}
@@ -259,43 +263,45 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs
; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr5
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vreg_128(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
+ ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32(i32) = COPY [[COPY5]](i32)
; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.2:
; UNPACKED-NEXT: successors: %bb.3(0x80000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
+ ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128(<4 x s32>) = REG_SEQUENCE [[INTRINSIC_CONVERGENT]](s32), %subreg.sub0, [[INTRINSIC_CONVERGENT1]](s32), %subreg.sub1, [[INTRINSIC_CONVERGENT2]](s32), %subreg.sub2, [[INTRINSIC_CONVERGENT3]](s32), %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub0_sub1(<4 x s32>)
+ ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub2_sub3(<4 x s32>)
+ ; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub0_sub1(<4 x s32>)
+ ; UNPACKED-NEXT: [[COPY12:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub2_sub3(<4 x s32>)
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY11]](s64), [[COPY9]](s64), implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY12]](s64), [[COPY10]](s64), implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[V_CMP_EQ_U64_e64_]](s1), [[V_CMP_EQ_U64_e64_1]](s1), implicit-def dead $scc
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(i32) = V_READFIRSTLANE_B32 [[COPY6]](i32), implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](i32), [[COPY6]](i32), implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[S_AND_B64_]](s1), [[V_CMP_EQ_U32_e64_]](s1), implicit-def dead $scc
+ ; UNPACKED-NEXT: [[COPY13:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[S_AND_B64_1]](s1)
+ ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[COPY13]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.3:
; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
+ ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]](i32), [[COPY8]](i32), [[REG_SEQUENCE]](<4 x s32>), [[V_READFIRSTLANE_B32_]](i32), 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; UNPACKED-NEXT: {{ $}}
@@ -312,43 +318,45 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs
; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
; PACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr5
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vreg_128(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
+ ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32(i32) = COPY [[COPY5]](i32)
; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.2:
; PACKED-NEXT: successors: %bb.3(0x80000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
+ ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sreg_32(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128(<4 x s32>) = REG_SEQUENCE [[INTRINSIC_CONVERGENT]](s32), %subreg.sub0, [[INTRINSIC_CONVERGENT1]](s32), %subreg.sub1, [[INTRINSIC_CONVERGENT2]](s32), %subreg.sub2, [[INTRINSIC_CONVERGENT3]](s32), %subreg.sub3
+ ; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub0_sub1(<4 x s32>)
+ ; PACKED-NEXT: [[COPY10:%[0-9]+]]:vreg_64(s64) = COPY [[BUILD_VECTOR]].sub2_sub3(<4 x s32>)
+ ; PACKED-NEXT: [[COPY11:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub0_sub1(<4 x s32>)
+ ; PACKED-NEXT: [[COPY12:%[0-9]+]]:sreg_64(s64) = COPY [[REG_SEQUENCE]].sub2_sub3(<4 x s32>)
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY11]](s64), [[COPY9]](s64), implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U64_e64 [[COPY12]](s64), [[COPY10]](s64), implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[V_CMP_EQ_U64_e64_]](s1), [[V_CMP_EQ_U64_e64_1]](s1), implicit-def dead $scc
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(i32) = V_READFIRSTLANE_B32 [[COPY6]](i32), implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec(s1) = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](i32), [[COPY6]](i32), implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B64 [[S_AND_B64_]](s1), [[V_CMP_EQ_U32_e64_]](s1), implicit-def dead $scc
+ ; PACKED-NEXT: [[COPY13:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[S_AND_B64_1]](s1)
+ ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[COPY13]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.3:
; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
+ ; PACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]](i32), [[COPY8]](i32), [[REG_SEQUENCE]](<4 x s32>), [[V_READFIRSTLANE_B32_]](i32), 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8) into %ir.rsrc, addrspace 8)
; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; PACKED-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
index a8a0d3b7708d0..3458ff092d67b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
@@ -8,41 +8,47 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
; GFX12: bb.1 (%ir-block.0):
; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
@@ -50,9 +56,10 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
ret void
@@ -244,100 +251,40 @@ define amdgpu_ps void @raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_so
define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset(half %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset
; UNPACKED: bb.1 (%ir-block.0):
- ; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.2:
- ; UNPACKED-NEXT: successors: %bb.3(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT4]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.3:
- ; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
- ; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.4:
- ; UNPACKED-NEXT: successors: %bb.5(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.5:
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
- ; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.2:
- ; PACKED-NEXT: successors: %bb.3(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT4]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.3:
- ; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
- ; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.4:
- ; PACKED-NEXT: successors: %bb.5(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.5:
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset
@@ -345,7 +292,9 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: successors: %bb.2(0x80000000)
; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
@@ -353,6 +302,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF
@@ -377,7 +327,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX12-NEXT: {{ $}}
@@ -396,106 +346,40 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soffset(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset) {
; UNPACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soffset
; UNPACKED: bb.1 (%ir-block.0):
- ; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.2:
- ; UNPACKED-NEXT: successors: %bb.3(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.3:
- ; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
- ; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.4:
- ; UNPACKED-NEXT: successors: %bb.5(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.5:
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soffset
; PACKED: bb.1 (%ir-block.0):
- ; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.2:
- ; PACKED-NEXT: successors: %bb.3(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.3:
- ; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
- ; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.4:
- ; PACKED-NEXT: successors: %bb.5(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.5:
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soffset
@@ -503,7 +387,9 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
; GFX12-NEXT: successors: %bb.2(0x80000000)
; GFX12-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
@@ -511,6 +397,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GFX12-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF
@@ -538,7 +425,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX12-NEXT: {{ $}}
@@ -557,108 +444,40 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset(half %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {
; UNPACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset
; UNPACKED: bb.1 (%ir-block.0):
- ; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.2:
- ; UNPACKED-NEXT: successors: %bb.3(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.3:
- ; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
- ; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.4:
- ; UNPACKED-NEXT: successors: %bb.5(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.5:
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset
; PACKED: bb.1 (%ir-block.0):
- ; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.2:
- ; PACKED-NEXT: successors: %bb.3(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.3:
- ; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
- ; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.4:
- ; PACKED-NEXT: successors: %bb.5(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.5:
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr5
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset
@@ -666,7 +485,9 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
; GFX12-NEXT: successors: %bb.2(0x80000000)
; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
@@ -674,6 +495,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
@@ -702,7 +524,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 78, 0, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX12-NEXT: {{ $}}
@@ -722,41 +544,47 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
; GFX12: bb.1 (%ir-block.0):
; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
@@ -764,9 +592,10 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 1, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)
ret void
@@ -777,41 +606,47 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
; GFX12: bb.1 (%ir-block.0):
; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
@@ -819,9 +654,10 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 2, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)
ret void
@@ -832,41 +668,47 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
; GFX12: bb.1 (%ir-block.0):
; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
@@ -874,9 +716,10 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 3, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)
ret void
@@ -887,41 +730,47 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[C]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
; GFX12: bb.1 (%ir-block.0):
; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
@@ -929,9 +778,10 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 78, 4, 0 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
index 552e96df676cf..f0f688f3fd1a7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
@@ -1,58 +1,52 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s
define amdgpu_ps void @raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i8 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; PACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset
; GFX12: bb.1 (%ir-block.0):
; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.i8(i8 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
ret void
@@ -65,39 +59,37 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.2:
; UNPACKED-NEXT: successors: %bb.3(0x80000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT4]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
+ ; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
+ ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.3:
; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; UNPACKED-NEXT: {{ $}}
@@ -114,39 +106,37 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.2:
; PACKED-NEXT: successors: %bb.3(0x80000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT4]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
+ ; PACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; PACKED-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; PACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
+ ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.3:
; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; PACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; PACKED-NEXT: {{ $}}
@@ -163,39 +153,37 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
; GFX12-NEXT: successors: %bb.2(0x80000000)
; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.2:
; GFX12-NEXT: successors: %bb.3(0x80000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; GFX12-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; GFX12-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; GFX12-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; GFX12-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; GFX12-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND]](s1)
- ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[INTRINSIC_CONVERGENT4]](s32), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; GFX12-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
+ ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[COPY6]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX12-NEXT: {{ $}}
@@ -217,42 +205,40 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.2:
; UNPACKED-NEXT: successors: %bb.3(0x80000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
+ ; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[S_AND_B64_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
+ ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.3:
; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; UNPACKED-NEXT: {{ $}}
@@ -269,42 +255,40 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.2:
; PACKED-NEXT: successors: %bb.3(0x80000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
+ ; PACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; PACKED-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; PACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[S_AND_B64_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
+ ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.3:
; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; PACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; PACKED-NEXT: {{ $}}
@@ -321,42 +305,40 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
; GFX12-NEXT: successors: %bb.2(0x80000000)
; GFX12-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr6
- ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.2:
; GFX12-NEXT: successors: %bb.3(0x80000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; GFX12-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; GFX12-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; GFX12-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; GFX12-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; GFX12-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; GFX12-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; GFX12-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[INTRINSIC_CONVERGENT5]](s32), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; GFX12-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
+ ; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec
+ ; GFX12-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
+ ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_1]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY5]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX12-NEXT: {{ $}}
@@ -378,43 +360,41 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs
; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; UNPACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.2:
; UNPACKED-NEXT: successors: %bb.3(0x80000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
+ ; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
+ ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
+ ; UNPACKED-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec
+ ; UNPACKED-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[S_AND_B64_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
+ ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec
; UNPACKED-NEXT: {{ $}}
; UNPACKED-NEXT: bb.3:
; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; UNPACKED-NEXT: {{ $}}
@@ -431,43 +411,41 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs
; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; PACKED-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.2:
; PACKED-NEXT: successors: %bb.3(0x80000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
+ ; PACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; PACKED-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; PACKED-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
+ ; PACKED-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
+ ; PACKED-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec
+ ; PACKED-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[S_AND_B64_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
+ ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec
; PACKED-NEXT: {{ $}}
; PACKED-NEXT: bb.3:
; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; PACKED-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; PACKED-NEXT: {{ $}}
@@ -484,43 +462,41 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs
; GFX12-NEXT: successors: %bb.2(0x80000000)
; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr5
- ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; GFX12-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.2:
; GFX12-NEXT: successors: %bb.3(0x80000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; GFX12-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; GFX12-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; GFX12-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; GFX12-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; GFX12-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
- ; GFX12-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY6]]
- ; GFX12-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[INTRINSIC_CONVERGENT5]](s32), implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec
+ ; GFX12-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
+ ; GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
+ ; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec
+ ; GFX12-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
+ ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_1]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: G_AMDGPU_TBUFFER_STORE_FORMAT [[COPY]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY7]](s32), [[COPY8]], [[INTRINSIC_CONVERGENT4]], 0, 94, 0, 0 :: (dereferenceable store (i8), addrspace 8)
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8)
; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX12-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
index 02afc5c7d0286..474d20695343f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
@@ -466,8 +466,8 @@ define amdgpu_ps half @struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vg
; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
; UNPACKED-NEXT: [[INT:%[0-9]+]]:_(i16) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.struct.buffer.load.format), [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), 0 :: (dereferenceable load (i16), align 1, addrspace 8)
; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[INT]](i16)
- ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
- ; UNPACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
;
; PACKED-LABEL: name: struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
@@ -484,8 +484,8 @@ define amdgpu_ps half @struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vg
; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
; PACKED-NEXT: [[INT:%[0-9]+]]:_(i16) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.struct.buffer.load.format), [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), 0 :: (dereferenceable load (i16), align 1, addrspace 8)
; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[INT]](i16)
- ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
- ; PACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
;
; GFX12-LABEL: name: struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
@@ -503,8 +503,8 @@ define amdgpu_ps half @struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vg
; GFX12-NEXT: [[AMDGPU_BUFFER_LOAD_FORMAT_D16_:%[0-9]+]]:vgpr_32(s32) = G_AMDGPU_BUFFER_LOAD_FORMAT_D16 [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), [[COPY5]], [[COPY6]], 0, 0, -1 :: (dereferenceable load (i16), align 1, addrspace 8)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_16(i16) = COPY [[AMDGPU_BUFFER_LOAD_FORMAT_D16_]].lo16(s32)
; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_16(f16) = COPY [[COPY7]](i16)
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY8]](f16)
- ; GFX12-NEXT: $vgpr0 = COPY [[COPY9]](s32)
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32(i32) = COPY [[COPY8]](f16)
+ ; GFX12-NEXT: $vgpr0 = COPY [[COPY9]](i32)
; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%val = call i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
%fval = bitcast i16 %val to half
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
index f62fcd05ee52c..03a8db30c9dc8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
@@ -8,39 +8,47 @@ define amdgpu_ps void @struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
; GFX12: bb.1 (%ir-block.0):
; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:vgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
@@ -49,7 +57,8 @@ define amdgpu_ps void @struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
; GFX12-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; GFX12-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; GFX12-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.struct.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
ret void
@@ -249,118 +258,49 @@ define amdgpu_ps void @struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vg
define amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(half inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
; UNPACKED-LABEL: name: struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
; UNPACKED: bb.1 (%ir-block.0):
- ; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[COPY6]](i32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.2:
- ; UNPACKED-NEXT: successors: %bb.3(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY7]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.3:
- ; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY8]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY9]](i32), [[COPY10]], [[INTRINSIC_CONVERGENT4]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
- ; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.4:
- ; UNPACKED-NEXT: successors: %bb.5(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.5:
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
; PACKED: bb.1 (%ir-block.0):
- ; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr3
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; PACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; PACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[COPY6]](i32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.2:
- ; PACKED-NEXT: successors: %bb.3(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY7]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.3:
- ; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY8]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY9]](i32), [[COPY10]], [[INTRINSIC_CONVERGENT4]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
- ; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.4:
- ; PACKED-NEXT: successors: %bb.5(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.5:
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
; GFX12: bb.1 (%ir-block.0):
- ; GFX12-NEXT: successors: %bb.2(0x80000000)
; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:sgpr(f16) = G_BITCAST [[TRUNC]](i16)
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
@@ -369,44 +309,8 @@ define amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr
; GFX12-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[COPY6]](i32)
- ; GFX12-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF
- ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: bb.2:
- ; GFX12-NEXT: successors: %bb.3(0x80000000)
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](i32)
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](i32)
- ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32), [[INTRINSIC_CONVERGENT2]](i32), [[INTRINSIC_CONVERGENT3]](i32)
- ; GFX12-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x i32>)
- ; GFX12-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x i32>)
- ; GFX12-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; GFX12-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; GFX12-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
- ; GFX12-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY7]]
- ; GFX12-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; GFX12-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[INTRINSIC_CONVERGENT5]](s32), implicit-def $exec, implicit-def $scc, implicit $exec
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: bb.3:
- ; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY8]](s32), [[BUILD_VECTOR1]](<4 x i32>), [[COPY9]](i32), [[COPY10]], [[INTRINSIC_CONVERGENT4]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
- ; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
- ; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: bb.4:
- ; GFX12-NEXT: successors: %bb.5(0x80000000)
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]]
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: bb.5:
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; GFX12-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.struct.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
ret void
@@ -417,48 +321,51 @@ define amdgpu_ps void @struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (i16), align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
+ ; UNPACKED-NEXT: BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i16), align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (i16), align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; PACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
+ ; PACKED-NEXT: BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i16), align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
; GFX12: bb.1 (%ir-block.0):
; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; GFX12-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x i32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (i16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
+ ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.struct.buffer.store.format.i16(i16 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
index d3a35267af8eb..e36b45f5de664 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
@@ -341,8 +341,8 @@ define amdgpu_ps half @struct_ptr_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex
; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
; UNPACKED-NEXT: [[INT:%[0-9]+]]:_(i16) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.struct.ptr.buffer.load.format), [[MV]](p8), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), 0 :: (dereferenceable load (i16) from %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[INT]](i16)
- ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
- ; UNPACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
;
; PACKED-LABEL: name: struct_ptr_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
@@ -359,8 +359,8 @@ define amdgpu_ps half @struct_ptr_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex
; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6
; PACKED-NEXT: [[INT:%[0-9]+]]:_(i16) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.struct.ptr.buffer.load.format), [[MV]](p8), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), 0 :: (dereferenceable load (i16) from %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[INT]](i16)
- ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
- ; PACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%val = call i16 @llvm.amdgcn.struct.ptr.buffer.load.format.i16(ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
%fval = bitcast i16 %val to half
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
index 8030b1d966067..90f0f218f6c94 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
@@ -7,32 +7,42 @@ define amdgpu_ps void @struct_ptr_buffer_store_format_f16__vgpr_val__sgpr_rsrc__
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: struct_ptr_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr5
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr6
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.struct.ptr.buffer.store.format.f16(half %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
ret void
@@ -177,110 +187,44 @@ define amdgpu_ps void @struct_ptr_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc
define amdgpu_ps void @struct_ptr_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(half inreg %val, ptr addrspace(8) %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
; UNPACKED-LABEL: name: struct_ptr_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
; UNPACKED: bb.1 (%ir-block.0):
- ; UNPACKED-NEXT: successors: %bb.2(0x80000000)
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[COPY6]](i32)
- ; UNPACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.2:
- ; UNPACKED-NEXT: successors: %bb.3(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; UNPACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; UNPACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; UNPACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; UNPACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
- ; UNPACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY7]]
- ; UNPACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; UNPACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; UNPACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.3:
- ; UNPACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY8]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY9]](i32), [[COPY10]], [[INTRINSIC_CONVERGENT4]], 0, 0, -1 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
- ; UNPACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; UNPACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.4:
- ; UNPACKED-NEXT: successors: %bb.5(0x80000000)
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: bb.5:
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; UNPACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; UNPACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; UNPACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: struct_ptr_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
; PACKED: bb.1 (%ir-block.0):
- ; PACKED-NEXT: successors: %bb.2(0x80000000)
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY $vgpr4
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; PACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32)
- ; PACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[COPY6]](i32)
- ; PACKED-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.2:
- ; PACKED-NEXT: successors: %bb.3(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY3]](s32)
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY4]](s32)
- ; PACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32), [[INTRINSIC_CONVERGENT2]](s32), [[INTRINSIC_CONVERGENT3]](s32)
- ; PACKED-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
- ; PACKED-NEXT: [[UV2:%[0-9]+]]:sgpr(s64), [[UV3:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
- ; PACKED-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV2]](s64), [[UV]]
- ; PACKED-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV3]](s64), [[UV1]]
- ; PACKED-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
- ; PACKED-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[INTRINSIC_CONVERGENT4]](i32), [[COPY7]]
- ; PACKED-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AND]], [[ICMP2]]
- ; PACKED-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[AND1]](s1)
- ; PACKED-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT5]](s64), implicit-def $exec, implicit-def $scc, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.3:
- ; PACKED-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY8]](s32), [[BUILD_VECTOR1]](<4 x s32>), [[COPY9]](i32), [[COPY10]], [[INTRINSIC_CONVERGENT4]], 0, 0, -1 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
- ; PACKED-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
- ; PACKED-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.4:
- ; PACKED-NEXT: successors: %bb.5(0x80000000)
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
- ; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: bb.5:
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2
+ ; PACKED-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; PACKED-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr3
+ ; PACKED-NEXT: [[MV:%[0-9]+]]:_(p8) = G_MERGE_VALUES [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $vgpr4
+ ; PACKED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](f16)
+ ; PACKED-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p8)
+ ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[ANYEXT]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (f16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.struct.ptr.buffer.store.format.f16(half %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
ret void
@@ -291,32 +235,34 @@ define amdgpu_ps void @struct_ptr_buffer_store_format_i16__vgpr_val__sgpr_rsrc__
; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; UNPACKED-NEXT: {{ $}}
- ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; UNPACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; UNPACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (i16) into %ir.rsrc, align 1, addrspace 8)
+ ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
+ ; UNPACKED-NEXT: BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i16) into %ir.rsrc, align 1, addrspace 8)
; UNPACKED-NEXT: S_ENDPGM 0
;
; PACKED-LABEL: name: struct_ptr_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
; PACKED: bb.1 (%ir-block.0):
; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; PACKED-NEXT: {{ $}}
- ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
- ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
- ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
- ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
- ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY $vgpr1
- ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY $vgpr2
- ; PACKED-NEXT: [[COPY7:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
- ; PACKED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
- ; PACKED-NEXT: G_AMDGPU_BUFFER_STORE_FORMAT_D16 [[COPY]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](i32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store (i16) into %ir.rsrc, align 1, addrspace 8)
+ ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; PACKED-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; PACKED-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
+ ; PACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
+ ; PACKED-NEXT: BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i16) into %ir.rsrc, align 1, addrspace 8)
; PACKED-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.struct.ptr.buffer.store.format.i16(i16 %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
index ba9416764b9e5..44cba2b4904c0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10-32 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=GFX10-64 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10-32 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=GFX10-64 %s
define amdgpu_ps void @static_exact(float %arg0, float %arg1) {
; SI-LABEL: static_exact:
@@ -984,17 +984,18 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index
; GFX9-NEXT: .LBB7_5: ; %.continue0
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v0, s6
-; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
+; GFX9-NEXT: s_mov_b64 s[8:9], s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[8:9]
; GFX9-NEXT: v_mov_b32_e32 v2, v0
-; GFX9-NEXT: s_xor_b64 s[4:5], s[0:1], -1
+; GFX9-NEXT: s_mov_b64 s[4:5], exec
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
-; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; GFX9-NEXT: s_and_b64 s[8:9], s[0:1], vcc
+; GFX9-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]
; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; GFX9-NEXT: s_cbranch_execz .LBB7_4
@@ -1010,9 +1011,9 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index
; GFX9-NEXT: .LBB7_8: ; %.return
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
-; GFX9-NEXT: v_bfrev_b32_e32 v0, 60
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x3c00
-; GFX9-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00
+; GFX9-NEXT: v_bfrev_b32_e32 v1, 60
+; GFX9-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm
; GFX9-NEXT: s_endpgm
; GFX9-NEXT: .LBB7_9:
; GFX9-NEXT: s_mov_b64 exec, 0
@@ -1049,15 +1050,16 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index
; GFX10-32-NEXT: s_cbranch_execz .LBB7_8
; GFX10-32-NEXT: .LBB7_5: ; %.continue0
; GFX10-32-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-32-NEXT: s_mov_b32 s3, s0
-; GFX10-32-NEXT: v_cndmask_b32_e64 v0, s2, 0, s3
-; GFX10-32-NEXT: s_xor_b32 s3, s0, -1
+; GFX10-32-NEXT: s_mov_b32 s4, s0
+; GFX10-32-NEXT: s_mov_b32 s3, exec_lo
+; GFX10-32-NEXT: v_cndmask_b32_e64 v0, s2, 0, s4
; GFX10-32-NEXT: v_mov_b32_e32 v2, v0
; GFX10-32-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
-; GFX10-32-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
-; GFX10-32-NEXT: s_or_b32 s3, s3, vcc_lo
+; GFX10-32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX10-32-NEXT: s_and_b32 s4, s0, vcc_lo
+; GFX10-32-NEXT: s_xor_b32 s3, s4, s3
; GFX10-32-NEXT: s_and_saveexec_b32 s4, s3
; GFX10-32-NEXT: s_xor_b32 s3, exec_lo, s4
; GFX10-32-NEXT: s_cbranch_execz .LBB7_4
@@ -1073,9 +1075,9 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index
; GFX10-32-NEXT: .LBB7_8: ; %.return
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0
-; GFX10-32-NEXT: v_bfrev_b32_e32 v0, 60
-; GFX10-32-NEXT: v_mov_b32_e32 v1, 0x3c00
-; GFX10-32-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm
+; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00
+; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60
+; GFX10-32-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm
; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: .LBB7_9:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
@@ -1112,15 +1114,16 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index
; GFX10-64-NEXT: s_cbranch_execz .LBB7_8
; GFX10-64-NEXT: .LBB7_5: ; %.continue0
; GFX10-64-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-64-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX10-64-NEXT: v_cndmask_b32_e64 v0, s6, 0, s[4:5]
-; GFX10-64-NEXT: s_xor_b64 s[4:5], s[0:1], -1
+; GFX10-64-NEXT: s_mov_b64 s[8:9], s[0:1]
+; GFX10-64-NEXT: s_mov_b64 s[4:5], exec
+; GFX10-64-NEXT: v_cndmask_b32_e64 v0, s6, 0, s[8:9]
; GFX10-64-NEXT: v_mov_b32_e32 v2, v0
; GFX10-64-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
-; GFX10-64-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
-; GFX10-64-NEXT: s_or_b64 s[4:5], s[4:5], vcc
+; GFX10-64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; GFX10-64-NEXT: s_and_b64 s[8:9], s[0:1], vcc
+; GFX10-64-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]
; GFX10-64-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX10-64-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; GFX10-64-NEXT: s_cbranch_execz .LBB7_4
@@ -1136,9 +1139,9 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index
; GFX10-64-NEXT: .LBB7_8: ; %.return
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1]
-; GFX10-64-NEXT: v_bfrev_b32_e32 v0, 60
-; GFX10-64-NEXT: v_mov_b32_e32 v1, 0x3c00
-; GFX10-64-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm
+; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00
+; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60
+; GFX10-64-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm
; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: .LBB7_9:
; GFX10-64-NEXT: s_mov_b64 exec, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
index 092df66fc0d9e..0a01248d713e3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-- -mcpu=gfx600 -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=35 %s -o - | FileCheck -check-prefix=LOOP %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-- -mcpu=gfx600 -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=37 %s -o - | FileCheck -check-prefix=UNROLL %s
+; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx600 -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=37 %s -o - | FileCheck -check-prefix=UNROLL %s
declare void @llvm.memset.p1.i32(ptr addrspace(1), i8, i32, i1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
index 4edc13ffc06dd..f24e498dafd91 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
define <2 x i16> @v_mul_v2i16(<2 x i16> %a, <2 x i16> %b) {
; GFX9-LABEL: v_mul_v2i16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
index 07f0d42912c36..b64a9462d2d1c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
@@ -120,7 +120,7 @@ define amdgpu_kernel void @test_uniform_indirect_call_from_kernel(ptr %fptr) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14
@@ -149,7 +149,7 @@ define amdgpu_kernel void @test_uniform_indirect_call_from_kernel(ptr %fptr) {
; CHECK-NEXT: $sgpr13 = COPY [[COPY12]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY13]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[LOAD]](p0), 0, csr_amdgpu_gfx90ainsts, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index eb1ae1150de51..03cf8c1ccaa23 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -328,16 +328,30 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX8-LABEL: v_saddsat_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_ashrrev_i16_e32 v2, 8, v1
-; GFX8-NEXT: v_ashrrev_i16_e32 v3, 8, v0
-; GFX8-NEXT: v_add_u16_e32 v2, v3, v2
-; GFX8-NEXT: v_add_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-NEXT: v_min_i16_e32 v2, 0x7f, v2
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xffffff80
-; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v0
-; GFX8-NEXT: v_max_i16_sdwa v2, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_max_i16_e32 v0, 0xff80, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v2, 8
+; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
+; GFX8-NEXT: v_min_i16_e32 v5, 0, v0
+; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_max_i16_e32 v4, 0, v0
+; GFX8-NEXT: v_sub_u16_e32 v5, 0x8000, v5
+; GFX8-NEXT: v_sub_u16_e32 v4, 0x7fff, v4
+; GFX8-NEXT: v_max_i16_e32 v1, v5, v1
+; GFX8-NEXT: v_min_i16_e32 v1, v1, v4
+; GFX8-NEXT: v_min_i16_e32 v4, 0, v3
+; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_max_i16_e32 v1, 0, v3
+; GFX8-NEXT: v_sub_u16_e32 v4, 0x8000, v4
+; GFX8-NEXT: v_sub_u16_e32 v1, 0x7fff, v1
+; GFX8-NEXT: v_max_i16_e32 v2, v4, v2
+; GFX8-NEXT: v_min_i16_e32 v1, v2, v1
+; GFX8-NEXT: v_add_u16_e32 v1, v3, v1
+; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_saddsat_v2i8:
@@ -369,15 +383,18 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX11-TRUE16-LABEL: v_saddsat_v2i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff00, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff00, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_i16 v0, v0, v1 clamp
+; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.h, v1.h, v0.h clamp
-; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, v0.l, v1.l clamp
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff00, v0.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_saddsat_v2i8:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
index b117baee09b18..6b85057d93082 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
@@ -5,8 +5,8 @@ define half @test_s16(half %a) #0 {
; GCN-LABEL: test_s16:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GCN-NEXT: v_cmp_ngt_f16_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
entry:
%fcmp = fcmp olt half %a, 0.0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
index 9561a79111635..d99e3832deb46 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx802 < %s | FileCheck -check-prefixes=GFX89,GFX8 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX89,GFX9 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX89,GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
define i32 @test_min_max_ValK0_K1_i32(i32 %a) {
; GFX89-LABEL: test_min_max_ValK0_K1_i32:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
index 5524e8b1d3ef9..885d04672478f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=SI %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250 %s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index a158a82b17c50..1973318a15513 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -328,16 +328,30 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX8-LABEL: v_ssubsat_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_ashrrev_i16_e32 v2, 8, v1
-; GFX8-NEXT: v_ashrrev_i16_e32 v3, 8, v0
-; GFX8-NEXT: v_sub_u16_e32 v2, v3, v2
-; GFX8-NEXT: v_sub_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-NEXT: v_min_i16_e32 v2, 0x7f, v2
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xffffff80
-; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v0
-; GFX8-NEXT: v_max_i16_sdwa v2, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_max_i16_e32 v0, 0xff80, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v2, 8
+; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
+; GFX8-NEXT: v_max_i16_e32 v4, -1, v0
+; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_add_u16_e32 v4, 0x8001, v4
+; GFX8-NEXT: v_min_i16_e32 v5, -1, v0
+; GFX8-NEXT: v_add_u16_e32 v5, 0x8000, v5
+; GFX8-NEXT: v_max_i16_e32 v1, v4, v1
+; GFX8-NEXT: v_min_i16_e32 v1, v1, v5
+; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_max_i16_e32 v1, -1, v3
+; GFX8-NEXT: v_add_u16_e32 v1, 0x8001, v1
+; GFX8-NEXT: v_min_i16_e32 v4, -1, v3
+; GFX8-NEXT: v_add_u16_e32 v4, 0x8000, v4
+; GFX8-NEXT: v_max_i16_e32 v1, v1, v2
+; GFX8-NEXT: v_min_i16_e32 v1, v1, v4
+; GFX8-NEXT: v_sub_u16_e32 v1, v3, v1
+; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v2i8:
@@ -369,15 +383,18 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX11-TRUE16-LABEL: v_ssubsat_v2i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff00, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff00, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
+; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
-; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.h, v1.h, v0.h clamp
-; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, v0.l, v1.l clamp
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff00, v0.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_ssubsat_v2i8:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
index c47d9a4e6774d..2ef329be39c76 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
; FIXME:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
index 54f5d8e3ccb45..23d765ea4a48e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
; FIXME:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
index 795a12fa06a4e..ea71106c677d9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
@@ -83,10 +83,10 @@ define void @v_constained_fma_f16_fpexcept_strict_div(half %x, half %y, half %z,
; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_div:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, v3
-; GFX942-NEXT: v_mov_b32_e32 v7, v4
+; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v4, v3
; GFX942-NEXT: v_fma_f16 v0, v0, v1, v2
-; GFX942-NEXT: global_store_short v[6:7], v0, off
+; GFX942-NEXT: global_store_short v[4:5], v0, off
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
;
@@ -531,10 +531,10 @@ define void @v_constained_fma_f16_fpexcept_strict_fneg_div(half %x, half %y, hal
; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_div:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, v3
-; GFX942-NEXT: v_mov_b32_e32 v7, v4
+; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v4, v3
; GFX942-NEXT: v_fma_f16 v0, v0, v1, -v2
-; GFX942-NEXT: global_store_short v[6:7], v0, off
+; GFX942-NEXT: global_store_short v[4:5], v0, off
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
;
@@ -644,10 +644,10 @@ define void @v_constained_fma_f16_fpexcept_strict_fneg_fneg_div(half %x, half %y
; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_div:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, v3
-; GFX942-NEXT: v_mov_b32_e32 v7, v4
+; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v4, v3
; GFX942-NEXT: v_fma_f16 v0, -v0, -v1, v2
-; GFX942-NEXT: global_store_short v[6:7], v0, off
+; GFX942-NEXT: global_store_short v[4:5], v0, off
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
;
@@ -758,10 +758,10 @@ define void @v_constained_fma_f16_fpexcept_strict_fabs_fabs_div(half %x, half %y
; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_div:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, v3
-; GFX942-NEXT: v_mov_b32_e32 v7, v4
+; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v4, v3
; GFX942-NEXT: v_fma_f16 v0, |v0|, |v1|, v2
-; GFX942-NEXT: global_store_short v[6:7], v0, off
+; GFX942-NEXT: global_store_short v[4:5], v0, off
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
index 5ba77fcb163d7..9909e080130ca 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX12 %s
define i16 @s_sub_i16(i16 inreg %a, i16 inreg %b) {
; GFX7-LABEL: s_sub_i16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
index 6fa1dcb294e70..0365952bb2339 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
@@ -231,12 +231,16 @@ define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX8-LABEL: v_uaddsat_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xff
-; GFX8-NEXT: v_min_u16_e32 v2, 0xff, v2
-; GFX8-NEXT: v_min_u16_sdwa v0, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 8
+; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
+; GFX8-NEXT: v_add_u16_e64 v1, v3, v2 clamp
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v2i8:
@@ -268,16 +272,16 @@ define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX11-TRUE16-LABEL: v_uaddsat_v2i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 8, v1.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.h, 8, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v1.h, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1 clamp
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_uaddsat_v2i8:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
index a380f15689775..e77069b693c1f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx802 < %s | FileCheck -check-prefixes=GFX89,GFX8 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX89,GFX9 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX89,GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
define i32 @test_min_max_ValK0_K1_u32(i32 %a) {
; GFX89-LABEL: test_min_max_ValK0_K1_u32:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
index 10764c12c96af..f24e6327cf021 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
@@ -219,9 +219,16 @@ define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX8-LABEL: v_usubsat_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 8
+; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
+; GFX8-NEXT: v_sub_u16_e64 v1, v3, v2 clamp
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v2i8:
@@ -248,14 +255,16 @@ define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX11-TRUE16-LABEL: v_usubsat_v2i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 8, v1.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.h, 8, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.h, v1.h, v0.h clamp
-; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, v0.l, v1.l clamp
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_usubsat_v2i8:
diff --git a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
index b364c3c3f16bd..8ff8e6c6b2a70 100644
--- a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
+++ b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefixes=FIXEDABI,FIXEDABI-SDAG %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefixes=FIXEDABI,FIXEDABI-GISEL %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefixes=FIXEDABI,FIXEDABI-GISEL %s
; Test with gfx803 so that
; addrspacecast/llvm.amdgcn.is.shared/llvm.amdgcn.is.private require
@@ -45,27 +45,49 @@ define void @parent_func_missing_inputs() #0 {
}
define amdgpu_kernel void @parent_kernel_missing_inputs() #0 {
-; FIXEDABI-LABEL: parent_kernel_missing_inputs:
-; FIXEDABI: ; %bb.0:
-; FIXEDABI-NEXT: s_add_i32 s4, s4, s9
-; FIXEDABI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
-; FIXEDABI-NEXT: s_add_u32 s0, s0, s9
-; FIXEDABI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; FIXEDABI-NEXT: s_addc_u32 s1, s1, 0
-; FIXEDABI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; FIXEDABI-NEXT: v_or_b32_e32 v0, v0, v1
-; FIXEDABI-NEXT: s_mov_b32 flat_scratch_lo, s5
-; FIXEDABI-NEXT: s_mov_b32 s14, s8
-; FIXEDABI-NEXT: s_getpc_b64 s[4:5]
-; FIXEDABI-NEXT: s_add_u32 s4, s4, requires_all_inputs at rel32@lo+4
-; FIXEDABI-NEXT: s_addc_u32 s5, s5, requires_all_inputs at rel32@hi+12
-; FIXEDABI-NEXT: v_or_b32_e32 v31, v0, v2
-; FIXEDABI-NEXT: s_mov_b64 s[8:9], 0
-; FIXEDABI-NEXT: s_mov_b32 s12, s6
-; FIXEDABI-NEXT: s_mov_b32 s13, s7
-; FIXEDABI-NEXT: s_mov_b32 s32, 0
-; FIXEDABI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; FIXEDABI-NEXT: s_endpgm
+; FIXEDABI-SDAG-LABEL: parent_kernel_missing_inputs:
+; FIXEDABI-SDAG: ; %bb.0:
+; FIXEDABI-SDAG-NEXT: s_add_i32 s4, s4, s9
+; FIXEDABI-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
+; FIXEDABI-SDAG-NEXT: s_add_u32 s0, s0, s9
+; FIXEDABI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; FIXEDABI-SDAG-NEXT: s_addc_u32 s1, s1, 0
+; FIXEDABI-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; FIXEDABI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; FIXEDABI-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s5
+; FIXEDABI-SDAG-NEXT: s_mov_b32 s14, s8
+; FIXEDABI-SDAG-NEXT: s_getpc_b64 s[4:5]
+; FIXEDABI-SDAG-NEXT: s_add_u32 s4, s4, requires_all_inputs at rel32@lo+4
+; FIXEDABI-SDAG-NEXT: s_addc_u32 s5, s5, requires_all_inputs at rel32@hi+12
+; FIXEDABI-SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; FIXEDABI-SDAG-NEXT: s_mov_b64 s[8:9], 0
+; FIXEDABI-SDAG-NEXT: s_mov_b32 s12, s6
+; FIXEDABI-SDAG-NEXT: s_mov_b32 s13, s7
+; FIXEDABI-SDAG-NEXT: s_mov_b32 s32, 0
+; FIXEDABI-SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
+; FIXEDABI-SDAG-NEXT: s_endpgm
+;
+; FIXEDABI-GISEL-LABEL: parent_kernel_missing_inputs:
+; FIXEDABI-GISEL: ; %bb.0:
+; FIXEDABI-GISEL-NEXT: s_add_i32 s4, s4, s9
+; FIXEDABI-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
+; FIXEDABI-GISEL-NEXT: s_add_u32 s0, s0, s9
+; FIXEDABI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; FIXEDABI-GISEL-NEXT: s_addc_u32 s1, s1, 0
+; FIXEDABI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; FIXEDABI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; FIXEDABI-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s5
+; FIXEDABI-GISEL-NEXT: s_mov_b32 s14, s8
+; FIXEDABI-GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; FIXEDABI-GISEL-NEXT: s_getpc_b64 s[4:5]
+; FIXEDABI-GISEL-NEXT: s_add_u32 s4, s4, requires_all_inputs at rel32@lo+4
+; FIXEDABI-GISEL-NEXT: s_addc_u32 s5, s5, requires_all_inputs at rel32@hi+12
+; FIXEDABI-GISEL-NEXT: s_mov_b64 s[8:9], 0
+; FIXEDABI-GISEL-NEXT: s_mov_b32 s12, s6
+; FIXEDABI-GISEL-NEXT: s_mov_b32 s13, s7
+; FIXEDABI-GISEL-NEXT: s_mov_b32 s32, 0
+; FIXEDABI-GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
+; FIXEDABI-GISEL-NEXT: s_endpgm
call void @requires_all_inputs()
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
index 9210bbf29ac10..37f2b8f41c22c 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s
; Test that a null check is not emitted for lowered addrspacecast
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll b/llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
index 666090c274c54..15aa370bd3b1b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "s_setreg_imm32_b32" --filter-out "shader" --version 6
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,REAL16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,REAL16 %s
define amdgpu_ps float @v_sin_f32(float %src) #1 {
; GCN-LABEL: v_sin_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/bitop3.ll b/llvm/test/CodeGen/AMDGPU/bitop3.ll
index 9e6acfc4899ab..95c5771742db0 100644
--- a/llvm/test/CodeGen/AMDGPU/bitop3.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitop3.ll
@@ -4,7 +4,7 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-SDAG-FAKE16,GFX1250-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-SDAG-TRUE16,GFX1250-TRUE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-GISEL-FAKE16,GFX1250-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-GISEL-TRUE16,GFX1250-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-GISEL-TRUE16,GFX1250-TRUE16 %s
; ========= Single bit functions =========
@@ -666,7 +666,7 @@ define amdgpu_ps half @test_xor3_b16(i16 %a, i16 %b, i16 %c) {
; GFX1250-GISEL-TRUE16-LABEL: test_xor3_b16:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0x96
+; GFX1250-GISEL-TRUE16-NEXT: v_xor3_b32 v0, v0, v1, v2
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%xor1 = xor i16 %a, %b
%xor2 = xor i16 %xor1, %c
@@ -701,7 +701,7 @@ define amdgpu_ps half @test_or3_b16(i16 %a, i16 %b, i16 %c) {
; GFX1250-GISEL-TRUE16-LABEL: test_or3_b16:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0xfe
+; GFX1250-GISEL-TRUE16-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%or1 = or i16 %a, %b
%or2 = or i16 %or1, %c
@@ -736,7 +736,7 @@ define amdgpu_ps half @test_and_or_b16(i16 %a, i16 %b, i16 %c) {
; GFX1250-GISEL-TRUE16-LABEL: test_and_or_b16:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0xec
+; GFX1250-GISEL-TRUE16-NEXT: v_and_or_b32 v0, v0, v1, v2
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%and1 = and i16 %a, %b
%or1 = or i16 %and1, %c
diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse.ll b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
index f1773510eeedb..ac8895b2c229b 100644
--- a/llvm/test/CodeGen/AMDGPU/bitreverse.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
@@ -5,7 +5,7 @@
; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -global-isel -global-isel-abort=2 | FileCheck %s --check-prefix=GISEL
; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global | FileCheck %s --check-prefixes=GFX11-FLAT,GFX11-FLAT-TRUE16
; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global | FileCheck %s --check-prefixes=GFX11-FLAT,GFX11-FLAT-FAKE16
-; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=GFX11-GISEL,GFX11-GISEL-TRUE16
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -global-isel | FileCheck %s --check-prefixes=GFX11-GISEL,GFX11-GISEL-TRUE16
; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=GFX11-GISEL,GFX11-GISEL-FAKE16
declare i32 @llvm.amdgcn.workitem.id.x() #1
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
index ba40c94ff0374..3f3b3ea497903 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
@@ -3447,10 +3447,12 @@ define <2 x i6> @load_v2i6(ptr addrspace(8) inreg %buf) {
; GISEL-LABEL: load_v2i6:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: buffer_load_ushort v1, off, s[16:19], 0
+; GISEL-NEXT: buffer_load_ushort v0, off, s[16:19], 0
; GISEL-NEXT: s_waitcnt vmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v0, 63, v1
-; GISEL-NEXT: v_bfe_u32 v1, v1, 6, 6
+; GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-NEXT: s_bfe_u32 s4, s4, 0x100000
+; GISEL-NEXT: s_lshr_b32 s4, s4, 6
+; GISEL-NEXT: v_mov_b32_e32 v1, s4
; GISEL-NEXT: s_setpc_b64 s[30:31]
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%ret = load <2 x i6>, ptr addrspace(7) %p
diff --git a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
index 7896314aef7b4..8227a70643d50 100644
--- a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
@@ -6,7 +6,7 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16,GFX11-FAKE16-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16,GFX11-FAKE16-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16,GFX11-TRUE16-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16,GFX11-TRUE16-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16,GFX11-TRUE16-GISEL %s
define void @undef_lo_v2i16(i16 %arg0) {
; GFX8-LABEL: undef_lo_v2i16:
@@ -81,45 +81,23 @@ define void @undef_lo_v2f16(half %arg0) {
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: undef_lo_v2f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-SDAG-NEXT: ;;#ASMSTART
-; GFX9-SDAG-NEXT: ; use v0
-; GFX9-SDAG-NEXT: ;;#ASMEND
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: undef_lo_v2f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0xffff
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX9-GISEL-NEXT: ;;#ASMSTART
-; GFX9-GISEL-NEXT: ; use v0
-; GFX9-GISEL-NEXT: ;;#ASMEND
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-SDAG-LABEL: undef_lo_v2f16:
-; GFX11-FAKE16-SDAG: ; %bb.0:
-; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-SDAG-NEXT: ; use v0
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMEND
-; GFX11-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: undef_lo_v2f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use v0
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-FAKE16-GISEL-LABEL: undef_lo_v2f16:
-; GFX11-FAKE16-GISEL: ; %bb.0:
-; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e64 v1, 0xffff, s0
-; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-GISEL-NEXT: ; use v0
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
-; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: undef_lo_v2f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: ;;#ASMSTART
+; GFX11-FAKE16-NEXT: ; use v0
+; GFX11-FAKE16-NEXT: ;;#ASMEND
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: undef_lo_v2f16:
; GFX11-TRUE16: ; %bb.0:
@@ -146,50 +124,26 @@ define void @undef_lo_op_v2f16(half %arg0) {
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: undef_lo_op_v2f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-SDAG-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
-; GFX9-SDAG-NEXT: ;;#ASMSTART
-; GFX9-SDAG-NEXT: ; use v0
-; GFX9-SDAG-NEXT: ;;#ASMEND
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: undef_lo_op_v2f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0xffff
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
-; GFX9-GISEL-NEXT: ;;#ASMSTART
-; GFX9-GISEL-NEXT: ; use v0
-; GFX9-GISEL-NEXT: ;;#ASMEND
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-SDAG-LABEL: undef_lo_op_v2f16:
-; GFX11-FAKE16-SDAG: ; %bb.0:
-; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-SDAG-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-SDAG-NEXT: ; use v0
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMEND
-; GFX11-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: undef_lo_op_v2f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use v0
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-FAKE16-GISEL-LABEL: undef_lo_op_v2f16:
-; GFX11-FAKE16-GISEL: ; %bb.0:
-; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e64 v1, 0xffff, s0
-; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX11-FAKE16-GISEL-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-GISEL-NEXT: ; use v0
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
-; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: undef_lo_op_v2f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT: ;;#ASMSTART
+; GFX11-FAKE16-NEXT: ; use v0
+; GFX11-FAKE16-NEXT: ;;#ASMEND
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: undef_lo_op_v2f16:
; GFX11-TRUE16: ; %bb.0:
@@ -365,45 +319,23 @@ define void @undef_lo3_v4f16(half %arg0) {
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: undef_lo3_v4f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-SDAG-NEXT: ;;#ASMSTART
-; GFX9-SDAG-NEXT: ; use v[0:1]
-; GFX9-SDAG-NEXT: ;;#ASMEND
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: undef_lo3_v4f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0xffff
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX9-GISEL-NEXT: ;;#ASMSTART
-; GFX9-GISEL-NEXT: ; use v[0:1]
-; GFX9-GISEL-NEXT: ;;#ASMEND
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-SDAG-LABEL: undef_lo3_v4f16:
-; GFX11-FAKE16-SDAG: ; %bb.0:
-; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-SDAG-NEXT: ; use v[0:1]
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMEND
-; GFX11-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: undef_lo3_v4f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use v[0:1]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-FAKE16-GISEL-LABEL: undef_lo3_v4f16:
-; GFX11-FAKE16-GISEL: ; %bb.0:
-; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e64 v1, 0xffff, s0
-; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-GISEL-NEXT: ; use v[0:1]
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
-; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: undef_lo3_v4f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: ;;#ASMSTART
+; GFX11-FAKE16-NEXT: ; use v[0:1]
+; GFX11-FAKE16-NEXT: ;;#ASMEND
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: undef_lo3_v4f16:
; GFX11-TRUE16: ; %bb.0:
@@ -571,50 +503,21 @@ define void @undef_hi_v2f16(half %arg0) {
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: undef_hi_v2f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: ;;#ASMSTART
-; GFX9-SDAG-NEXT: ; use v0
-; GFX9-SDAG-NEXT: ;;#ASMEND
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: undef_hi_v2f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, s4, 16, v0
-; GFX9-GISEL-NEXT: ;;#ASMSTART
-; GFX9-GISEL-NEXT: ; use v0
-; GFX9-GISEL-NEXT: ;;#ASMEND
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-SDAG-LABEL: undef_hi_v2f16:
-; GFX11-FAKE16-SDAG: ; %bb.0:
-; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-SDAG-NEXT: ; use v0
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMEND
-; GFX11-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-GISEL-LABEL: undef_hi_v2f16:
-; GFX11-FAKE16-GISEL: ; %bb.0:
-; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-GISEL-NEXT: ; use v0
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
-; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: undef_hi_v2f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use v0
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: undef_hi_v2f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-NEXT: ; use v0
-; GFX11-TRUE16-NEXT: ;;#ASMEND
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: undef_hi_v2f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: ;;#ASMSTART
+; GFX11-NEXT: ; use v0
+; GFX11-NEXT: ;;#ASMEND
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%undef.hi = insertelement <2 x half> poison, half %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<2 x half> %undef.hi);
ret void
@@ -631,46 +534,23 @@ define void @undef_hi_op_v2f16(half %arg0) {
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: undef_hi_op_v2f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
-; GFX9-SDAG-NEXT: ;;#ASMSTART
-; GFX9-SDAG-NEXT: ; use v0
-; GFX9-SDAG-NEXT: ;;#ASMEND
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: undef_hi_op_v2f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, s4, 16, v0
-; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
-; GFX9-GISEL-NEXT: ;;#ASMSTART
-; GFX9-GISEL-NEXT: ; use v0
-; GFX9-GISEL-NEXT: ;;#ASMEND
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-SDAG-LABEL: undef_hi_op_v2f16:
-; GFX11-FAKE16-SDAG: ; %bb.0:
-; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-SDAG-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-SDAG-NEXT: ; use v0
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMEND
-; GFX11-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: undef_hi_op_v2f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use v0
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-FAKE16-GISEL-LABEL: undef_hi_op_v2f16:
-; GFX11-FAKE16-GISEL: ; %bb.0:
-; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX11-FAKE16-GISEL-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-GISEL-NEXT: ; use v0
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
-; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: undef_hi_op_v2f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT: ;;#ASMSTART
+; GFX11-FAKE16-NEXT: ; use v0
+; GFX11-FAKE16-NEXT: ;;#ASMEND
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-SDAG-LABEL: undef_hi_op_v2f16:
; GFX11-TRUE16-SDAG: ; %bb.0:
@@ -839,50 +719,21 @@ define void @undef_hi3_v4f16(half %arg0) {
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: undef_hi3_v4f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: ;;#ASMSTART
-; GFX9-SDAG-NEXT: ; use v[0:1]
-; GFX9-SDAG-NEXT: ;;#ASMEND
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: undef_hi3_v4f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, s4, 16, v0
-; GFX9-GISEL-NEXT: ;;#ASMSTART
-; GFX9-GISEL-NEXT: ; use v[0:1]
-; GFX9-GISEL-NEXT: ;;#ASMEND
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-SDAG-LABEL: undef_hi3_v4f16:
-; GFX11-FAKE16-SDAG: ; %bb.0:
-; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-SDAG-NEXT: ; use v[0:1]
-; GFX11-FAKE16-SDAG-NEXT: ;;#ASMEND
-; GFX11-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-GISEL-LABEL: undef_hi3_v4f16:
-; GFX11-FAKE16-GISEL: ; %bb.0:
-; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
-; GFX11-FAKE16-GISEL-NEXT: ; use v[0:1]
-; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
-; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: undef_hi3_v4f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use v[0:1]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: undef_hi3_v4f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-NEXT: ; use v[0:1]
-; GFX11-TRUE16-NEXT: ;;#ASMEND
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: undef_hi3_v4f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: ;;#ASMSTART
+; GFX11-NEXT: ; use v[0:1]
+; GFX11-NEXT: ;;#ASMEND
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%undef.hi = insertelement <4 x half> poison, half %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<4 x half> %undef.hi);
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/call-c-function.ll b/llvm/test/CodeGen/AMDGPU/call-c-function.ll
index 4fbc7271ba0c5..b7dd27aff2251 100644
--- a/llvm/test/CodeGen/AMDGPU/call-c-function.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-c-function.ll
@@ -15,6 +15,7 @@ define amdgpu_ps void @amdgpu_ps_call_default_cc() {
; GISEL-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GISEL-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GISEL-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GISEL-NEXT: [[DEF3:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GISEL-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
; GISEL-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]]
; GISEL-NEXT: $sgpr4_sgpr5 = COPY [[DEF]]
@@ -26,7 +27,7 @@ define amdgpu_ps void @amdgpu_ps_call_default_cc() {
; GISEL-NEXT: $sgpr13 = COPY [[DEF2]]
; GISEL-NEXT: $sgpr14 = COPY [[DEF2]]
; GISEL-NEXT: $sgpr15 = COPY [[DEF2]]
- ; GISEL-NEXT: $vgpr31 = COPY [[DEF2]]
+ ; GISEL-NEXT: $vgpr31 = COPY [[DEF3]]
; GISEL-NEXT: [[S_MOV_B1:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
; GISEL-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_MOV_B1]], 0, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
@@ -47,6 +48,7 @@ define amdgpu_gfx void @amdgpu_gfx_call_default_cc() {
; GISEL-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GISEL-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GISEL-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GISEL-NEXT: [[DEF3:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GISEL-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GISEL-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]]
; GISEL-NEXT: $sgpr4_sgpr5 = COPY [[DEF]]
@@ -58,7 +60,7 @@ define amdgpu_gfx void @amdgpu_gfx_call_default_cc() {
; GISEL-NEXT: $sgpr13 = COPY [[DEF2]]
; GISEL-NEXT: $sgpr14 = COPY [[DEF2]]
; GISEL-NEXT: $sgpr15 = COPY [[DEF2]]
- ; GISEL-NEXT: $vgpr31 = COPY [[DEF2]]
+ ; GISEL-NEXT: $vgpr31 = COPY [[DEF3]]
; GISEL-NEXT: [[S_MOV_B1:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
; GISEL-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_MOV_B1]], 0, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; GISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
diff --git a/llvm/test/CodeGen/AMDGPU/call-constant.ll b/llvm/test/CodeGen/AMDGPU/call-constant.ll
index db265a3188cdf..d09e0b1723831 100644
--- a/llvm/test/CodeGen/AMDGPU/call-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-constant.ll
@@ -1,16 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GISEL %s
define amdgpu_kernel void @test_call_undef() #0 {
-; GCN-LABEL: test_call_undef:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_add_i32 s12, s12, s17
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: test_call_undef:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_call_undef:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; GISEL-NEXT: v_mov_b32_e32 v0, 1
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
+; GISEL-NEXT: s_endpgm
%val = call i32 undef(i32 1)
%op = add i32 %val, 1
store volatile i32 %op, ptr addrspace(1) poison
@@ -51,16 +70,35 @@ define i32 @test_tail_call_undef() #0 {
}
define amdgpu_kernel void @test_call_null() #0 {
-; GCN-LABEL: test_call_null:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_add_i32 s12, s12, s17
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: test_call_null:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: v_mov_b32_e32 v0, 0
+; SDAG-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_call_null:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; GISEL-NEXT: v_mov_b32_e32 v0, 1
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_swappc_b64 s[30:31], 0
+; GISEL-NEXT: s_endpgm
%val = call i32 null(i32 1)
%op = add i32 %val, 1
store volatile i32 %op, ptr addrspace(1) null
@@ -99,3 +137,5 @@ define i32 @test_tail_call_null() #0 {
%call = tail call i32 null(i32 1)
ret i32 %call
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GCN: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll
index 90561c74a225e..2799efe3f16d2 100644
--- a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll
@@ -1,31 +1,55 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GISEL %s
define amdgpu_kernel void @test_bitcast_return_type_noinline() #0 {
-; GCN-LABEL: test_bitcast_return_type_noinline:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_add_i32 s12, s12, s17
-; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GCN-NEXT: s_add_u32 s0, s0, s17
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_mov_b32 s12, s14
-; GCN-NEXT: s_getpc_b64 s[18:19]
-; GCN-NEXT: s_add_u32 s18, s18, ret_i32_noinline at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s19, s19, ret_i32_noinline at rel32@hi+12
-; GCN-NEXT: v_or_b32_e32 v31, v0, v2
-; GCN-NEXT: s_mov_b32 s14, s16
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: test_bitcast_return_type_noinline:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ret_i32_noinline at rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ret_i32_noinline at rel32@hi+12
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_bitcast_return_type_noinline:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ret_i32_noinline at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ret_i32_noinline at rel32@hi+12
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = call float @ret_i32_noinline()
%op = fadd float %val, 1.0
store volatile float %op, ptr addrspace(1) poison
@@ -33,29 +57,53 @@ define amdgpu_kernel void @test_bitcast_return_type_noinline() #0 {
}
define amdgpu_kernel void @test_bitcast_return_type_alwaysinline() #0 {
-; GCN-LABEL: test_bitcast_return_type_alwaysinline:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_add_i32 s12, s12, s17
-; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GCN-NEXT: s_add_u32 s0, s0, s17
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_mov_b32 s12, s14
-; GCN-NEXT: s_getpc_b64 s[18:19]
-; GCN-NEXT: s_add_u32 s18, s18, ret_i32_alwaysinline at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s19, s19, ret_i32_alwaysinline at rel32@hi+12
-; GCN-NEXT: v_or_b32_e32 v31, v0, v2
-; GCN-NEXT: s_mov_b32 s14, s16
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: test_bitcast_return_type_alwaysinline:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ret_i32_alwaysinline at rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ret_i32_alwaysinline at rel32@hi+12
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_bitcast_return_type_alwaysinline:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ret_i32_alwaysinline at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ret_i32_alwaysinline at rel32@hi+12
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = call float @ret_i32_alwaysinline()
%op = fadd float %val, 1.0
store volatile float %op, ptr addrspace(1) poison
@@ -63,30 +111,55 @@ define amdgpu_kernel void @test_bitcast_return_type_alwaysinline() #0 {
}
define amdgpu_kernel void @test_bitcast_argument_type() #0 {
-; GCN-LABEL: test_bitcast_argument_type:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_add_i32 s12, s12, s17
-; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GCN-NEXT: s_add_u32 s0, s0, s17
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_mov_b32 s12, s14
-; GCN-NEXT: s_getpc_b64 s[18:19]
-; GCN-NEXT: s_add_u32 s18, s18, ident_i32 at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s19, s19, ident_i32 at rel32@hi+12
-; GCN-NEXT: v_or_b32_e32 v31, v0, v2
-; GCN-NEXT: s_mov_b32 s14, s16
-; GCN-NEXT: v_mov_b32_e32 v0, 2.0
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v0
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: test_bitcast_argument_type:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ident_i32 at rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ident_i32 at rel32@hi+12
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: v_mov_b32_e32 v0, 2.0
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_i32_e32 v0, vcc, 1, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_bitcast_argument_type:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ident_i32 at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ident_i32 at rel32@hi+12
+; GISEL-NEXT: v_mov_b32_e32 v0, 2.0
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, 1, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = call i32 @ident_i32(float 2.0)
%op = add i32 %val, 1
store volatile i32 %op, ptr addrspace(1) poison
@@ -94,30 +167,55 @@ define amdgpu_kernel void @test_bitcast_argument_type() #0 {
}
define amdgpu_kernel void @test_bitcast_argument_and_return_types() #0 {
-; GCN-LABEL: test_bitcast_argument_and_return_types:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_add_i32 s12, s12, s17
-; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GCN-NEXT: s_add_u32 s0, s0, s17
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_mov_b32 s12, s14
-; GCN-NEXT: s_getpc_b64 s[18:19]
-; GCN-NEXT: s_add_u32 s18, s18, ident_i32 at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s19, s19, ident_i32 at rel32@hi+12
-; GCN-NEXT: v_or_b32_e32 v31, v0, v2
-; GCN-NEXT: s_mov_b32 s14, s16
-; GCN-NEXT: v_mov_b32_e32 v0, 2.0
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: test_bitcast_argument_and_return_types:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ident_i32 at rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ident_i32 at rel32@hi+12
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: v_mov_b32_e32 v0, 2.0
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_bitcast_argument_and_return_types:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ident_i32 at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ident_i32 at rel32@hi+12
+; GISEL-NEXT: v_mov_b32_e32 v0, 2.0
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = call float @ident_i32(float 2.0)
%op = fadd float %val, 1.0
store volatile float %op, ptr addrspace(1) poison
@@ -189,31 +287,57 @@ define amdgpu_kernel void @test_bitcast_use_workitem_id_x() #3 {
@_ZTIi = external global ptr
declare i32 @__gxx_personality_v0(...)
define amdgpu_kernel void @test_invoke() #0 personality ptr @__gxx_personality_v0 {
-; GCN-LABEL: test_invoke:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_add_i32 s12, s12, s17
-; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GCN-NEXT: s_add_u32 s0, s0, s17
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_mov_b32 s12, s14
-; GCN-NEXT: s_getpc_b64 s[18:19]
-; GCN-NEXT: s_add_u32 s18, s18, ident_i32 at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s19, s19, ident_i32 at rel32@hi+12
-; GCN-NEXT: v_or_b32_e32 v31, v0, v2
-; GCN-NEXT: s_mov_b32 s14, s16
-; GCN-NEXT: v_mov_b32_e32 v0, 2.0
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: ; implicit-def: $sgpr15
-; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: test_invoke:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ident_i32 at rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ident_i32 at rel32@hi+12
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: v_mov_b32_e32 v0, 2.0
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: ; implicit-def: $sgpr15
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_invoke:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ident_i32 at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ident_i32 at rel32@hi+12
+; GISEL-NEXT: v_mov_b32_e32 v0, 2.0
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: ; implicit-def: $sgpr15
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = invoke float @ident_i32(float 2.0)
to label %continue unwind label %broken
diff --git a/llvm/test/CodeGen/AMDGPU/call-encoding.ll b/llvm/test/CodeGen/AMDGPU/call-encoding.ll
index 7decfce40bdbc..6c36c2424a66e 100644
--- a/llvm/test/CodeGen/AMDGPU/call-encoding.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-encoding.ll
@@ -1,7 +1,7 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=fiji -d - | FileCheck --check-prefix=GCN %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx900 -d - | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=fiji -d - | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx900 -d - | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=fiji -d - | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx900 -d - | FileCheck --check-prefix=GCN %s
; XUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=hawaii -d - | FileCheck --check-prefixes=GCN,CI %s
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
index 2c2c5165c6803..0e579531e829b 100644
--- a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
@@ -3,10 +3,10 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 < %s | FileCheck -check-prefixes=GCN,MUBUF,SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-ipra=0 < %s | FileCheck -check-prefixes=GCN,MUBUF,SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-ipra=0 -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=GCN,FLATSCR,SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-ipra=0 < %s | FileCheck -check-prefixes=GCN,MUBUF,GISEL %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 < %s | FileCheck -check-prefixes=GCN,MUBUF,GISEL %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-ipra=0 < %s | FileCheck -check-prefixes=GCN,MUBUF,GISEL %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-ipra=0 -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=GCN,FLATSCR,GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-ipra=0 < %s | FileCheck -check-prefixes=GCN,MUBUF,GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 < %s | FileCheck -check-prefixes=GCN,MUBUF,GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-ipra=0 < %s | FileCheck -check-prefixes=GCN,MUBUF,GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-ipra=0 -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=GCN,FLATSCR,GISEL %s
declare hidden void @external_void_func_void() #3
@@ -227,41 +227,6 @@ define hidden void @void_func_void_clobber_vcc() #2 {
}
define amdgpu_kernel void @test_call_void_func_void_clobber_vcc(ptr addrspace(1) %out) #0 {
-; FLATSCR-LABEL: test_call_void_func_void_clobber_vcc:
-; FLATSCR: ; %bb.0:
-; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13
-; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0
-; FLATSCR-NEXT: s_add_u32 s8, s4, 8
-; FLATSCR-NEXT: s_addc_u32 s9, s5, 0
-; FLATSCR-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; FLATSCR-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; FLATSCR-NEXT: s_mov_b32 s14, s12
-; FLATSCR-NEXT: s_mov_b32 s13, s11
-; FLATSCR-NEXT: s_mov_b32 s12, s10
-; FLATSCR-NEXT: s_mov_b64 s[10:11], s[6:7]
-; FLATSCR-NEXT: s_getpc_b64 s[16:17]
-; FLATSCR-NEXT: s_add_u32 s16, s16, void_func_void_clobber_vcc at rel32@lo+4
-; FLATSCR-NEXT: s_addc_u32 s17, s17, void_func_void_clobber_vcc at rel32@hi+12
-; FLATSCR-NEXT: v_or3_b32 v31, v0, v1, v2
-; FLATSCR-NEXT: s_mov_b64 s[4:5], s[0:1]
-; FLATSCR-NEXT: s_mov_b64 s[6:7], s[2:3]
-; FLATSCR-NEXT: s_mov_b32 s32, 0
-; FLATSCR-NEXT: ;;#ASMSTART
-; FLATSCR-NEXT: ; def vcc
-; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: s_mov_b64 s[34:35], vcc
-; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; FLATSCR-NEXT: global_load_dword v0, v[0:1], off glc
-; FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; FLATSCR-NEXT: s_mov_b64 vcc, s[34:35]
-; FLATSCR-NEXT: global_load_dword v0, v[0:1], off glc
-; FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; FLATSCR-NEXT: ; kill: killed $vgpr0_vgpr1
-; FLATSCR-NEXT: ; kill: killed $vgpr0_vgpr1
-; FLATSCR-NEXT: ;;#ASMSTART
-; FLATSCR-NEXT: ; use vcc
-; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: s_endpgm
%vcc = call i64 asm sideeffect "; def $0", "={vcc}"()
call void @void_func_void_clobber_vcc()
%val0 = load volatile i32, ptr addrspace(1) poison
@@ -467,51 +432,11 @@ define hidden void @void_func_void_clobber_s34() #2 {
}
define amdgpu_kernel void @test_call_void_func_void_clobber_s33() #0 {
-; FLATSCR-LABEL: test_call_void_func_void_clobber_s33:
-; FLATSCR: ; %bb.0:
-; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13
-; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0
-; FLATSCR-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; FLATSCR-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; FLATSCR-NEXT: s_mov_b32 s14, s12
-; FLATSCR-NEXT: s_mov_b32 s13, s11
-; FLATSCR-NEXT: s_mov_b32 s12, s10
-; FLATSCR-NEXT: s_mov_b64 s[10:11], s[6:7]
-; FLATSCR-NEXT: s_mov_b64 s[8:9], s[4:5]
-; FLATSCR-NEXT: s_getpc_b64 s[16:17]
-; FLATSCR-NEXT: s_add_u32 s16, s16, void_func_void_clobber_s33 at rel32@lo+4
-; FLATSCR-NEXT: s_addc_u32 s17, s17, void_func_void_clobber_s33 at rel32@hi+12
-; FLATSCR-NEXT: v_or3_b32 v31, v0, v1, v2
-; FLATSCR-NEXT: s_mov_b64 s[4:5], s[0:1]
-; FLATSCR-NEXT: s_mov_b64 s[6:7], s[2:3]
-; FLATSCR-NEXT: s_mov_b32 s32, 0
-; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; FLATSCR-NEXT: s_endpgm
call void @void_func_void_clobber_s33()
ret void
}
define amdgpu_kernel void @test_call_void_func_void_clobber_s34() #0 {
-; FLATSCR-LABEL: test_call_void_func_void_clobber_s34:
-; FLATSCR: ; %bb.0:
-; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13
-; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0
-; FLATSCR-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; FLATSCR-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; FLATSCR-NEXT: s_mov_b32 s14, s12
-; FLATSCR-NEXT: s_mov_b32 s13, s11
-; FLATSCR-NEXT: s_mov_b32 s12, s10
-; FLATSCR-NEXT: s_mov_b64 s[10:11], s[6:7]
-; FLATSCR-NEXT: s_mov_b64 s[8:9], s[4:5]
-; FLATSCR-NEXT: s_getpc_b64 s[16:17]
-; FLATSCR-NEXT: s_add_u32 s16, s16, void_func_void_clobber_s34 at rel32@lo+4
-; FLATSCR-NEXT: s_addc_u32 s17, s17, void_func_void_clobber_s34 at rel32@hi+12
-; FLATSCR-NEXT: v_or3_b32 v31, v0, v1, v2
-; FLATSCR-NEXT: s_mov_b64 s[4:5], s[0:1]
-; FLATSCR-NEXT: s_mov_b64 s[6:7], s[2:3]
-; FLATSCR-NEXT: s_mov_b32 s32, 0
-; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; FLATSCR-NEXT: s_endpgm
call void @void_func_void_clobber_s34()
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll b/llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
index 2090a36681eae..d0f99bd8f5396 100644
--- a/llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s -check-prefix=GISEL
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s -check-prefix=GISEL
; Check for optimizing the passed implicit workitem ID based on the
; required group size. This should avoid a few bit packing operations.
@@ -30,10 +30,10 @@ define amdgpu_kernel void @known_x_0(ptr addrspace(1) %out) "amdgpu-flat-work-gr
; GISEL-NEXT: s_add_u32 s0, s0, s17
; GISEL-NEXT: s_addc_u32 s1, s1, 0
; GISEL-NEXT: v_lshlrev_b32_e32 v0, 20, v2
+; GISEL-NEXT: v_lshl_or_b32 v31, v1, 10, v0
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, callee at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, callee at rel32@hi+12
-; GISEL-NEXT: v_lshl_or_b32 v31, v1, 10, v0
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GISEL-NEXT: s_endpgm
@@ -63,10 +63,10 @@ define amdgpu_kernel void @known_y_0(ptr addrspace(1) %out) "amdgpu-flat-work-gr
; GISEL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GISEL-NEXT: s_add_u32 s0, s0, s17
; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_lshl_or_b32 v31, v2, 20, v0
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, callee at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, callee at rel32@hi+12
-; GISEL-NEXT: v_lshl_or_b32 v31, v2, 20, v0
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GISEL-NEXT: s_endpgm
@@ -96,10 +96,10 @@ define amdgpu_kernel void @known_z_0(ptr addrspace(1) %out) "amdgpu-flat-work-gr
; GISEL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GISEL-NEXT: s_add_u32 s0, s0, s17
; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_lshl_or_b32 v31, v1, 10, v0
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, callee at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, callee at rel32@hi+12
-; GISEL-NEXT: v_lshl_or_b32 v31, v1, 10, v0
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GISEL-NEXT: s_endpgm
@@ -162,10 +162,10 @@ define amdgpu_kernel void @known_xz_0(ptr addrspace(1) %out) "amdgpu-flat-work-g
; GISEL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GISEL-NEXT: s_add_u32 s0, s0, s17
; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_lshlrev_b32_e32 v31, 10, v1
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, callee at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, callee at rel32@hi+12
-; GISEL-NEXT: v_lshlrev_b32_e32 v31, 10, v1
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/call-skip.ll b/llvm/test/CodeGen/AMDGPU/call-skip.ll
index 0cc00a807f008..a4a247572c494 100644
--- a/llvm/test/CodeGen/AMDGPU/call-skip.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-skip.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel=0 -mcpu=hawaii < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel=1 -global-isel-abort=2 -mcpu=hawaii < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel=1 -mcpu=hawaii < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GISEL %s
; A call should be skipped if all lanes are zero, since we don't know
; what side effects should be avoided inside the call.
@@ -80,32 +80,59 @@ end:
}
define amdgpu_kernel void @if_call_kernel() #0 {
-; GCN-LABEL: if_call_kernel:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_add_i32 s12, s12, s17
-; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GCN-NEXT: s_add_u32 s0, s0, s17
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-NEXT: s_and_saveexec_b64 s[18:19], vcc
-; GCN-NEXT: s_cbranch_execz .LBB3_2
-; GCN-NEXT: ; %bb.1: ; %call
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_getpc_b64 s[18:19]
-; GCN-NEXT: s_add_u32 s18, s18, func at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s19, s19, func at rel32@hi+12
-; GCN-NEXT: v_or_b32_e32 v31, v0, v2
-; GCN-NEXT: s_mov_b32 s12, s14
-; GCN-NEXT: s_mov_b32 s14, s16
-; GCN-NEXT: ; implicit-def: $sgpr15
-; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GCN-NEXT: .LBB3_2: ; %end
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: if_call_kernel:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_and_saveexec_b64 s[18:19], vcc
+; SDAG-NEXT: s_cbranch_execz .LBB3_2
+; SDAG-NEXT: ; %bb.1: ; %call
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, func at rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, func at rel32@hi+12
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: ; implicit-def: $sgpr15
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: .LBB3_2: ; %end
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: if_call_kernel:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_and_saveexec_b64 s[18:19], vcc
+; GISEL-NEXT: s_cbranch_execz .LBB3_2
+; GISEL-NEXT: ; %bb.1: ; %call
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, func at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, func at rel32@hi+12
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: ; implicit-def: $sgpr15
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: .LBB3_2: ; %end
+; GISEL-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x()
%cc = icmp eq i32 %id, 0
br i1 %cc, label %call, label %end
@@ -123,6 +150,3 @@ declare i32 @llvm.amdgcn.workitem.id.x() #2
attributes #0 = { nounwind }
attributes #1 = { nounwind noinline }
attributes #2 = { nounwind readnone speculatable }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL: {{.*}}
-; SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll b/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
index 8187de3f21544..369e3e796b273 100644
--- a/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
+++ b/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=SDAG %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GISEL %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GISEL %s
define amdgpu_vs void @fcmp_f32_olt_to_ogt(ptr addrspace(1) inreg %out, float inreg %a) {
; SDAG-LABEL: fcmp_f32_olt_to_ogt:
@@ -223,11 +223,10 @@ define amdgpu_vs void @fcmp_f16_olt_to_ogt(ptr addrspace(1) inreg %out, half inr
; GISEL-LABEL: fcmp_f16_olt_to_ogt:
; GISEL: ; %bb.0: ; %entry
; GISEL-NEXT: s_cmp_gt_f16 s2, 0x4000
-; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-NEXT: s_endpgm
entry:
%0 = fcmp olt half 2.0, %a
@@ -249,11 +248,10 @@ define amdgpu_vs void @fcmp_f16_ogt_to_olt(ptr addrspace(1) inreg %out, half inr
; GISEL-LABEL: fcmp_f16_ogt_to_olt:
; GISEL: ; %bb.0: ; %entry
; GISEL-NEXT: s_cmp_lt_f16 s2, 0x4000
-; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-NEXT: s_endpgm
entry:
%0 = fcmp ogt half 2.0, %a
@@ -275,11 +273,10 @@ define amdgpu_vs void @fcmp_f16_ole_to_oge(ptr addrspace(1) inreg %out, half inr
; GISEL-LABEL: fcmp_f16_ole_to_oge:
; GISEL: ; %bb.0: ; %entry
; GISEL-NEXT: s_cmp_ge_f16 s2, 0x4000
-; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-NEXT: s_endpgm
entry:
%0 = fcmp ole half 2.0, %a
@@ -301,11 +298,10 @@ define amdgpu_vs void @fcmp_f16_oge_to_ole(ptr addrspace(1) inreg %out, half inr
; GISEL-LABEL: fcmp_f16_oge_to_ole:
; GISEL: ; %bb.0: ; %entry
; GISEL-NEXT: s_cmp_le_f16 s2, 0x4000
-; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-NEXT: s_endpgm
entry:
%0 = fcmp oge half 2.0, %a
@@ -327,11 +323,10 @@ define amdgpu_vs void @fcmp_f16_ult_to_ugt(ptr addrspace(1) inreg %out, half inr
; GISEL-LABEL: fcmp_f16_ult_to_ugt:
; GISEL: ; %bb.0: ; %entry
; GISEL-NEXT: s_cmp_nle_f16 s2, 0x4000
-; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-NEXT: s_endpgm
entry:
%0 = fcmp ult half 2.0, %a
@@ -353,11 +348,10 @@ define amdgpu_vs void @fcmp_f16_ugt_to_ult(ptr addrspace(1) inreg %out, half inr
; GISEL-LABEL: fcmp_f16_ugt_to_ult:
; GISEL: ; %bb.0: ; %entry
; GISEL-NEXT: s_cmp_nge_f16 s2, 0x4000
-; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-NEXT: s_endpgm
entry:
%0 = fcmp ugt half 2.0, %a
@@ -379,11 +373,10 @@ define amdgpu_vs void @fcmp_ule_to_uge(ptr addrspace(1) inreg %out, half inreg %
; GISEL-LABEL: fcmp_ule_to_uge:
; GISEL: ; %bb.0: ; %entry
; GISEL-NEXT: s_cmp_nlt_f16 s2, 0x4000
-; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-NEXT: s_endpgm
entry:
%0 = fcmp ule half 2.0, %a
@@ -405,11 +398,10 @@ define amdgpu_vs void @fcmp_uge_to_ule(ptr addrspace(1) inreg %out, half inreg %
; GISEL-LABEL: fcmp_uge_to_ule:
; GISEL: ; %bb.0: ; %entry
; GISEL-NEXT: s_cmp_ngt_f16 s2, 0x4000
-; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-NEXT: s_endpgm
entry:
%0 = fcmp uge half 2.0, %a
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index 125c12f84a1c7..aac2538fd3f24 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -1996,43 +1996,24 @@ define half @fmul_select_f16_test6(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: fmul_select_f16_test6:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x4200
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xc800
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: fmul_select_f16_test6:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xc800
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x4200
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: fmul_select_f16_test6:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0xc800
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4200, v3, vcc_lo
-; GFX10-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: fmul_select_f16_test6:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x4200
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xc800
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: fmul_select_f16_test6:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x4200
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xc800, vcc_lo
-; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: fmul_select_f16_test6:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v3, 0xc800
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x4200, v3, vcc_lo
+; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test6:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -2067,10 +2048,10 @@ define half @fmul_select_f16_test6(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test6:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x4200
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc800
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0xc800, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4200, v3, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
@@ -2106,43 +2087,24 @@ define half @fmul_select_f16_test7(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: fmul_select_f16_test7:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xc400
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x4800
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: fmul_select_f16_test7:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x4800
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xc400
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: fmul_select_f16_test7:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x4800
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xc400, v3, vcc_lo
-; GFX10-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: fmul_select_f16_test7:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xc400
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x4800
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: fmul_select_f16_test7:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0xc400
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x4800, vcc_lo
-; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: fmul_select_f16_test7:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v3, 0x4800
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0xc400, v3, vcc_lo
+; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test7:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -2177,10 +2139,10 @@ define half @fmul_select_f16_test7(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test7:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc400
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x4800
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x4800, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xc400, v3, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
@@ -2362,42 +2324,26 @@ define half @fmul_select_f16_test10_sel_log2val_neg11_pos11(half %x, i32 %bool.a
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX9-SDAG-NEXT: v_med3_i32 v1, v1, s4, v2
-; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc
-; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo
-; GFX10-SDAG-NEXT: v_med3_i32 v1, v1, s4, 0x7fff
-; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc
+; GFX9-NEXT: s_movk_i32 s4, 0x8000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX9-NEXT: v_med3_i32 v1, v1, s4, v2
+; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-NEXT: s_movk_i32 s4, 0x8000
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo
+; GFX10-NEXT: v_med3_i32 v1, v1, s4, 0x7fff
+; GFX10-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -2434,8 +2380,10 @@ define half @fmul_select_f16_test10_sel_log2val_neg11_pos11(half %x, i32 %bool.a
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_movk_i32 s0, 0x8000
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
@@ -2455,42 +2403,26 @@ define half @fmul_select_f16_test11_sel_log2val_pos7_neg14(half %x, i32 %bool.ar
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX9-SDAG-NEXT: v_med3_i32 v1, v1, s4, v2
-; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc
-; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo
-; GFX10-SDAG-NEXT: v_med3_i32 v1, v1, s4, 0x7fff
-; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc
+; GFX9-NEXT: s_movk_i32 s4, 0x8000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX9-NEXT: v_med3_i32 v1, v1, s4, v2
+; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-NEXT: s_movk_i32 s4, 0x8000
+; GFX10-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo
+; GFX10-NEXT: v_med3_i32 v1, v1, s4, 0x7fff
+; GFX10-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -2527,8 +2459,10 @@ define half @fmul_select_f16_test11_sel_log2val_pos7_neg14(half %x, i32 %bool.ar
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_movk_i32 s0, 0x8000
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
diff --git a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
index c36d203a620ca..34641c39ee128 100644
--- a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
@@ -2,7 +2,7 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-GISEL %s
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform(i32 %n) #0 {
; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform:
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
index ce49dfea9fe30..ca19f36484b5e 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
@@ -4,19 +4,19 @@
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GFX678,GFX678-SDAG,GFX8-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GFX678,GFX678-GISEL,GFX8-GISEL %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-TRUE16 %s
+; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-TRUE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-FAKE16 %s
+; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-FAKE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1251,GFX1251-TRUE16,GFX1251-SDAG-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1251,GFX1251-TRUE16,GFX1251-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1251,GFX1251-TRUE16,GFX1251-GISEL-TRUE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1251,GFX1251-FAKE16,GFX1251-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1251,GFX1251-FAKE16,GFX1251-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1251,GFX1251-FAKE16,GFX1251-GISEL-FAKE16 %s
declare float @llvm.fabs.f32(float) #0
declare float @llvm.canonicalize.f32(float) #0
diff --git a/llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll b/llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
index 00b29819df8fd..38294226076c1 100644
--- a/llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -global-isel=0 < %s | FileCheck -check-prefix=SDAG-GFX1150 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -global-isel=1 < %s | FileCheck -check-prefix=GISEL-GFX1150 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL-GFX1150 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefix=SDAG-GFX1200 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=1 < %s | FileCheck -check-prefix=GISEL-GFX1200 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL-GFX1200 %s
define amdgpu_vs void @f32_olt(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_olt:
@@ -647,11 +647,10 @@ define amdgpu_vs void @f16_olt(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_olt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_lt_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_olt:
@@ -666,11 +665,10 @@ define amdgpu_vs void @f16_olt(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_olt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_lt_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp olt half %a, %b
@@ -692,11 +690,10 @@ define amdgpu_vs void @f16_oeq(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_oeq:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_eq_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_oeq:
@@ -711,11 +708,10 @@ define amdgpu_vs void @f16_oeq(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_oeq:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_eq_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp oeq half %a, %b
@@ -737,11 +733,10 @@ define amdgpu_vs void @f16_ole(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_ole:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_le_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ole:
@@ -756,11 +751,10 @@ define amdgpu_vs void @f16_ole(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_ole:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_le_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ole half %a, %b
@@ -782,11 +776,10 @@ define amdgpu_vs void @f16_ogt(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_ogt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_gt_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ogt:
@@ -801,11 +794,10 @@ define amdgpu_vs void @f16_ogt(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_ogt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_gt_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ogt half %a, %b
@@ -827,11 +819,10 @@ define amdgpu_vs void @f16_one(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_one:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_lg_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_one:
@@ -846,11 +837,10 @@ define amdgpu_vs void @f16_one(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_one:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_lg_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp one half %a, %b
@@ -872,11 +862,10 @@ define amdgpu_vs void @f16_oge(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_oge:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_ge_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_oge:
@@ -891,11 +880,10 @@ define amdgpu_vs void @f16_oge(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_oge:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_ge_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp oge half %a, %b
@@ -917,11 +905,10 @@ define amdgpu_vs void @f16_ord(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_ord:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_o_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ord:
@@ -936,11 +923,10 @@ define amdgpu_vs void @f16_ord(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_ord:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_o_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ord half %a, %b
@@ -962,11 +948,10 @@ define amdgpu_vs void @f16_uno(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_uno:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_u_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_uno:
@@ -981,11 +966,10 @@ define amdgpu_vs void @f16_uno(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_uno:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_u_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp uno half %a, %b
@@ -1007,11 +991,10 @@ define amdgpu_vs void @f16_ult(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_ult:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nge_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ult:
@@ -1026,11 +1009,10 @@ define amdgpu_vs void @f16_ult(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_ult:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nge_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ult half %a, %b
@@ -1052,11 +1034,10 @@ define amdgpu_vs void @f16_ueq(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_ueq:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nlg_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ueq:
@@ -1071,11 +1052,10 @@ define amdgpu_vs void @f16_ueq(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_ueq:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nlg_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ueq half %a, %b
@@ -1097,11 +1077,10 @@ define amdgpu_vs void @f16_ule(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_ule:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_ngt_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ule:
@@ -1116,11 +1095,10 @@ define amdgpu_vs void @f16_ule(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_ule:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_ngt_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ule half %a, %b
@@ -1142,11 +1120,10 @@ define amdgpu_vs void @f16_ugt(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_ugt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nle_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ugt:
@@ -1161,11 +1138,10 @@ define amdgpu_vs void @f16_ugt(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_ugt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nle_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ugt half %a, %b
@@ -1187,11 +1163,10 @@ define amdgpu_vs void @f16_une(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_une:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_neq_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_une:
@@ -1206,11 +1181,10 @@ define amdgpu_vs void @f16_une(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_une:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_neq_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp une half %a, %b
@@ -1232,11 +1206,10 @@ define amdgpu_vs void @f16_uge(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1150-LABEL: f16_uge:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nlt_f16 s2, s3
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_uge:
@@ -1251,11 +1224,10 @@ define amdgpu_vs void @f16_uge(ptr addrspace(1) inreg %out, half inreg %a, half
; GISEL-GFX1200-LABEL: f16_uge:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nlt_f16 s2, s3
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GISEL-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp uge half %a, %b
diff --git a/llvm/test/CodeGen/AMDGPU/fma.f16.ll b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
index 875d9ee11e41f..43788342bdf2b 100644
--- a/llvm/test/CodeGen/AMDGPU/fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
@@ -5,11 +5,11 @@
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GFX10,GFX10-GISEL
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GFX11-SDAG-TRUE16
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GFX11-SDAG-FAKE16
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GFX11-GISEL-TRUE16
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GFX11-GISEL-TRUE16
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GFX11-GISEL-FAKE16
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GFX12-SDAG-TRUE16
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GFX12-SDAG-FAKE16
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GFX12-GISEL-TRUE16
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GFX12-GISEL-TRUE16
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GFX12-GISEL-FAKE16
declare half @llvm.fma.f16(half, half, half)
@@ -178,19 +178,12 @@ define half @test_fmac(half %x, half %y, half %z) {
; GFX10+ has v_fmaak_f16.
define half @test_fmaak(half %x, half %y, half %z) {
-; GFX9-SDAG-LABEL: test_fmaak:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x4200
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, v1, s4
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_fmaak:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x4200
-; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v1, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmaak:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x4200
+; GFX9-NEXT: v_fma_f16 v0, v0, v1, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_fmaak:
; GFX10: ; %bb.0:
@@ -267,19 +260,12 @@ define half @test_fmaak(half %x, half %y, half %z) {
; GFX10+ has v_fmamk_f16.
define half @test_fmamk(half %x, half %y, half %z) {
-; GFX9-SDAG-LABEL: test_fmamk:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x4200
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_fmamk:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x4200
-; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v1, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmamk:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x4200
+; GFX9-NEXT: v_fma_f16 v0, v0, s4, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_fmamk:
; GFX10: ; %bb.0:
@@ -356,53 +342,28 @@ define half @test_fmamk(half %x, half %y, half %z) {
; Regression test for a crash caused by D139469.
define i32 @test_D139469_f16(half %arg) {
-; GFX9-SDAG-LABEL: test_D139469_f16:
-; GFX9-SDAG: ; %bb.0: ; %bb
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x291e
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x211e
-; GFX9-SDAG-NEXT: v_mul_f16_e32 v1, 0x291e, v0
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v2
-; GFX9-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
-; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_D139469_f16:
-; GFX9-GISEL: ; %bb.0: ; %bb
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mul_f16_e32 v2, 0x291e, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x291e
-; GFX9-GISEL-NEXT: v_cmp_gt_f16_e32 vcc, 0, v2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x211e
-; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v1, v2
-; GFX9-GISEL-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
-; GFX9-GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_D139469_f16:
-; GFX10-SDAG: ; %bb.0: ; %bb
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x291e
-; GFX10-SDAG-NEXT: v_mul_f16_e32 v1, 0x291e, v0
-; GFX10-SDAG-NEXT: v_fmaak_f16 v0, s4, v0, 0x211e
-; GFX10-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
-; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-GISEL-LABEL: test_D139469_f16:
-; GFX10-GISEL: ; %bb.0: ; %bb
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e
-; GFX10-GISEL-NEXT: v_mul_f16_e32 v2, 0x291e, v0
-; GFX10-GISEL-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
-; GFX10-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2
-; GFX10-GISEL-NEXT: v_cmp_gt_f16_e64 s4, 0, v1
-; GFX10-GISEL-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_D139469_f16:
+; GFX9: ; %bb.0: ; %bb
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x291e
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x211e
+; GFX9-NEXT: v_mul_f16_e32 v1, 0x291e, v0
+; GFX9-NEXT: v_fma_f16 v0, v0, s4, v2
+; GFX9-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX9-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: test_D139469_f16:
+; GFX10: ; %bb.0: ; %bb
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_movk_i32 s4, 0x291e
+; GFX10-NEXT: v_mul_f16_e32 v1, 0x291e, v0
+; GFX10-NEXT: v_fmaak_f16 v0, s4, v0, 0x211e
+; GFX10-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX10-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_D139469_f16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %bb
@@ -447,15 +408,13 @@ define i32 @test_D139469_f16(half %arg) {
; GFX11-GISEL-FAKE16-LABEL: test_D139469_f16:
; GFX11-GISEL-FAKE16: ; %bb.0: ; %bb
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0x211e
-; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x291e, v0
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-FAKE16-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_gt_f16_e64 s0, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-GISEL-FAKE16-NEXT: s_movk_i32 s0, 0x291e
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x291e, v0
+; GFX11-GISEL-FAKE16-NEXT: v_fmaak_f16 v0, s0, v0, 0x211e
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_D139469_f16:
@@ -521,16 +480,15 @@ define i32 @test_D139469_f16(half %arg) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0x211e
-; GFX12-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x291e, v0
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-FAKE16-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
-; GFX12-GISEL-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-GISEL-FAKE16-NEXT: v_cmp_gt_f16_e64 s0, 0, v1
-; GFX12-GISEL-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
+; GFX12-GISEL-FAKE16-NEXT: s_movk_i32 s0, 0x291e
+; GFX12-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x291e, v0
; GFX12-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX12-GISEL-FAKE16-NEXT: v_fmaak_f16 v0, s0, v0, 0x211e
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v1, v0
+; GFX12-GISEL-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
+; GFX12-GISEL-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
bb:
%i = fmul contract half %arg, 0xH291E
@@ -740,3 +698,8 @@ bb:
%i5 = zext <2 x i1> %i4 to <2 x i32>
ret <2 x i32> %i5
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX10-GISEL: {{.*}}
+; GFX10-SDAG: {{.*}}
+; GFX9-GISEL: {{.*}}
+; GFX9-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll b/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
index b7edb3dc13e5d..b9ebc359b0609 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
@@ -832,45 +832,25 @@ define half @fmed3_f32_fpext_f16_unrepresentable_k0(half %arg1, half %arg2) #1 {
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_unrepresentable_k0:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-SDAG-NEXT: s_mov_b32 s4, 0x4f800000
-; GFX8-SDAG-NEXT: v_med3_f32 v0, s4, v0, v1
-; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_unrepresentable_k0:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GFX8-GISEL-NEXT: v_med3_f32 v0, v2, v0, v1
-; GFX8-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_unrepresentable_k0:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x4f800000
-; GFX9-SDAG-NEXT: v_med3_f32 v0, s4, v0, v1
-; GFX9-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: fmed3_f32_fpext_f16_unrepresentable_k0:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GFX9-GISEL-NEXT: v_med3_f32 v0, v2, v0, v1
-; GFX9-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: fmed3_f32_fpext_f16_unrepresentable_k0:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX8-NEXT: s_mov_b32 s4, 0x4f800000
+; GFX8-NEXT: v_med3_f32 v0, s4, v0, v1
+; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: fmed3_f32_fpext_f16_unrepresentable_k0:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9-NEXT: s_mov_b32 s4, 0x4f800000
+; GFX9-NEXT: v_med3_f32 v0, s4, v0, v1
+; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%arg1.ext = fpext half %arg1 to float
%arg2.ext = fpext half %arg2 to float
%med3 = call float @llvm.amdgcn.fmed3.f32(float 0x41f0000000000000, float %arg1.ext, float %arg2.ext)
@@ -899,45 +879,25 @@ define half @fmed3_f32_fpext_f16_unrepresentable_k1(half %arg0, half %arg2) #1 {
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_unrepresentable_k1:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-SDAG-NEXT: s_mov_b32 s4, 0x4f800000
-; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, s4, v1
-; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_unrepresentable_k1:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GFX8-GISEL-NEXT: v_med3_f32 v0, v0, v2, v1
-; GFX8-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_unrepresentable_k1:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x4f800000
-; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, s4, v1
-; GFX9-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: fmed3_f32_fpext_f16_unrepresentable_k1:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GFX9-GISEL-NEXT: v_med3_f32 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: fmed3_f32_fpext_f16_unrepresentable_k1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX8-NEXT: s_mov_b32 s4, 0x4f800000
+; GFX8-NEXT: v_med3_f32 v0, v0, s4, v1
+; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: fmed3_f32_fpext_f16_unrepresentable_k1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9-NEXT: s_mov_b32 s4, 0x4f800000
+; GFX9-NEXT: v_med3_f32 v0, v0, s4, v1
+; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%arg0.ext = fpext half %arg0 to float
%arg2.ext = fpext half %arg2 to float
%med3 = call float @llvm.amdgcn.fmed3.f32(float %arg0.ext, float 0x41f0000000000000, float %arg2.ext)
@@ -966,45 +926,25 @@ define half @fmed3_f32_fpext_f16_unrepresentable_k2(half %arg0, half %arg1) #1 {
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_unrepresentable_k2:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-SDAG-NEXT: s_mov_b32 s4, 0x4f800000
-; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, s4
-; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_unrepresentable_k2:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GFX8-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2
-; GFX8-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_unrepresentable_k2:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x4f800000
-; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, v1, s4
-; GFX9-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: fmed3_f32_fpext_f16_unrepresentable_k2:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GFX9-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2
-; GFX9-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: fmed3_f32_fpext_f16_unrepresentable_k2:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX8-NEXT: s_mov_b32 s4, 0x4f800000
+; GFX8-NEXT: v_med3_f32 v0, v0, v1, s4
+; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: fmed3_f32_fpext_f16_unrepresentable_k2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9-NEXT: s_mov_b32 s4, 0x4f800000
+; GFX9-NEXT: v_med3_f32 v0, v0, v1, s4
+; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%arg0.ext = fpext half %arg0 to float
%arg1.ext = fpext half %arg1 to float
%med3 = call float @llvm.amdgcn.fmed3.f32(float %arg0.ext, float %arg1.ext, float 0x41f0000000000000)
@@ -1014,3 +954,8 @@ define half @fmed3_f32_fpext_f16_unrepresentable_k2(half %arg0, half %arg1) #1 {
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX8-GISEL: {{.*}}
+; GFX8-SDAG: {{.*}}
+; GFX9-GISEL: {{.*}}
+; GFX9-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3.ll b/llvm/test/CodeGen/AMDGPU/fmed3.ll
index 1597a2b122e8b..fa289820cc291 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3.ll
@@ -8,7 +8,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -global-isel-abort=2 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -global-isel-abort=2 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
define amdgpu_kernel void @v_test_nnan_input_fmed3_r_i_i_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {
; SI-SDAG-LABEL: v_test_nnan_input_fmed3_r_i_i_f32:
@@ -9071,12 +9071,8 @@ define half @v_test_nnan_input_fmed3_r_i_i_f16_maximum_minimum(half %a) {
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_add_f16_e32 v0, 1.0, v0
-; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-GISEL-NEXT: v_max_f32_e32 v0, 2.0, v0
-; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-GISEL-NEXT: v_min_f32_e32 v0, 4.0, v0
-; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_max_f16_e32 v0, 2.0, v0
+; VI-GISEL-NEXT: v_min_f16_e32 v0, 4.0, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_test_nnan_input_fmed3_r_i_i_f16_maximum_minimum:
diff --git a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
index 1f5f0eaec2d81..7811b3b13228a 100644
--- a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
@@ -3377,29 +3377,17 @@ define half @v_mul_1_f16(half %x) {
}
define half @v_mul_2_f16(half %x) {
-; GFX9-SDAG-LABEL: v_mul_2_f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_add_f16_e32 v0, v0, v0
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_mul_2_f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, 2.0, v0
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: v_mul_2_f16:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_add_f16_e32 v0, v0, v0
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_2_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_add_f16_e32 v0, v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: v_mul_2_f16:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, 2.0, v0
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_mul_2_f16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_add_f16_e32 v0, v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_mul_2_f16:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -3422,7 +3410,7 @@ define half @v_mul_2_f16(half %x) {
; GFX11-GISEL-FAKE16-LABEL: v_mul_2_f16:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 2.0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%mul = fmul half %x, 2.0
ret half %mul
@@ -3792,19 +3780,12 @@ define half @v_mul_0x1p14_f16(half %x) {
; Check that this doesn't interfer with fma formation
define half @v_fma_mul_add_32_f16(half %x, half %y) {
-; GFX9-SDAG-LABEL: v_fma_mul_add_32_f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x5000
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_fma_mul_add_32_f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x5000
-; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fma_mul_add_32_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x5000
+; GFX9-NEXT: v_fma_f16 v0, v0, s4, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fma_mul_add_32_f16:
; GFX10: ; %bb.0:
@@ -3841,19 +3822,12 @@ define half @v_fma_mul_add_32_f16(half %x, half %y) {
}
define half @v_fma_mul_sub_32_f16(half %x, half %y) {
-; GFX9-SDAG-LABEL: v_fma_mul_sub_32_f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x5000
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, -v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_fma_mul_sub_32_f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x5000
-; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v2, -v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fma_mul_sub_32_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x5000
+; GFX9-NEXT: v_fma_f16 v0, v0, s4, -v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fma_mul_sub_32_f16:
; GFX10: ; %bb.0:
@@ -3890,19 +3864,12 @@ define half @v_fma_mul_sub_32_f16(half %x, half %y) {
}
define half @v_fma_mul_add_neg32_f16(half %x, half %y) {
-; GFX9-SDAG-LABEL: v_fma_mul_add_neg32_f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0xd000
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_fma_mul_add_neg32_f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xd000
-; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fma_mul_add_neg32_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0xd000
+; GFX9-NEXT: v_fma_f16 v0, v0, s4, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fma_mul_add_neg32_f16:
; GFX10: ; %bb.0:
@@ -3939,19 +3906,12 @@ define half @v_fma_mul_add_neg32_f16(half %x, half %y) {
}
define half @v_mul_fabs_32_f16(half %x) {
-; GFX9-SDAG-LABEL: v_mul_fabs_32_f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x5000
-; GFX9-SDAG-NEXT: v_mul_f16_e64 v0, |v0|, s4
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_mul_fabs_32_f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x5000
-; GFX9-GISEL-NEXT: v_mul_f16_e64 v0, |v0|, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_fabs_32_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x5000
+; GFX9-NEXT: v_mul_f16_e64 v0, |v0|, s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_mul_fabs_32_f16:
; GFX10: ; %bb.0:
@@ -3988,19 +3948,12 @@ define half @v_mul_fabs_32_f16(half %x) {
}
define half @v_mul_add_fma_fabs_32_f16(half %x, half %y) {
-; GFX9-SDAG-LABEL: v_mul_add_fma_fabs_32_f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x5000
-; GFX9-SDAG-NEXT: v_fma_f16 v0, |v0|, s4, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_mul_add_fma_fabs_32_f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x5000
-; GFX9-GISEL-NEXT: v_fma_f16 v0, |v0|, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_add_fma_fabs_32_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x5000
+; GFX9-NEXT: v_fma_f16 v0, |v0|, s4, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_mul_add_fma_fabs_32_f16:
; GFX10: ; %bb.0:
@@ -5975,42 +5928,24 @@ define half @v_mul_f16_select_n128_n16(i32 %arg, half %x) {
}
define half @v_contract_mul_add_f16_select_64_1(i32 %arg, half %x, half %y) {
-; GFX9-SDAG-LABEL: v_contract_mul_add_f16_select_64_1:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x3c00
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x5400
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_64_1:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc
-; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_64_1:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x5400
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo
-; GFX10-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_contract_mul_add_f16_select_64_1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x5400
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_64_1:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_contract_mul_add_f16_select_64_1:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v3, 0x5400
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo
+; GFX10-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_64_1:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -6042,10 +5977,10 @@ define half @v_contract_mul_add_f16_select_64_1(i32 %arg, half %x, half %y) {
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_64_1:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x5400
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_fma_f16 v0, v1, v0, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
%select.pow2 = select contract i1 %cond, half 64.0, half 1.0
@@ -6055,42 +5990,24 @@ define half @v_contract_mul_add_f16_select_64_1(i32 %arg, half %x, half %y) {
}
define half @v_contract_mul_add_f16_select_1_64(i32 %arg, half %x, half %y) {
-; GFX9-SDAG-LABEL: v_contract_mul_add_f16_select_1_64:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x5400
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x3c00
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_1_64:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc
-; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_1_64:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x3c00
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
-; GFX10-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_contract_mul_add_f16_select_1_64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x5400
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x3c00
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_1_64:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_contract_mul_add_f16_select_1_64:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
+; GFX10-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_1_64:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -6122,10 +6039,10 @@ define half @v_contract_mul_add_f16_select_1_64(i32 %arg, half %x, half %y) {
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_1_64:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x3c00
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_fma_f16 v0, v1, v0, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
%select.pow2 = select contract i1 %cond, half 1.0, half 64.0
@@ -6135,42 +6052,24 @@ define half @v_contract_mul_add_f16_select_1_64(i32 %arg, half %x, half %y) {
}
define half @v_contract_mul_add_f16_select_n64_n1(i32 %arg, half %x, half %y) {
-; GFX9-SDAG-LABEL: v_contract_mul_add_f16_select_n64_n1:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xbc00
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xd400
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_n64_n1:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc
-; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0
-; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_n64_n1:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0xd400
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo
-; GFX10-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_contract_mul_add_f16_select_n64_n1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xbc00
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xd400
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_n64_n1:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0
-; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_contract_mul_add_f16_select_n64_n1:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v3, 0xd400
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo
+; GFX10-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_n64_n1:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -6202,10 +6101,10 @@ define half @v_contract_mul_add_f16_select_n64_n1(i32 %arg, half %x, half %y) {
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_n64_n1:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0xd400
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, -v1, v0
-; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_fma_f16 v0, v1, v0, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
%select.pow2 = select contract i1 %cond, half -64.0, half -1.0
@@ -6215,42 +6114,24 @@ define half @v_contract_mul_add_f16_select_n64_n1(i32 %arg, half %x, half %y) {
}
define half @v_contract_mul_add_f16_select_n1_n64(i32 %arg, half %x, half %y) {
-; GFX9-SDAG-LABEL: v_contract_mul_add_f16_select_n1_n64:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xd400
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xbc00
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_n1_n64:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc
-; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0
-; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_n1_n64:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0xbc00
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
-; GFX10-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_contract_mul_add_f16_select_n1_n64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xd400
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xbc00
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_n1_n64:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0
-; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_contract_mul_add_f16_select_n1_n64:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v3, 0xbc00
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
+; GFX10-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_n1_n64:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -6282,10 +6163,10 @@ define half @v_contract_mul_add_f16_select_n1_n64(i32 %arg, half %x, half %y) {
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_n1_n64:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0xbc00
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, -v1, v0
-; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_fma_f16 v0, v1, v0, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
%select.pow2 = select contract i1 %cond, half -1.0, half -64.0
@@ -6357,42 +6238,24 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) {
}
define half @v_contract_mul_add_f16_select_128_4(i32 %arg, half %x, half %y) {
-; GFX9-SDAG-LABEL: v_contract_mul_add_f16_select_128_4:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x4400
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x5800
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_128_4:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc
-; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_128_4:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x5800
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
-; GFX10-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_contract_mul_add_f16_select_128_4:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x4400
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x5800
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_128_4:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_contract_mul_add_f16_select_128_4:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v3, 0x5800
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
+; GFX10-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_128_4:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -6424,10 +6287,10 @@ define half @v_contract_mul_add_f16_select_128_4(i32 %arg, half %x, half %y) {
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_128_4:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x5800
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_fma_f16 v0, v1, v0, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
%select.pow2 = select i1 %cond, half 128.0, half 4.0
@@ -6499,42 +6362,24 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) {
}
define half @v_contract_mul_add_f16_select_4_128(i32 %arg, half %x, half %y) {
-; GFX9-SDAG-LABEL: v_contract_mul_add_f16_select_4_128:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x5800
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x4400
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_4_128:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc
-; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_4_128:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x4400
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x5800, v3, vcc_lo
-; GFX10-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_contract_mul_add_f16_select_4_128:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x5800
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x4400
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_4_128:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_contract_mul_add_f16_select_4_128:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v3, 0x4400
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x5800, v3, vcc_lo
+; GFX10-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_4_128:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -6566,10 +6411,10 @@ define half @v_contract_mul_add_f16_select_4_128(i32 %arg, half %x, half %y) {
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_4_128:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x4400
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x5800, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_fma_f16 v0, v1, v0, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
%select.pow2 = select i1 %cond, half 4.0, half 128.0
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
index d99c776aa4897..d1f334c52f7ae 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
@@ -2055,36 +2055,21 @@ define i64 @test_s_signed_i64_f16(half inreg %f) nounwind {
; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-ISEL-LABEL: test_s_signed_i64_f16:
-; GFX12-ISEL: ; %bb.0:
-; GFX12-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-ISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-ISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-ISEL-NEXT: s_cvt_f32_f16 s0, s0
-; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s0, s0
-; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_ashr_i32 s1, s0, 31
-; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GI-LABEL: test_s_signed_i64_f16:
-; GFX12-GI: ; %bb.0:
-; GFX12-GI-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GI-NEXT: s_wait_expcnt 0x0
-; GFX12-GI-NEXT: s_wait_samplecnt 0x0
-; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: s_cvt_f32_f16 s0, s0
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: s_cvt_i32_f32 s0, s0
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: test_s_signed_i64_f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_cvt_f32_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_cvt_i32_f32 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_ashr_i32 s1, s0, 31
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
ret i64 %x
}
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index 504ba59733cbe..79ff5f47a60de 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2385,17 +2385,14 @@ define <4 x i1> @test_signed_v4f16_v4i1(<4 x half> %f) {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
-; GFX12-GI-NEXT: v_med3_i16 v1.l, v1.l, -1, 0
-; GFX12-GI-NEXT: v_med3_i16 v2.l, v0.h, -1, 0
; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
+; GFX12-GI-NEXT: v_med3_i16 v1.l, v0.h, -1, 0
+; GFX12-GI-NEXT: v_med3_i16 v2.l, v2.l, -1, 0
; GFX12-GI-NEXT: v_med3_i16 v3.l, v1.h, -1, 0
-; GFX12-GI-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-GI-NEXT: v_mov_b32_e32 v2, v4
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i1> @llvm.fptosi.sat.v4f16.v4i1(<4 x half> %f)
ret <4 x i1> %x
@@ -2599,19 +2596,15 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_mov_b16_e32 v2.l, 0xff80
+; GFX12-GI-NEXT: v_mov_b16_e32 v2.h, 0xff80
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
-; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, v2.l, 0x7f
-; GFX12-GI-NEXT: v_med3_i16 v3.l, v0.h, v2.l, 0x7f
-; GFX12-GI-NEXT: v_med3_i16 v1.l, v1.l, v2.l, 0x7f
-; GFX12-GI-NEXT: v_med3_i16 v2.l, v1.h, v2.l, 0x7f
-; GFX12-GI-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-GI-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GFX12-GI-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-GI-NEXT: v_mov_b32_e32 v3, v5
+; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, v2.h, 0x7f
+; GFX12-GI-NEXT: v_med3_i16 v1.l, v0.h, v2.h, 0x7f
+; GFX12-GI-NEXT: v_med3_i16 v2.l, v2.l, v2.h, 0x7f
+; GFX12-GI-NEXT: v_med3_i16 v3.l, v1.h, v2.h, 0x7f
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i8> @llvm.fptosi.sat.v4f16.v4i8(<4 x half> %f)
ret <4 x i8> %x
@@ -3938,28 +3931,22 @@ define <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v4.l, v1.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX12-GI-NEXT: v_med3_i16 v4.l, v0.h, -1, 0
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v3.h, v3.h
+; GFX12-GI-NEXT: v_med3_i16 v1.l, v0.h, -1, 0
+; GFX12-GI-NEXT: v_med3_i16 v8.l, v4.l, -1, 0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v2.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, v2.h
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.h, v3.l
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v3.l, v3.h
-; GFX12-GI-NEXT: v_med3_i16 v1.l, v1.l, -1, 0
-; GFX12-GI-NEXT: v_med3_i16 v5.l, v1.h, -1, 0
-; GFX12-GI-NEXT: v_med3_i16 v2.l, v2.l, -1, 0
-; GFX12-GI-NEXT: v_med3_i16 v6.l, v0.h, -1, 0
-; GFX12-GI-NEXT: v_med3_i16 v3.l, v3.l, -1, 0
-; GFX12-GI-NEXT: v_med3_i16 v7.l, v2.h, -1, 0
-; GFX12-GI-NEXT: v_mov_b16_e32 v8.l, v1.l
-; GFX12-GI-NEXT: v_mov_b16_e32 v9.l, v2.l
; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
-; GFX12-GI-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-GI-NEXT: v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v2, v8
-; GFX12-GI-NEXT: v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
-; GFX12-GI-NEXT: v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v6, v7
-; GFX12-GI-NEXT: v_mov_b32_e32 v7, v10
+; GFX12-GI-NEXT: v_med3_i16 v3.l, v1.h, -1, 0
+; GFX12-GI-NEXT: v_med3_i16 v4.l, v0.h, -1, 0
+; GFX12-GI-NEXT: v_med3_i16 v5.l, v2.l, -1, 0
+; GFX12-GI-NEXT: v_med3_i16 v6.l, v2.h, -1, 0
+; GFX12-GI-NEXT: v_med3_i16 v7.l, v3.h, -1, 0
+; GFX12-GI-NEXT: v_mov_b32_e32 v2, v8
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i1> @llvm.fptosi.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x
@@ -4307,30 +4294,24 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_mov_b16_e32 v4.l, 0xff80
+; GFX12-GI-NEXT: v_mov_b16_e32 v4.h, 0xff80
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v4.l, v1.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX12-GI-NEXT: v_med3_i16 v5.l, v0.h, v4.l, 0x7f
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v3.h, v3.h
+; GFX12-GI-NEXT: v_med3_i16 v1.l, v0.h, v4.h, 0x7f
+; GFX12-GI-NEXT: v_med3_i16 v8.l, v4.l, v4.h, 0x7f
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v1.h
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.h, v2.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, v2.h
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.h, v3.l
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v3.l, v3.h
-; GFX12-GI-NEXT: v_med3_i16 v1.l, v1.l, v4.l, 0x7f
-; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, v4.l, 0x7f
-; GFX12-GI-NEXT: v_med3_i16 v2.l, v2.l, v4.l, 0x7f
-; GFX12-GI-NEXT: v_med3_i16 v6.l, v0.h, v4.l, 0x7f
-; GFX12-GI-NEXT: v_med3_i16 v3.l, v3.l, v4.l, 0x7f
-; GFX12-GI-NEXT: v_med3_i16 v7.l, v1.h, v4.l, 0x7f
-; GFX12-GI-NEXT: v_med3_i16 v8.l, v2.h, v4.l, 0x7f
-; GFX12-GI-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-GI-NEXT: v_mov_b16_e32 v9.l, v2.l
-; GFX12-GI-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, v5
-; GFX12-GI-NEXT: v_dual_mov_b32 v3, v6 :: v_dual_mov_b32 v2, v4
-; GFX12-GI-NEXT: v_dual_mov_b32 v4, v7 :: v_dual_mov_b32 v5, v9
-; GFX12-GI-NEXT: v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v10
+; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, v4.h, 0x7f
+; GFX12-GI-NEXT: v_med3_i16 v3.l, v0.h, v4.h, 0x7f
+; GFX12-GI-NEXT: v_med3_i16 v4.l, v1.h, v4.h, 0x7f
+; GFX12-GI-NEXT: v_med3_i16 v5.l, v2.l, v4.h, 0x7f
+; GFX12-GI-NEXT: v_med3_i16 v6.l, v2.h, v4.h, 0x7f
+; GFX12-GI-NEXT: v_med3_i16 v7.l, v3.h, v4.h, 0x7f
+; GFX12-GI-NEXT: v_mov_b32_e32 v2, v8
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index e65f01c46f2a5..5f57ec812f98b 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -2247,17 +2247,14 @@ define <4 x i1> @test_unsigned_v4f16_v4i1(<4 x half> %f) {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, v1.l
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
-; GFX12-GI-NEXT: v_min_u16 v1.l, v1.l, 1
-; GFX12-GI-NEXT: v_min_u16 v2.l, v0.h, 1
; GFX12-GI-NEXT: v_min_u16 v0.l, v0.l, 1
+; GFX12-GI-NEXT: v_min_u16 v1.l, v0.h, 1
+; GFX12-GI-NEXT: v_min_u16 v2.l, v2.l, 1
; GFX12-GI-NEXT: v_min_u16 v3.l, v1.h, 1
-; GFX12-GI-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-GI-NEXT: v_mov_b32_e32 v2, v4
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i1> @llvm.fptoui.sat.v4f16.v4i1(<4 x half> %f)
ret <4 x i1> %x
@@ -2437,17 +2434,14 @@ define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, v1.l
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
-; GFX12-GI-NEXT: v_min_u16 v1.l, 0xff, v1.l
-; GFX12-GI-NEXT: v_min_u16 v2.l, 0xff, v0.h
; GFX12-GI-NEXT: v_min_u16 v0.l, 0xff, v0.l
+; GFX12-GI-NEXT: v_min_u16 v1.l, 0xff, v0.h
+; GFX12-GI-NEXT: v_min_u16 v2.l, 0xff, v2.l
; GFX12-GI-NEXT: v_min_u16 v3.l, 0xff, v1.h
-; GFX12-GI-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-GI-NEXT: v_mov_b32_e32 v2, v4
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i8> @llvm.fptoui.sat.v4f16.v4i8(<4 x half> %f)
ret <4 x i8> %x
@@ -3715,28 +3709,22 @@ define <8 x i1> @test_unsigned_v8f16_v8i1(<8 x half> %f) {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v4.l, v1.l
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX12-GI-NEXT: v_min_u16 v4.l, v0.h, 1
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v3.h, v3.h
+; GFX12-GI-NEXT: v_min_u16 v1.l, v0.h, 1
+; GFX12-GI-NEXT: v_min_u16 v8.l, v4.l, 1
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v2.l
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, v2.h
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.h, v3.l
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v3.l, v3.h
-; GFX12-GI-NEXT: v_min_u16 v1.l, v1.l, 1
-; GFX12-GI-NEXT: v_min_u16 v5.l, v1.h, 1
-; GFX12-GI-NEXT: v_min_u16 v2.l, v2.l, 1
-; GFX12-GI-NEXT: v_min_u16 v6.l, v0.h, 1
-; GFX12-GI-NEXT: v_min_u16 v3.l, v3.l, 1
-; GFX12-GI-NEXT: v_min_u16 v7.l, v2.h, 1
-; GFX12-GI-NEXT: v_mov_b16_e32 v8.l, v1.l
-; GFX12-GI-NEXT: v_mov_b16_e32 v9.l, v2.l
; GFX12-GI-NEXT: v_min_u16 v0.l, v0.l, 1
-; GFX12-GI-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-GI-NEXT: v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v2, v8
-; GFX12-GI-NEXT: v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
-; GFX12-GI-NEXT: v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v6, v7
-; GFX12-GI-NEXT: v_mov_b32_e32 v7, v10
+; GFX12-GI-NEXT: v_min_u16 v3.l, v1.h, 1
+; GFX12-GI-NEXT: v_min_u16 v4.l, v0.h, 1
+; GFX12-GI-NEXT: v_min_u16 v5.l, v2.l, 1
+; GFX12-GI-NEXT: v_min_u16 v6.l, v2.h, 1
+; GFX12-GI-NEXT: v_min_u16 v7.l, v3.h, 1
+; GFX12-GI-NEXT: v_mov_b32_e32 v2, v8
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i1> @llvm.fptoui.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x
@@ -4048,28 +4036,22 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v4.l, v1.l
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX12-GI-NEXT: v_min_u16 v4.l, 0xff, v0.h
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v3.h, v3.h
+; GFX12-GI-NEXT: v_min_u16 v1.l, 0xff, v0.h
+; GFX12-GI-NEXT: v_min_u16 v8.l, 0xff, v4.l
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v2.l
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, v2.h
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.h, v3.l
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v3.l, v3.h
-; GFX12-GI-NEXT: v_min_u16 v1.l, 0xff, v1.l
-; GFX12-GI-NEXT: v_min_u16 v5.l, 0xff, v1.h
-; GFX12-GI-NEXT: v_min_u16 v2.l, 0xff, v2.l
-; GFX12-GI-NEXT: v_min_u16 v6.l, 0xff, v0.h
-; GFX12-GI-NEXT: v_min_u16 v3.l, 0xff, v3.l
-; GFX12-GI-NEXT: v_min_u16 v7.l, 0xff, v2.h
-; GFX12-GI-NEXT: v_mov_b16_e32 v8.l, v1.l
-; GFX12-GI-NEXT: v_mov_b16_e32 v9.l, v2.l
; GFX12-GI-NEXT: v_min_u16 v0.l, 0xff, v0.l
-; GFX12-GI-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-GI-NEXT: v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v2, v8
-; GFX12-GI-NEXT: v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
-; GFX12-GI-NEXT: v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v6, v7
-; GFX12-GI-NEXT: v_mov_b32_e32 v7, v10
+; GFX12-GI-NEXT: v_min_u16 v3.l, 0xff, v1.h
+; GFX12-GI-NEXT: v_min_u16 v4.l, 0xff, v0.h
+; GFX12-GI-NEXT: v_min_u16 v5.l, 0xff, v2.l
+; GFX12-GI-NEXT: v_min_u16 v6.l, 0xff, v2.h
+; GFX12-GI-NEXT: v_min_u16 v7.l, 0xff, v3.h
+; GFX12-GI-NEXT: v_mov_b32_e32 v2, v8
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x
diff --git a/llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll b/llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
index 122fbc908d337..df2f914afe7bb 100644
--- a/llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
+++ b/llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=CHECK,SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=CHECK,GISEL %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=CHECK,GISEL %s
; Test that fneg is folded into source modifiers when it wasn't
; possible to fold fsub to fneg without context.
@@ -339,108 +339,66 @@ define <2 x float> @fold_v2f32_fsub_into_fneg_modifier_dynamic_nsz(<2 x float> %
define half @fold_f16_fsub_into_fneg_modifier_ieee(half %v0, half %v1) #0 {
-; SDAG-LABEL: fold_f16_fsub_into_fneg_modifier_ieee:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_mul_f16_e64 v0, -v0, v1
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: fold_f16_fsub_into_fneg_modifier_ieee:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_max_f16_e64 v0, -v0, -v0
-; GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: fold_f16_fsub_into_fneg_modifier_ieee:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f16_e64 v0, -v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub half -0.0, %v0
%mul = fmul half %sub, %v1
ret half %mul
}
define half @fold_f16_fsub_into_fneg_modifier_daz(half %v0, half %v1) #1 {
-; SDAG-LABEL: fold_f16_fsub_into_fneg_modifier_daz:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_mul_f16_e64 v0, -v0, v1
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: fold_f16_fsub_into_fneg_modifier_daz:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_max_f16_e64 v0, -v0, -v0
-; GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: fold_f16_fsub_into_fneg_modifier_daz:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f16_e64 v0, -v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub half -0.0, %v0
%mul = fmul half %sub, %v1
ret half %mul
}
define half @fold_f16_fsub_into_fneg_modifier_ieee_nsz(half %v0, half %v1) #0 {
-; SDAG-LABEL: fold_f16_fsub_into_fneg_modifier_ieee_nsz:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_mul_f16_e64 v0, -v0, v1
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: fold_f16_fsub_into_fneg_modifier_ieee_nsz:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_max_f16_e64 v0, -v0, -v0
-; GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: fold_f16_fsub_into_fneg_modifier_ieee_nsz:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f16_e64 v0, -v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub nsz half -0.0, %v0
%mul = fmul nsz half %sub, %v1
ret half %mul
}
define half @fold_f16_fsub_into_fneg_modifier_daz_nsz(half %v0, half %v1) #1 {
-; SDAG-LABEL: fold_f16_fsub_into_fneg_modifier_daz_nsz:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_mul_f16_e64 v0, -v0, v1
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: fold_f16_fsub_into_fneg_modifier_daz_nsz:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_max_f16_e64 v0, -v0, -v0
-; GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: fold_f16_fsub_into_fneg_modifier_daz_nsz:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f16_e64 v0, -v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub nsz half -0.0, %v0
%mul = fmul nsz half %sub, %v1
ret half %mul
}
define half @fold_f16_fsub_into_fneg_modifier_dynamic(half %v0, half %v1) #2 {
-; SDAG-LABEL: fold_f16_fsub_into_fneg_modifier_dynamic:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_mul_f16_e64 v0, -v0, v1
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: fold_f16_fsub_into_fneg_modifier_dynamic:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_max_f16_e64 v0, -v0, -v0
-; GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: fold_f16_fsub_into_fneg_modifier_dynamic:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f16_e64 v0, -v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub half -0.0, %v0
%mul = fmul half %sub, %v1
ret half %mul
}
define half @fold_f16_fsub_into_fneg_modifier_dynamic_nsz(half %v0, half %v1) #2 {
-; SDAG-LABEL: fold_f16_fsub_into_fneg_modifier_dynamic_nsz:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_mul_f16_e64 v0, -v0, v1
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: fold_f16_fsub_into_fneg_modifier_dynamic_nsz:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_max_f16_e64 v0, -v0, -v0
-; GISEL-NEXT: v_mul_f16_e32 v0, v0, v1
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: fold_f16_fsub_into_fneg_modifier_dynamic_nsz:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f16_e64 v0, -v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub nsz half -0.0, %v0
%mul = fmul nsz half %sub, %v1
ret half %mul
@@ -731,69 +689,42 @@ define float @no_fold_f32_select_user_fsub_into_fneg_modifier_dynamic(i1 %cond,
}
define half @fold_f16_select_user_fsub_into_fneg_modifier_ieee(i1 %cond, half %v0, half %v1) #0 {
-; SDAG-LABEL: fold_f16_select_user_fsub_into_fneg_modifier_ieee:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_and_b32_e32 v0, 1, v0
-; SDAG-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: fold_f16_select_user_fsub_into_fneg_modifier_ieee:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v0, 1, v0
-; GISEL-NEXT: v_max_f16_e64 v1, -v1, -v1
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: fold_f16_select_user_fsub_into_fneg_modifier_ieee:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT: v_xor_b32_e32 v1, 0x8000, v1
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub half -0.0, %v0
%mul = select i1 %cond, half %sub, half %v1
ret half %mul
}
define half @no_fold_f16_select_user_fsub_into_fneg_modifier_daz(i1 %cond, half %v0, half %v1) #1 {
-; SDAG-LABEL: no_fold_f16_select_user_fsub_into_fneg_modifier_daz:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_and_b32_e32 v0, 1, v0
-; SDAG-NEXT: v_sub_f16_e32 v1, 0x8000, v1
-; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: no_fold_f16_select_user_fsub_into_fneg_modifier_daz:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v0, 1, v0
-; GISEL-NEXT: v_max_f16_e64 v1, -v1, -v1
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: no_fold_f16_select_user_fsub_into_fneg_modifier_daz:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT: v_sub_f16_e32 v1, 0x8000, v1
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub half -0.0, %v0
%mul = select i1 %cond, half %sub, half %v1
ret half %mul
}
define half @no_fold_f16_select_user_fsub_into_fneg_modifier_dynamic(i1 %cond, half %v0, half %v1) #2 {
-; SDAG-LABEL: no_fold_f16_select_user_fsub_into_fneg_modifier_dynamic:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_and_b32_e32 v0, 1, v0
-; SDAG-NEXT: v_sub_f16_e32 v1, 0x8000, v1
-; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: no_fold_f16_select_user_fsub_into_fneg_modifier_dynamic:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v0, 1, v0
-; GISEL-NEXT: v_max_f16_e64 v1, -v1, -v1
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: no_fold_f16_select_user_fsub_into_fneg_modifier_dynamic:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT: v_sub_f16_e32 v1, 0x8000, v1
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub half -0.0, %v0
%mul = select i1 %cond, half %sub, half %v1
ret half %mul
@@ -1192,21 +1123,13 @@ define i1 @no_fold_f64_fsub_into_fneg_modifier_class_var_daz(double %v0, i32 %te
}
define i1 @no_fold_f16_fsub_into_fneg_modifier_class_var_daz(half %v0, i32 %testmask) #1 {
-; SDAG-LABEL: no_fold_f16_fsub_into_fneg_modifier_class_var_daz:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_sub_f16_e32 v0, 0x8000, v0
-; SDAG-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
-; SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: no_fold_f16_fsub_into_fneg_modifier_class_var_daz:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_max_f16_e64 v0, -v0, -v0
-; GISEL-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: no_fold_f16_fsub_into_fneg_modifier_class_var_daz:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_sub_f16_e32 v0, 0x8000, v0
+; CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub half -0.0, %v0
%class = call i1 @llvm.amdgcn.class.f16(half %sub, i32 %testmask)
ret i1 %class
@@ -1235,23 +1158,14 @@ define i1 @no_fold_f64_fsub_into_fneg_modifier_class_daz(double %v0) #1 {
}
define i1 @no_fold_f16_fsub_into_fneg_modifier_class_daz(half %v0) #1 {
-; SDAG-LABEL: no_fold_f16_fsub_into_fneg_modifier_class_daz:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: v_sub_f16_e32 v0, 0x8000, v0
-; SDAG-NEXT: v_mov_b32_e32 v1, 0x90
-; SDAG-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
-; SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-LABEL: no_fold_f16_fsub_into_fneg_modifier_class_daz:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_max_f16_e64 v0, -v0, -v0
-; GISEL-NEXT: v_mov_b32_e32 v1, 0x90
-; GISEL-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: no_fold_f16_fsub_into_fneg_modifier_class_daz:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_sub_f16_e32 v0, 0x8000, v0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0x90
+; CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%sub = fsub half -0.0, %v0
%class = call i1 @llvm.is.fpclass.f16(half %sub, i32 144)
ret i1 %class
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call.ll b/llvm/test/CodeGen/AMDGPU/indirect-call.ll
index ed6ce1e8cf76a..32387a9fe61ff 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-call.ll
@@ -46,10 +46,10 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr(i8) #0 {
; GISEL-NEXT: s_load_dwordx2 s[18:19], s[14:15], 0x0
; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GISEL-NEXT: s_add_u32 s8, s8, 8
-; GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
; GISEL-NEXT: s_addc_u32 s9, s9, 0
-; GISEL-NEXT: v_or_b32_e32 v31, v0, v2
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
; GISEL-NEXT: s_mov_b32 s14, s16
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
@@ -102,12 +102,12 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr_arg(i8) #0 {
; GISEL-NEXT: s_load_dwordx2 s[18:19], s[14:15], 0x0
; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GISEL-NEXT: s_add_u32 s8, s8, 8
-; GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
; GISEL-NEXT: s_addc_u32 s9, s9, 0
-; GISEL-NEXT: v_or_b32_e32 v31, v0, v2
-; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v1
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7b
+; GISEL-NEXT: s_mov_b32 s14, s16
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index cb28afcd54535..83bf546b52003 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -9,10 +9,10 @@
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG,GFX900-SDAG,GFX900 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL,GFX900-GISEL,GFX900 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL,GFX900-GISEL,GFX900 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A,GFX9-SDAG,GFX90A-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A,GFX9-GISEL,GFX90A-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A,GFX9-GISEL,GFX90A-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
@@ -28,9 +28,9 @@
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1200,GFX1200-GISEL,GFX1200-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG,GFX1250-FAKE16,GFX1250-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16,GFX1250-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16,GFX1250-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG,GFX1250-REAL16,GFX1250-SDAG-REAL16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16,GFX1250-GISEL-REAL16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16,GFX1250-GISEL-REAL16 %s
; Test for integer mad formation for patterns used in clpeak
diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
index 08de0a47e9073..257c63a00d7e5 100644
--- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
@@ -522,35 +522,35 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_cc_float(float inreg %a, float %b)
define amdgpu_cs_chain void @amdgpu_cs_chain_cc_half(half inreg %a, half %b) {
; GISEL-GFX11-LABEL: name: amdgpu_cs_chain_cc_half
- ; GISEL-GFX11: bb.1 (%ir-block.0):
+ ; GISEL-GFX11: bb.0 (%ir-block.0):
; GISEL-GFX11-NEXT: liveins: $sgpr0, $vgpr8
; GISEL-GFX11-NEXT: {{ $}}
- ; GISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
- ; GISEL-GFX11-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
- ; GISEL-GFX11-NEXT: $vgpr0 = COPY [[COPY]]
- ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY1]]
- ; GISEL-GFX11-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def $scc
- ; GISEL-GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4)
- ; GISEL-GFX11-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1
- ; GISEL-GFX11-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
+ ; GISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; GISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+ ; GISEL-GFX11-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
+ ; GISEL-GFX11-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def dead $scc
+ ; GISEL-GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
+ ; GISEL-GFX11-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY]]
+ ; GISEL-GFX11-NEXT: $sgpr30_sgpr31 = SI_CALL killed [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1
+ ; GISEL-GFX11-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; GISEL-GFX11-NEXT: S_ENDPGM 0
;
; GISEL-GFX10-LABEL: name: amdgpu_cs_chain_cc_half
- ; GISEL-GFX10: bb.1 (%ir-block.0):
+ ; GISEL-GFX10: bb.0 (%ir-block.0):
; GISEL-GFX10-NEXT: liveins: $sgpr0, $vgpr8
; GISEL-GFX10-NEXT: {{ $}}
- ; GISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
- ; GISEL-GFX10-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
- ; GISEL-GFX10-NEXT: $vgpr0 = COPY [[COPY]]
- ; GISEL-GFX10-NEXT: $vgpr1 = COPY [[COPY1]]
+ ; GISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; GISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+ ; GISEL-GFX10-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
+ ; GISEL-GFX10-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def dead $scc
+ ; GISEL-GFX10-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
; GISEL-GFX10-NEXT: [[COPY2:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51
; GISEL-GFX10-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY2]]
- ; GISEL-GFX10-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def $scc
- ; GISEL-GFX10-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4)
- ; GISEL-GFX10-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3
- ; GISEL-GFX10-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
+ ; GISEL-GFX10-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; GISEL-GFX10-NEXT: $vgpr1 = COPY [[COPY]]
+ ; GISEL-GFX10-NEXT: $sgpr30_sgpr31 = SI_CALL killed [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit $vgpr1
+ ; GISEL-GFX10-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; GISEL-GFX10-NEXT: S_ENDPGM 0
;
; DAGISEL-GFX11-LABEL: name: amdgpu_cs_chain_cc_half
@@ -590,35 +590,35 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_cc_half(half inreg %a, half %b) {
define amdgpu_cs_chain void @amdgpu_cs_chain_cc_bfloat(bfloat inreg %a, bfloat %b) {
; GISEL-GFX11-LABEL: name: amdgpu_cs_chain_cc_bfloat
- ; GISEL-GFX11: bb.1 (%ir-block.0):
+ ; GISEL-GFX11: bb.0 (%ir-block.0):
; GISEL-GFX11-NEXT: liveins: $sgpr0, $vgpr8
; GISEL-GFX11-NEXT: {{ $}}
- ; GISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
- ; GISEL-GFX11-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
- ; GISEL-GFX11-NEXT: $vgpr0 = COPY [[COPY]]
- ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY1]]
- ; GISEL-GFX11-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def $scc
- ; GISEL-GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4)
- ; GISEL-GFX11-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1
- ; GISEL-GFX11-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
+ ; GISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; GISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+ ; GISEL-GFX11-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
+ ; GISEL-GFX11-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def dead $scc
+ ; GISEL-GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
+ ; GISEL-GFX11-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY]]
+ ; GISEL-GFX11-NEXT: $sgpr30_sgpr31 = SI_CALL killed [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1
+ ; GISEL-GFX11-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; GISEL-GFX11-NEXT: S_ENDPGM 0
;
; GISEL-GFX10-LABEL: name: amdgpu_cs_chain_cc_bfloat
- ; GISEL-GFX10: bb.1 (%ir-block.0):
+ ; GISEL-GFX10: bb.0 (%ir-block.0):
; GISEL-GFX10-NEXT: liveins: $sgpr0, $vgpr8
; GISEL-GFX10-NEXT: {{ $}}
- ; GISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
- ; GISEL-GFX10-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
- ; GISEL-GFX10-NEXT: $vgpr0 = COPY [[COPY]]
- ; GISEL-GFX10-NEXT: $vgpr1 = COPY [[COPY1]]
+ ; GISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; GISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+ ; GISEL-GFX10-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
+ ; GISEL-GFX10-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def dead $scc
+ ; GISEL-GFX10-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
; GISEL-GFX10-NEXT: [[COPY2:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51
; GISEL-GFX10-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY2]]
- ; GISEL-GFX10-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def $scc
- ; GISEL-GFX10-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4)
- ; GISEL-GFX10-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3
- ; GISEL-GFX10-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
+ ; GISEL-GFX10-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; GISEL-GFX10-NEXT: $vgpr1 = COPY [[COPY]]
+ ; GISEL-GFX10-NEXT: $sgpr30_sgpr31 = SI_CALL killed [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit $vgpr1
+ ; GISEL-GFX10-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; GISEL-GFX10-NEXT: S_ENDPGM 0
;
; DAGISEL-GFX11-LABEL: name: amdgpu_cs_chain_cc_bfloat
diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
index e9da4a992bfe7..22b87ec313558 100644
--- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
@@ -735,43 +735,40 @@ define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_cc_float(float in
define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_cc_half(half inreg %a, half %b) {
; GISEL-GFX11-TRUE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
- ; GISEL-GFX11-TRUE16: bb.1 (%ir-block.0):
+ ; GISEL-GFX11-TRUE16: bb.0 (%ir-block.0):
; GISEL-GFX11-TRUE16-NEXT: liveins: $sgpr0, $vgpr8
; GISEL-GFX11-TRUE16-NEXT: {{ $}}
- ; GISEL-GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GISEL-GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
- ; GISEL-GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
+ ; GISEL-GFX11-TRUE16-NEXT: [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
; GISEL-GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
- ; GISEL-GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
- ; GISEL-GFX11-TRUE16-NEXT: [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, [[COPY3]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
- ; GISEL-GFX11-TRUE16-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[DEF]]
- ; GISEL-GFX11-TRUE16-NEXT: FLAT_STORE_SHORT_t16 [[COPY4]], [[V_ADD_F16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (f16) into `ptr poison`)
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+ ; GISEL-GFX11-TRUE16-NEXT: FLAT_STORE_SHORT_t16 killed [[COPY3]], killed [[V_ADD_F16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
; GISEL-GFX11-TRUE16-NEXT: S_ENDPGM 0
;
; GISEL-GFX11-FAKE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
- ; GISEL-GFX11-FAKE16: bb.1 (%ir-block.0):
+ ; GISEL-GFX11-FAKE16: bb.0 (%ir-block.0):
; GISEL-GFX11-FAKE16-NEXT: liveins: $sgpr0, $vgpr8
; GISEL-GFX11-FAKE16-NEXT: {{ $}}
- ; GISEL-GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GISEL-GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; GISEL-GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; GISEL-GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+ ; GISEL-GFX11-FAKE16-NEXT: [[V_ADD_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_fake16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GISEL-GFX11-FAKE16-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
- ; GISEL-GFX11-FAKE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
- ; GISEL-GFX11-FAKE16-NEXT: [[V_ADD_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_fake16_e64 0, [[COPY2]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-GFX11-FAKE16-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
- ; GISEL-GFX11-FAKE16-NEXT: FLAT_STORE_SHORT [[COPY3]], [[V_ADD_F16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (f16) into `ptr poison`)
+ ; GISEL-GFX11-FAKE16-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+ ; GISEL-GFX11-FAKE16-NEXT: FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_F16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
; GISEL-GFX11-FAKE16-NEXT: S_ENDPGM 0
;
; GISEL-GFX10-LABEL: name: amdgpu_cs_chain_preserve_cc_half
- ; GISEL-GFX10: bb.1 (%ir-block.0):
+ ; GISEL-GFX10: bb.0 (%ir-block.0):
; GISEL-GFX10-NEXT: liveins: $sgpr0, $vgpr8
; GISEL-GFX10-NEXT: {{ $}}
- ; GISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; GISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; GISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+ ; GISEL-GFX10-NEXT: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GISEL-GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
- ; GISEL-GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
- ; GISEL-GFX10-NEXT: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY2]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-GFX10-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
- ; GISEL-GFX10-NEXT: FLAT_STORE_SHORT [[COPY3]], [[V_ADD_F16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (f16) into `ptr poison`)
+ ; GISEL-GFX10-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+ ; GISEL-GFX10-NEXT: FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_F16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
; GISEL-GFX10-NEXT: S_ENDPGM 0
;
; DAGISEL-GFX11-WF32-TRUE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
index 160230819cc9a..228b80174111c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
@@ -243,9 +243,9 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte0:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
+; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1
-; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
+; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 0)
store i32 %cvt, ptr addrspace(1) %out
@@ -294,9 +294,9 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
+; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:1
-; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
+; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 1)
store i32 %cvt, ptr addrspace(1) %out
@@ -331,9 +331,9 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte2:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
+; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:2
-; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
+; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 2)
store i32 %cvt, ptr addrspace(1) %out
@@ -368,9 +368,9 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte3:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
+; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:3
-; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
+; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 3)
store i32 %cvt, ptr addrspace(1) %out
@@ -447,9 +447,9 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte0:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
+; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1
-; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
+; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 0)
store i32 %cvt, ptr addrspace(1) %out
@@ -498,9 +498,9 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
+; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:1
-; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
+; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 1)
store i32 %cvt, ptr addrspace(1) %out
@@ -535,9 +535,9 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte2:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
+; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:2
-; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
+; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 2)
store i32 %cvt, ptr addrspace(1) %out
@@ -572,9 +572,9 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte3:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
+; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:3
-; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
+; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 3)
store i32 %cvt, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
index b73053e554e1c..e896b3fff42ef 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
@@ -2,7 +2,7 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=ASM-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=ASM-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=ASM-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=ASM-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=ASM-GISEL-FAKE16 %s
; Test that we can use v0 for temporaries in the if.then block.
define i32 @dead_i32(i1 %cond, i32 %x, ptr addrspace(1) %ptr1) #0 {
@@ -771,47 +771,44 @@ define %non_trivial_types @dead_non_trivial(i1 %cond, %non_trivial_types %x, ptr
; ASM-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; ASM-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; ASM-GISEL-FAKE16-NEXT: s_clause 0x15
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v33, off, s32
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v34, off, s32 offset:4
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v35, off, s32 offset:8
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v36, off, s32 offset:12
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v37, off, s32 offset:16
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v38, off, s32 offset:20
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v39, off, s32 offset:24
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v48, off, s32 offset:28
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v49, off, s32 offset:32
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v50, off, s32 offset:36
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v51, off, s32 offset:40
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v52, off, s32 offset:44
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v53, off, s32 offset:48
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:52
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v55, off, s32 offset:56
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v64, off, s32 offset:60
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v65, off, s32 offset:64
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v66, off, s32 offset:68
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v67, off, s32 offset:72
-; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:76
; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v32, off, s32 offset:80
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:76
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:72
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v34, off, s32 offset:68
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v35, off, s32 offset:64
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v36, off, s32 offset:60
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v37, off, s32 offset:56
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v38, off, s32 offset:52
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v39, off, s32 offset:48
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v48, off, s32 offset:44
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v49, off, s32 offset:40
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v50, off, s32 offset:36
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v51, off, s32 offset:32
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v52, off, s32 offset:28
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v53, off, s32 offset:24
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:20
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v55, off, s32 offset:16
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v64, off, s32 offset:12
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v65, off, s32 offset:8
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v66, off, s32 offset:4
+; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v67, off, s32
; ASM-GISEL-FAKE16-NEXT: scratch_load_b32 v68, off, s32 offset:84
; ASM-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; ASM-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; ASM-GISEL-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1
+; ASM-GISEL-FAKE16-NEXT: v_cmpx_eq_u32_e32 1, v1
; ASM-GISEL-FAKE16-NEXT: s_cbranch_execz .LBB3_2
; ASM-GISEL-FAKE16-NEXT: ; %bb.1: ; %if.then
-; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s1, 0
-; ASM-GISEL-FAKE16-NEXT: s_movk_i32 s2, 0x3e00
; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
-; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_add_nc_u32 v1, 15, v68
-; ASM-GISEL-FAKE16-NEXT: v_mov_b32_e32 v8, s1
+; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v1, 15, v68
+; ASM-GISEL-FAKE16-NEXT: v_mov_b32_e32 v4, 0x3e00
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr2
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr3
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr5
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr6
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr7
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12_vgpr13
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr14_vgpr15_vgpr16_vgpr17
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr14_vgpr15
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr18
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr19
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr20
@@ -825,42 +822,42 @@ define %non_trivial_types @dead_non_trivial(i1 %cond, %non_trivial_types %x, ptr
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr28
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr29
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr30
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr33
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr34
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr35
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr36
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr37
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr38
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr39
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr48
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr49
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr50
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr51
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr52
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr53
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr54
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr55
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr64
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr65
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr66
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr67
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr66
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr65
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr64
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr55
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr54
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr53
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr52
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr51
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr50
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr49
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr48
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr39
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr38
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr37
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr36
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr35
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr34
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr33
; ASM-GISEL-FAKE16-NEXT: global_store_b32 v[31:32], v1, off
; ASM-GISEL-FAKE16-NEXT: .LBB3_2: ; %if.end
; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-GISEL-FAKE16-NEXT: s_clause 0x16
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b8 v0, v2, off
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b16 v0, v3, off offset:2
; ASM-GISEL-FAKE16-NEXT: scratch_store_b16 v0, v4, off offset:4
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b16 v0, v3, off offset:2
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b8 v0, v2, off
; ASM-GISEL-FAKE16-NEXT: scratch_store_b16 v0, v5, off offset:6
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v6, off offset:8
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v7, off offset:12
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v8, off offset:16
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v13, off offset:48
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b128 v0, v[14:17], off offset:64
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v18, off offset:80
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v19, off offset:84
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b128 v0, v[14:17], off offset:64
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v20, off offset:88
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v21, off offset:92
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v22, off offset:96
@@ -872,44 +869,27 @@ define %non_trivial_types @dead_non_trivial(i1 %cond, %non_trivial_types %x, ptr
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v28, off offset:120
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v29, off offset:124
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v30, off offset:128
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x15
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v33, off offset:132
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x14
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v34, off offset:136
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x13
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v35, off offset:140
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x12
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v36, off offset:144
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x11
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v37, off offset:148
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x10
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v38, off offset:152
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0xf
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v39, off offset:156
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0xe
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v48, off offset:160
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0xd
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v49, off offset:164
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0xc
+; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x1
+; ASM-GISEL-FAKE16-NEXT: s_clause 0x12
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v67, off offset:132
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v66, off offset:136
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v65, off offset:140
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v64, off offset:144
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v55, off offset:148
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v54, off offset:152
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v53, off offset:156
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v52, off offset:160
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v51, off offset:164
; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v50, off offset:168
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0xb
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v51, off offset:172
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0xa
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v52, off offset:176
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x9
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v53, off offset:180
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x8
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v54, off offset:184
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x7
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v55, off offset:188
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x6
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v64, off offset:192
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x5
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v65, off offset:196
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x4
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v66, off offset:200
-; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x3
-; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v67, off offset:204
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v49, off offset:172
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v48, off offset:176
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v39, off offset:180
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v38, off offset:184
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v37, off offset:188
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v36, off offset:192
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v35, off offset:196
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v34, off offset:200
+; ASM-GISEL-FAKE16-NEXT: scratch_store_b32 v0, v33, off offset:204
; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
; ASM-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
; ASM-GISEL-LABEL: dead_non_trivial:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
index d183754c6fe91..7cd12145d9b7f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GISEL %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
define float @v_exp2_f32(float %src) {
; GCN-LABEL: v_exp2_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
index 3ff5b68ba6ecc..1be64166d16af 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-GISEL %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-GISEL %s
declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
index 55127032a982d..5379546f7ee5f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel < %s | FileCheck -check-prefixes=GFX10GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX10GISEL %s
; TODO: global-isel produces more code - there will need to be some more combines in the postregbankselectcombine phase
; Depends on some other changes to pass this test - those are in review separately
@@ -13,8 +13,6 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
;
; GFX10GISEL-LABEL: sample_d_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -33,8 +31,7 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
;
; GFX10GISEL-LABEL: sample_d_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX10GISEL-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -60,11 +57,15 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
;
; GFX10GISEL-LABEL: sample_d_3d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX10GISEL-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX10GISEL-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX10GISEL-NEXT: v_lshl_or_b32 v7, s0, 16, v8
-; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX10GISEL-NEXT: v_mov_b32_e32 v15, v8
+; GFX10GISEL-NEXT: v_mov_b32_e32 v13, v5
+; GFX10GISEL-NEXT: v_mov_b32_e32 v12, v4
+; GFX10GISEL-NEXT: v_mov_b32_e32 v11, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v2
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v1
+; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v0
+; GFX10GISEL-NEXT: v_perm_b32 v14, v7, v6, 0x5040100
+; GFX10GISEL-NEXT: image_sample_d v[0:3], v[8:15], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -81,8 +82,6 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
;
; GFX10GISEL-LABEL: sample_c_d_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10GISEL-NEXT: v_lshl_or_b32 v3, s0, 16, v3
; GFX10GISEL-NEXT: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -101,8 +100,7 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
;
; GFX10GISEL-LABEL: sample_c_d_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX10GISEL-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -121,8 +119,7 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
;
; GFX10GISEL-LABEL: sample_d_cl_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX10GISEL-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX10GISEL-NEXT: image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -146,11 +143,13 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
;
; GFX10GISEL-LABEL: sample_d_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX10GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, s0, 16, v6
-; GFX10GISEL-NEXT: image_sample_d_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX10GISEL-NEXT: v_mov_b32_e32 v11, v6
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v2
+; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v1
+; GFX10GISEL-NEXT: v_mov_b32_e32 v6, v0
+; GFX10GISEL-NEXT: v_perm_b32 v10, v5, v4, 0x5040100
+; GFX10GISEL-NEXT: image_sample_d_cl v[0:3], v[6:11], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -168,8 +167,7 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
;
; GFX10GISEL-LABEL: sample_c_d_cl_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10GISEL-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX10GISEL-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -194,11 +192,14 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
;
; GFX10GISEL-LABEL: sample_c_d_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX10GISEL-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX10GISEL-NEXT: v_lshl_or_b32 v6, s0, 16, v7
-; GFX10GISEL-NEXT: image_sample_c_d_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX10GISEL-NEXT: v_mov_b32_e32 v13, v7
+; GFX10GISEL-NEXT: v_mov_b32_e32 v11, v4
+; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v2
+; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v1
+; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v0
+; GFX10GISEL-NEXT: v_perm_b32 v12, v6, v5, 0x5040100
+; GFX10GISEL-NEXT: image_sample_c_d_cl v[0:3], v[7:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -215,8 +216,6 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
;
; GFX10GISEL-LABEL: sample_cd_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10GISEL-NEXT: image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -235,8 +234,7 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
;
; GFX10GISEL-LABEL: sample_cd_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX10GISEL-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
; GFX10GISEL-NEXT: image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -254,8 +252,6 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
;
; GFX10GISEL-LABEL: sample_c_cd_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10GISEL-NEXT: v_lshl_or_b32 v3, s0, 16, v3
; GFX10GISEL-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -274,8 +270,7 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
;
; GFX10GISEL-LABEL: sample_c_cd_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX10GISEL-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -294,8 +289,7 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
;
; GFX10GISEL-LABEL: sample_cd_cl_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX10GISEL-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX10GISEL-NEXT: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -319,11 +313,13 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
;
; GFX10GISEL-LABEL: sample_cd_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX10GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, s0, 16, v6
-; GFX10GISEL-NEXT: image_sample_cd_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX10GISEL-NEXT: v_mov_b32_e32 v11, v6
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v2
+; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v1
+; GFX10GISEL-NEXT: v_mov_b32_e32 v6, v0
+; GFX10GISEL-NEXT: v_perm_b32 v10, v5, v4, 0x5040100
+; GFX10GISEL-NEXT: image_sample_cd_cl v[0:3], v[6:11], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -341,8 +337,7 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
;
; GFX10GISEL-LABEL: sample_c_cd_cl_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10GISEL-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX10GISEL-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -367,11 +362,14 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
;
; GFX10GISEL-LABEL: sample_c_cd_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX10GISEL-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX10GISEL-NEXT: v_lshl_or_b32 v6, s0, 16, v7
-; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX10GISEL-NEXT: v_mov_b32_e32 v13, v7
+; GFX10GISEL-NEXT: v_mov_b32_e32 v11, v4
+; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v2
+; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v1
+; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v0
+; GFX10GISEL-NEXT: v_perm_b32 v12, v6, v5, 0x5040100
+; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[7:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -396,11 +394,15 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
;
; GFX10GISEL-LABEL: sample_c_d_o_2darray_V1:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX10GISEL-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX10GISEL-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX10GISEL-NEXT: v_lshl_or_b32 v7, s0, 16, v8
-; GFX10GISEL-NEXT: image_sample_c_d_o v0, v[0:7], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX10GISEL-NEXT: v_mov_b32_e32 v15, v8
+; GFX10GISEL-NEXT: v_mov_b32_e32 v13, v5
+; GFX10GISEL-NEXT: v_mov_b32_e32 v12, v4
+; GFX10GISEL-NEXT: v_mov_b32_e32 v11, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v2
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v1
+; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v0
+; GFX10GISEL-NEXT: v_perm_b32 v14, v7, v6, 0x5040100
+; GFX10GISEL-NEXT: image_sample_c_d_o v0, v[8:15], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -425,11 +427,15 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
;
; GFX10GISEL-LABEL: sample_c_d_o_2darray_V2:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX10GISEL-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX10GISEL-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX10GISEL-NEXT: v_lshl_or_b32 v7, s0, 16, v8
-; GFX10GISEL-NEXT: image_sample_c_d_o v[0:1], v[0:7], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX10GISEL-NEXT: v_mov_b32_e32 v15, v8
+; GFX10GISEL-NEXT: v_mov_b32_e32 v13, v5
+; GFX10GISEL-NEXT: v_mov_b32_e32 v12, v4
+; GFX10GISEL-NEXT: v_mov_b32_e32 v11, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v2
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v1
+; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v0
+; GFX10GISEL-NEXT: v_perm_b32 v14, v7, v6, 0x5040100
+; GFX10GISEL-NEXT: image_sample_c_d_o v[0:1], v[8:15], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -468,10 +474,6 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_d_1d(<8 x i32> inreg %rsrc, <4 x
;
; GFX10GISEL-LABEL: sample_g16_noa16_d_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -491,11 +493,9 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_d_2d(<8 x i32> inreg %rsrc, <4 x
;
; GFX10GISEL-LABEL: sample_g16_noa16_d_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10GISEL-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -516,14 +516,10 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_d_3d(<8 x i32> inreg %rsrc, <4 x
;
; GFX10GISEL-LABEL: sample_g16_noa16_d_3d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v9, 0xffff, v2
-; GFX10GISEL-NEXT: v_and_b32_e32 v10, 0xffff, v3
-; GFX10GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, v1, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v3, s0, 16, v9
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v4, 16, v10
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, s0, 16, v5
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v3, v2
+; GFX10GISEL-NEXT: v_perm_b32 v2, v1, v0, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v4, v4, v9, 0x5040100
; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[2:8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -541,10 +537,6 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_1d(<8 x i32> inreg %rsrc, <4
;
; GFX10GISEL-LABEL: sample_g16_noa16_c_d_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10GISEL-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -564,11 +556,9 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_2d(<8 x i32> inreg %rsrc, <4
;
; GFX10GISEL-LABEL: sample_g16_noa16_c_d_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX10GISEL-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10GISEL-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10GISEL-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -585,10 +575,6 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_d_cl_1d(<8 x i32> inreg %rsrc, <4
;
; GFX10GISEL-LABEL: sample_g16_noa16_d_cl_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX10GISEL-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -608,11 +594,9 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_d_cl_2d(<8 x i32> inreg %rsrc, <4
;
; GFX10GISEL-LABEL: sample_g16_noa16_d_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX10GISEL-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10GISEL-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10GISEL-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -629,10 +613,6 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_1d(<8 x i32> inreg %rsrc,
;
; GFX10GISEL-LABEL: sample_g16_noa16_c_d_cl_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10GISEL-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -656,10 +636,8 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_2d(<8 x i32> inreg %rsrc,
; GFX10GISEL: ; %bb.0: ; %main_body
; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v2
; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX10GISEL-NEXT: v_lshl_or_b32 v3, v8, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v4, 16, v1
+; GFX10GISEL-NEXT: v_perm_b32 v4, v4, v3, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v3, v8, v1, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_d_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -677,10 +655,6 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_cd_1d(<8 x i32> inreg %rsrc, <4 x
;
; GFX10GISEL-LABEL: sample_g16_noa16_cd_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX10GISEL-NEXT: image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -700,11 +674,9 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_cd_2d(<8 x i32> inreg %rsrc, <4 x
;
; GFX10GISEL-LABEL: sample_g16_noa16_cd_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX10GISEL-NEXT: image_sample_cd_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10GISEL-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10GISEL-NEXT: image_sample_cd_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -721,10 +693,6 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_1d(<8 x i32> inreg %rsrc, <4
;
; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10GISEL-NEXT: image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -744,11 +712,9 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_2d(<8 x i32> inreg %rsrc, <4
;
; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX10GISEL-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10GISEL-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX10GISEL-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -765,10 +731,6 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_cd_cl_1d(<8 x i32> inreg %rsrc, <
;
; GFX10GISEL-LABEL: sample_g16_noa16_cd_cl_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX10GISEL-NEXT: image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -788,11 +750,9 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_cd_cl_2d(<8 x i32> inreg %rsrc, <
;
; GFX10GISEL-LABEL: sample_g16_noa16_cd_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX10GISEL-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10GISEL-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10GISEL-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -809,10 +769,6 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_1d(<8 x i32> inreg %rsrc,
;
; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_cl_1d:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10GISEL-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -836,10 +792,8 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_2d(<8 x i32> inreg %rsrc,
; GFX10GISEL: ; %bb.0: ; %main_body
; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v2
; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX10GISEL-NEXT: v_lshl_or_b32 v3, v8, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v4, 16, v1
+; GFX10GISEL-NEXT: v_perm_b32 v4, v4, v3, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v3, v8, v1, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -863,14 +817,12 @@ define amdgpu_ps float @sample_g16_noa16_c_d_o_2darray_V1(<8 x i32> inreg %rsrc,
;
; GFX10GISEL-LABEL: sample_g16_noa16_c_d_o_2darray_V1:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v2
-; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v3
-; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v2
; GFX10GISEL-NEXT: v_mov_b32_e32 v3, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v9
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, v5, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v10, 16, v0
+; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0
+; GFX10GISEL-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v4, v9, v10, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_d_o_g16 v0, v[2:8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -894,14 +846,12 @@ define amdgpu_ps <2 x float> @sample_g16_noa16_c_d_o_2darray_V2(<8 x i32> inreg
;
; GFX10GISEL-LABEL: sample_g16_noa16_c_d_o_2darray_V2:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v2
-; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v3
-; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0
+; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v3
+; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v2
; GFX10GISEL-NEXT: v_mov_b32_e32 v3, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v9
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, v5, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v10, 16, v0
+; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0
+; GFX10GISEL-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v4, v9, v10, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_d_o_g16 v[0:1], v[2:8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -941,12 +891,6 @@ define amdgpu_ps <4 x float> @sample_d_1d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
;
; GFX10GISEL-LABEL: sample_d_1d_g16_a16:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, s0, 16, v2
; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
@@ -967,13 +911,10 @@ define amdgpu_ps <4 x float> @sample_d_2d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
;
; GFX10GISEL-LABEL: sample_d_2d_g16_a16:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX10GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, v5, 16, v4
-; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX10GISEL-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v3, v3, v2, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v2, v1, v0, 0x5040100
+; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[2:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
@@ -996,19 +937,13 @@ define amdgpu_ps <4 x float> @sample_d_3d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3
;
; GFX10GISEL-LABEL: sample_d_3d_g16_a16:
; GFX10GISEL: ; %bb.0: ; %main_body
-; GFX10GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX10GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX10GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v5
-; GFX10GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v6
-; GFX10GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v8
-; GFX10GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10GISEL-NEXT: v_lshl_or_b32 v2, v4, 16, v2
-; GFX10GISEL-NEXT: v_lshl_or_b32 v3, s0, 16, v3
-; GFX10GISEL-NEXT: v_lshl_or_b32 v4, v7, 16, v5
-; GFX10GISEL-NEXT: v_lshl_or_b32 v5, s0, 16, v6
-; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX10GISEL-NEXT: v_mov_b32_e32 v12, v8
+; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v5
+; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v2
+; GFX10GISEL-NEXT: v_perm_b32 v11, v7, v6, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v9, v4, v3, 0x5040100
+; GFX10GISEL-NEXT: v_perm_b32 v7, v1, v0, 0x5040100
+; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[7:12], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog
main_body:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
index 0a580d2232502..2f52f34fafebc 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-GISEL %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-FAKE16 %s
define amdgpu_ps void @sample_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
; GFX10_11-LABEL: sample_1d_nortn:
@@ -437,38 +437,15 @@ main_body:
}
define amdgpu_ps void @sample_d_1d_g16_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
-; GFX10_11-SDAG-LABEL: sample_d_1d_g16_nortn:
-; GFX10_11-SDAG: ; %bb.0: ; %main_body
-; GFX10_11-SDAG-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10_11-SDAG-NEXT: s_endpgm
-;
-; GFX10_11-GISEL-LABEL: sample_d_1d_g16_nortn:
-; GFX10_11-GISEL: ; %bb.0: ; %main_body
-; GFX10_11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10_11-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10_11-GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10_11-GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10_11-GISEL-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10_11-GISEL-NEXT: s_endpgm
-;
-; GFX12PLUS-SDAG-LABEL: sample_d_1d_g16_nortn:
-; GFX12PLUS-SDAG: ; %bb.0: ; %main_body
-; GFX12PLUS-SDAG-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12PLUS-SDAG-NEXT: s_endpgm
-;
-; GFX12PLUS-GISEL-TRUE16-LABEL: sample_d_1d_g16_nortn:
-; GFX12PLUS-GISEL-TRUE16: ; %bb.0: ; %main_body
-; GFX12PLUS-GISEL-TRUE16-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12PLUS-GISEL-TRUE16-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_d_1d_g16_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12PLUS-GISEL-FAKE16-LABEL: sample_d_1d_g16_nortn:
-; GFX12PLUS-GISEL-FAKE16: ; %bb.0: ; %main_body
-; GFX12PLUS-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12PLUS-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12PLUS-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX12PLUS-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX12PLUS-GISEL-FAKE16-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12PLUS-GISEL-FAKE16-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_d_1d_g16_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.d.1d.nortn.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
@@ -499,3 +476,6 @@ declare void @llvm.amdgcn.image.sample.d.1d.nortn.f16.f32(i32, half, half, float
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX12PLUS-GISEL-FAKE16: {{.*}}
+; GFX12PLUS-GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
index a945fc295d22c..f2b6095b35467 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
@@ -4,9 +4,9 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16,GFX12-TRUE16-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16,GFX12-TRUE16-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16,GFX12-TRUE16-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX12-FAKE16-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX12-FAKE16-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX12-FAKE16-GISEL %s
define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
; GFX11-LABEL: v_interp_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
index e7980ba554474..7e364cb287682 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
@@ -5,13 +5,13 @@
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=PRE-GFX12,GFX10,GFX10-GISEL,GFX1030-GISEL %s
; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1012 < %s 2>&1 | FileCheck -check-prefix=ERR %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=PRE-GFX12,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=PRE-GFX12,GFX11-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=PRE-GFX12,GFX11-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=PRE-GFX12,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=PRE-GFX12,GFX11-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=PRE-GFX12,GFX11-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
index bee6b07941b43..7db61c783c5ec 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
@@ -3,10 +3,10 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,CI-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,CI-GISEL %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,CI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
define amdgpu_kernel void @is_private_vgpr(ptr addrspace(1) %ptr.ptr) {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
index 88f00395368f1..b626e562a4a99 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
define float @v_log_f32(float %src) {
; GCN-LABEL: v_log_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
index b5e2ab05bf7f8..0476c346436ad 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
@@ -1,5 +1,5 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefix=ERR-SDAG %s
; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefix=ERR-GISEL %s
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
index aa994558162db..551e906859224 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG-TRUE16 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL-FAKE16 %s
define half @v_sqrt_f16(half %src) {
; GCN-LABEL: v_sqrt_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
index 7fb6bc782a4ef..310a428638c7a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
@@ -2325,11 +2325,11 @@ define void @test_writelane_i16(ptr addrspace(1) %out, i16 %src, i32 %src1) {
; GFX802-GISEL: ; %bb.0:
; GFX802-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX802-GISEL-NEXT: flat_load_ushort v4, v[0:1]
-; GFX802-GISEL-NEXT: v_readfirstlane_b32 s4, v3
-; GFX802-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; GFX802-GISEL-NEXT: s_mov_b32 m0, s4
+; GFX802-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX802-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX802-GISEL-NEXT: s_mov_b32 m0, s5
; GFX802-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX802-GISEL-NEXT: v_writelane_b32 v4, s5, m0
+; GFX802-GISEL-NEXT: v_writelane_b32 v4, s4, m0
; GFX802-GISEL-NEXT: flat_store_short v[0:1], v4
; GFX802-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX802-GISEL-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
index 6bf7c6b7bb10b..b2c573e6578c8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
@@ -10,9 +10,9 @@
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define { half, i32 } @test_frexp_f16_i32(half %a) {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
index 3603e87d7ddae..4a9b61bce0a88 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
@@ -201,17 +201,17 @@ define half @test_ldexp_f16_i8(half %a, i8 %b) {
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_ldexp_f16_i8:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_ldexp_f16_sdwa v0, v0, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_ldexp_f16_i8:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_ldexp_f16_sdwa v0, v0, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_ldexp_f16_i8:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_ldexp_f16_sdwa v0, v0, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: test_ldexp_f16_i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_ldexp_f16_sdwa v0, v0, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_ldexp_f16_i8:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -229,26 +229,6 @@ define half @test_ldexp_f16_i8(half %a, i8 %b) {
; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-GISEL-LABEL: test_ldexp_f16_i8:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
-; GFX8-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3
-; GFX8-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_ldexp_f16_i8:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
-; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3
-; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-GISEL-TRUE16-LABEL: test_ldexp_f16_i8:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -263,9 +243,7 @@ define half @test_ldexp_f16_i8(half %a, i8 %b) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.ldexp.f16.i8(half %a, i8 %b)
@@ -330,23 +308,23 @@ define half @test_ldexp_f16_i32(half %a, i32 %b) {
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_ldexp_f16_i32:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX8-SDAG-NEXT: v_med3_i32 v1, v1, s4, v2
-; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_ldexp_f16_i32:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX9-SDAG-NEXT: v_med3_i32 v1, v1, s4, v2
-; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_ldexp_f16_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_movk_i32 s4, 0x8000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX8-NEXT: v_med3_i32 v1, v1, s4, v2
+; GFX8-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: test_ldexp_f16_i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x8000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX9-NEXT: v_med3_i32 v1, v1, s4, v2
+; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_ldexp_f16_i32:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -366,24 +344,6 @@ define half @test_ldexp_f16_i32(half %a, i32 %b) {
; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-GISEL-LABEL: test_ldexp_f16_i32:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
-; GFX8-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3
-; GFX8-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_ldexp_f16_i32:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
-; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3
-; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-GISEL-TRUE16-LABEL: test_ldexp_f16_i32:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -396,9 +356,9 @@ define half @test_ldexp_f16_i32(half %a, i32 %b) {
; GFX11-GISEL-FAKE16-LABEL: test_ldexp_f16_i32:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.ldexp.f16.i32(half %a, i32 %b)
@@ -1131,3 +1091,7 @@ attributes #0 = { nounwind readnone }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX6-GISEL: {{.*}}
; GFX6-SDAG: {{.*}}
+; GFX8-GISEL: {{.*}}
+; GFX8-SDAG: {{.*}}
+; GFX9-GISEL: {{.*}}
+; GFX9-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
index bfbc7b07c71f1..b215d75009c02 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=CHECK,DAGISEL
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=CHECK,DAGISEL
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=CHECK,GISEL
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=CHECK,GISEL
+; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=CHECK,GISEL
+; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=CHECK,GISEL
; Test that in dynamic VGPR mode, the return of sponentry points after the area reserved for CWSR.
@@ -105,24 +105,43 @@ if.end:
declare amdgpu_gfx i32 @callee()
define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_calls(i32 %val) #0 {
-; CHECK-LABEL: sponentry_cs_dvgpr_calls:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
-; CHECK-NEXT: s_mov_b32 s1, callee at abs32@hi
-; CHECK-NEXT: s_cmp_lg_u32 0, s33
-; CHECK-NEXT: s_mov_b32 s0, callee at abs32@lo
-; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0
-; CHECK-NEXT: s_cselect_b32 s32, 0x1d0, 16
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; CHECK-NEXT: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
-; CHECK-NEXT: s_wait_storecnt 0x0
-; CHECK-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS
-; CHECK-NEXT: s_wait_storecnt 0x0
-; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
-; CHECK-NEXT: s_cmp_lg_u32 0, s0
-; CHECK-NEXT: s_cmovk_i32 s0, 0x1c0
-; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
-; CHECK-NEXT: ; return to shader part epilog
+; DAGISEL-LABEL: sponentry_cs_dvgpr_calls:
+; DAGISEL: ; %bb.0:
+; DAGISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
+; DAGISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
+; DAGISEL-NEXT: s_cmp_lg_u32 0, s33
+; DAGISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
+; DAGISEL-NEXT: s_cmovk_i32 s33, 0x1c0
+; DAGISEL-NEXT: s_cselect_b32 s32, 0x1d0, 16
+; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; DAGISEL-NEXT: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
+; DAGISEL-NEXT: s_wait_storecnt 0x0
+; DAGISEL-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS
+; DAGISEL-NEXT: s_wait_storecnt 0x0
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; DAGISEL-NEXT: s_cmp_lg_u32 0, s0
+; DAGISEL-NEXT: s_cmovk_i32 s0, 0x1c0
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; DAGISEL-NEXT: ; return to shader part epilog
+;
+; GISEL-LABEL: sponentry_cs_dvgpr_calls:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
+; GISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
+; GISEL-NEXT: s_cmp_lg_u32 0, s33
+; GISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
+; GISEL-NEXT: s_cmovk_i32 s33, 0x1c0
+; GISEL-NEXT: s_cselect_b32 s32, 0x1d0, 16
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GISEL-NEXT: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
+; GISEL-NEXT: s_wait_storecnt 0x0
+; GISEL-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS
+; GISEL-NEXT: s_wait_storecnt 0x0
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GISEL-NEXT: s_cmp_lg_u32 0, s0
+; GISEL-NEXT: s_cmovk_i32 s0, 0x1c0
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GISEL-NEXT: ; return to shader part epilog
%local = alloca i32, addrspace(5)
%res = call amdgpu_gfx i32 @callee()
store volatile i32 %res, ptr addrspace(5) %local
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
index 55c87db1fcbf9..11bade44eb909 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=0 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
@@ -66,62 +66,122 @@ define amdgpu_kernel void @workgroup_ids_kernel() {
}
define amdgpu_kernel void @caller() {
-; GFX9-LABEL: caller:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GFX9-NEXT: s_mov_b32 s38, -1
-; GFX9-NEXT: s_mov_b32 s39, 0xe00000
-; GFX9-NEXT: s_add_u32 s36, s36, s11
-; GFX9-NEXT: s_addc_u32 s37, s37, 0
-; GFX9-NEXT: s_mov_b32 s12, s8
-; GFX9-NEXT: s_add_u32 s8, s4, 36
-; GFX9-NEXT: s_addc_u32 s9, s5, 0
-; GFX9-NEXT: s_getpc_b64 s[4:5]
-; GFX9-NEXT: s_add_u32 s4, s4, callee at gotpcrel32@lo+4
-; GFX9-NEXT: s_addc_u32 s5, s5, callee at gotpcrel32@hi+12
-; GFX9-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x0
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
-; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
-; GFX9-NEXT: v_mov_b32_e32 v0, s12
-; GFX9-NEXT: s_mov_b32 s32, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_swappc_b64 s[30:31], s[14:15]
-; GFX9-NEXT: s_endpgm
+; GFX9-SDAG-LABEL: caller:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
+; GFX9-SDAG-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
+; GFX9-SDAG-NEXT: s_mov_b32 s38, -1
+; GFX9-SDAG-NEXT: s_mov_b32 s39, 0xe00000
+; GFX9-SDAG-NEXT: s_add_u32 s36, s36, s11
+; GFX9-SDAG-NEXT: s_addc_u32 s37, s37, 0
+; GFX9-SDAG-NEXT: s_mov_b32 s12, s8
+; GFX9-SDAG-NEXT: s_add_u32 s8, s4, 36
+; GFX9-SDAG-NEXT: s_addc_u32 s9, s5, 0
+; GFX9-SDAG-NEXT: s_getpc_b64 s[4:5]
+; GFX9-SDAG-NEXT: s_add_u32 s4, s4, callee at gotpcrel32@lo+4
+; GFX9-SDAG-NEXT: s_addc_u32 s5, s5, callee at gotpcrel32@hi+12
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x0
+; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-SDAG-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-SDAG-NEXT: v_or3_b32 v31, v0, v1, v2
+; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], s[0:1]
+; GFX9-SDAG-NEXT: s_mov_b64 s[6:7], s[2:3]
+; GFX9-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
+; GFX9-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-SDAG-NEXT: s_mov_b32 s32, 0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: s_swappc_b64 s[30:31], s[14:15]
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: caller:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
+; GFX9-GISEL-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
+; GFX9-GISEL-NEXT: s_mov_b32 s38, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s39, 0xe00000
+; GFX9-GISEL-NEXT: s_add_u32 s36, s36, s11
+; GFX9-GISEL-NEXT: s_addc_u32 s37, s37, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s14, s8
+; GFX9-GISEL-NEXT: s_add_u32 s8, s4, 36
+; GFX9-GISEL-NEXT: s_addc_u32 s9, s5, 0
+; GFX9-GISEL-NEXT: s_mov_b64 s[12:13], s[0:1]
+; GFX9-GISEL-NEXT: s_getpc_b64 s[0:1]
+; GFX9-GISEL-NEXT: s_add_u32 s0, s0, callee at gotpcrel32@lo+4
+; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, callee at gotpcrel32@hi+12
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x0
+; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GFX9-GISEL-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
+; GFX9-GISEL-NEXT: v_or3_b32 v31, v0, v1, v2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s14
+; GFX9-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
+; GFX9-GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
+; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], s[12:13]
+; GFX9-GISEL-NEXT: s_mov_b32 s12, s14
+; GFX9-GISEL-NEXT: s_mov_b32 s32, 0
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX9-GISEL-NEXT: s_endpgm
;
-; GFX9ARCH-LABEL: caller:
-; GFX9ARCH: ; %bb.0:
-; GFX9ARCH-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9ARCH-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GFX9ARCH-NEXT: s_mov_b32 s38, -1
-; GFX9ARCH-NEXT: s_mov_b32 s39, 0xe00000
-; GFX9ARCH-NEXT: s_add_u32 s36, s36, s8
-; GFX9ARCH-NEXT: s_addc_u32 s37, s37, 0
-; GFX9ARCH-NEXT: s_add_u32 s8, s4, 36
-; GFX9ARCH-NEXT: s_addc_u32 s9, s5, 0
-; GFX9ARCH-NEXT: s_getpc_b64 s[4:5]
-; GFX9ARCH-NEXT: s_add_u32 s4, s4, callee at gotpcrel32@lo+4
-; GFX9ARCH-NEXT: s_addc_u32 s5, s5, callee at gotpcrel32@hi+12
-; GFX9ARCH-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x0
-; GFX9ARCH-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX9ARCH-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX9ARCH-NEXT: s_mov_b64 s[10:11], s[6:7]
-; GFX9ARCH-NEXT: v_or3_b32 v31, v0, v1, v2
-; GFX9ARCH-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9ARCH-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX9ARCH-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9ARCH-NEXT: s_mov_b64 s[2:3], s[38:39]
-; GFX9ARCH-NEXT: v_mov_b32_e32 v0, ttmp9
-; GFX9ARCH-NEXT: s_mov_b32 s32, 0
-; GFX9ARCH-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9ARCH-NEXT: s_swappc_b64 s[30:31], s[12:13]
-; GFX9ARCH-NEXT: s_endpgm
+; GFX9ARCH-SDAG-LABEL: caller:
+; GFX9ARCH-SDAG: ; %bb.0:
+; GFX9ARCH-SDAG-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
+; GFX9ARCH-SDAG-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
+; GFX9ARCH-SDAG-NEXT: s_mov_b32 s38, -1
+; GFX9ARCH-SDAG-NEXT: s_mov_b32 s39, 0xe00000
+; GFX9ARCH-SDAG-NEXT: s_add_u32 s36, s36, s8
+; GFX9ARCH-SDAG-NEXT: s_addc_u32 s37, s37, 0
+; GFX9ARCH-SDAG-NEXT: s_add_u32 s8, s4, 36
+; GFX9ARCH-SDAG-NEXT: s_addc_u32 s9, s5, 0
+; GFX9ARCH-SDAG-NEXT: s_getpc_b64 s[4:5]
+; GFX9ARCH-SDAG-NEXT: s_add_u32 s4, s4, callee at gotpcrel32@lo+4
+; GFX9ARCH-SDAG-NEXT: s_addc_u32 s5, s5, callee at gotpcrel32@hi+12
+; GFX9ARCH-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x0
+; GFX9ARCH-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GFX9ARCH-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9ARCH-SDAG-NEXT: v_or3_b32 v31, v0, v1, v2
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[4:5], s[0:1]
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[6:7], s[2:3]
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
+; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
+; GFX9ARCH-SDAG-NEXT: s_mov_b32 s32, 0
+; GFX9ARCH-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9ARCH-SDAG-NEXT: s_swappc_b64 s[30:31], s[12:13]
+; GFX9ARCH-SDAG-NEXT: s_endpgm
+;
+; GFX9ARCH-GISEL-LABEL: caller:
+; GFX9ARCH-GISEL: ; %bb.0:
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s38, -1
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s39, 0xe00000
+; GFX9ARCH-GISEL-NEXT: s_add_u32 s36, s36, s8
+; GFX9ARCH-GISEL-NEXT: s_addc_u32 s37, s37, 0
+; GFX9ARCH-GISEL-NEXT: s_add_u32 s8, s4, 36
+; GFX9ARCH-GISEL-NEXT: s_addc_u32 s9, s5, 0
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[12:13], s[0:1]
+; GFX9ARCH-GISEL-NEXT: s_getpc_b64 s[0:1]
+; GFX9ARCH-GISEL-NEXT: s_add_u32 s0, s0, callee at gotpcrel32@lo+4
+; GFX9ARCH-GISEL-NEXT: s_addc_u32 s1, s1, callee at gotpcrel32@hi+12
+; GFX9ARCH-GISEL-NEXT: s_load_dwordx2 s[14:15], s[0:1], 0x0
+; GFX9ARCH-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9ARCH-GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
+; GFX9ARCH-GISEL-NEXT: v_or3_b32 v31, v0, v1, v2
+; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[4:5], s[12:13]
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s32, 0
+; GFX9ARCH-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9ARCH-GISEL-NEXT: s_swappc_b64 s[30:31], s[14:15]
+; GFX9ARCH-GISEL-NEXT: s_endpgm
;
; GFX12-SDAG-LABEL: caller:
; GFX12-SDAG: ; %bb.0:
@@ -239,5 +299,4 @@ declare void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32>, ptr addrspace(8)
attributes #0 = { nounwind "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX9-GISEL: {{.*}}
-; GFX9-SDAG: {{.*}}
+; GFX9ARCH: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
index 2d0d1d4605202..3776cf033be17 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs < %s | FileCheck -check-prefix=GFX9-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefix=GFX9-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel < %s | FileCheck -check-prefix=GFX9-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefix=GFX12-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel < %s | FileCheck -check-prefix=GFX12-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefix=GFX1250-GISEL %s
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index 5b4ca0bfc1812..4ed52387aa03a 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -354,12 +354,12 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
; SDAG-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; SDAG-GFX9: ; %bb.0:
-; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; SDAG-GFX9-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; VI: ; %bb.0:
@@ -386,22 +386,11 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX11-NEXT: v_and_b32_e64 v1, 0xffff, s0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; GISEL-GFX9: ; %bb.0:
-; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xffff
-; GISEL-GFX9-NEXT: v_and_b32_e32 v1, s4, v1
-; GISEL-GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -609,6 +598,8 @@ attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GISEL-GFX11-FAKE16: {{.*}}
+; GISEL-GFX9: {{.*}}
; GISEL-VI: {{.*}}
; SDAG-GFX11: {{.*}}
+; SDAG-GFX9: {{.*}}
; SDAG-VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index 840896b41398c..0dc06672b395a 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -359,23 +359,23 @@ define float @v_mad_mix_f32_negf16lo_f16lo_f16lo(half %src0, half %src1, half %s
; GFX906-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
-; SDAG-GFX9GEN: ; %bb.0:
-; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SDAG-GFX9GEN-NEXT: v_mad_f32 v0, -v0, v1, v2
-; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-VI-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SDAG-VI-NEXT: v_mad_f32 v0, -v0, v1, v2
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
+; GFX9GEN: ; %bb.0:
+; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX9GEN-NEXT: v_mad_f32 v0, -v0, v1, v2
+; GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; VI-NEXT: v_mad_f32 v0, -v0, v1, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
; SDAG-CI: ; %bb.0:
@@ -386,24 +386,6 @@ define float @v_mad_mix_f32_negf16lo_f16lo_f16lo(half %src0, half %src1, half %s
; SDAG-CI-NEXT: v_mad_f32 v0, -v0, v1, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
-; GISEL-GFX9GEN: ; %bb.0:
-; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v3, -v0
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v2
-; GISEL-GFX9GEN-NEXT: v_mac_f32_e32 v0, v3, v1
-; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-VI-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v3, -v0
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v2
-; GISEL-VI-NEXT: v_mac_f32_e32 v0, v3, v1
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -747,27 +729,27 @@ define float @v_mad_mix_f32_f16lo_f16lo_negabsf32(half %src0, half %src1, float
; inline immediate.
define float @v_mad_mix_f32_f16lo_f16lo_f32imm1(half %src0, half %src1) #0 {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: s_mov_b32 s0, 1.0
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_mov_b32 s0, 1.0
+; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
-; SDAG-GFX900: ; %bb.0:
-; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX900-NEXT: s_mov_b32 s4, 1.0
-; SDAG-GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
-; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 1.0
+; GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
+; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
-; SDAG-GFX906: ; %bb.0:
-; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX906-NEXT: s_mov_b32 s4, 1.0
-; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
-; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+; GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: s_mov_b32 s4, 1.0
+; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
;
; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
; GFX9GEN: ; %bb.0:
@@ -792,28 +774,6 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imm1(half %src0, half %src1) #0 {
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mad_f32 v0, v0, v1, 1.0
; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v2, 1.0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
-; GISEL-GFX900: ; %bb.0:
-; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX900-NEXT: v_mov_b32_e32 v2, 1.0
-; GISEL-GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
-; GISEL-GFX906: ; %bb.0:
-; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX906-NEXT: v_mov_b32_e32 v2, 1.0
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float 1.0)
@@ -821,27 +781,27 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imm1(half %src0, half %src1) #0 {
}
define float @v_mad_mix_f32_f16lo_f16lo_f32imminv2pi(half %src0, half %src1) #0 {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0.15915494
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_mov_b32 s0, 0.15915494
+; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
-; SDAG-GFX900: ; %bb.0:
-; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX900-NEXT: s_mov_b32 s4, 0.15915494
-; SDAG-GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
-; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0.15915494
+; GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
+; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
-; SDAG-GFX906: ; %bb.0:
-; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX906-NEXT: s_mov_b32 s4, 0.15915494
-; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
-; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+; GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: s_mov_b32 s4, 0.15915494
+; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
;
; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
; GFX9GEN: ; %bb.0:
@@ -867,28 +827,6 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imminv2pi(half %src0, half %src1) #0
; SDAG-CI-NEXT: v_madak_f32 v0, v0, v1, 0x3e22f983
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v2, 0.15915494
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
-; GISEL-GFX900: ; %bb.0:
-; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX900-NEXT: v_mov_b32_e32 v2, 0.15915494
-; GISEL-GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
-; GISEL-GFX906: ; %bb.0:
-; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX906-NEXT: v_mov_b32_e32 v2, 0.15915494
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -910,43 +848,43 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imminv2pi(half %src0, half %src1) #0
; f32 1/2pi = 0x3e22f983
define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi(half %src0, half %src1) #0 {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0x3e230000
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_mov_b32 s0, 0x3e230000
+; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; SDAG-GFX900: ; %bb.0:
-; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX900-NEXT: s_mov_b32 s4, 0x3e230000
-; SDAG-GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
-; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x3e230000
+; GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
+; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; SDAG-GFX906: ; %bb.0:
-; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX906-NEXT: s_mov_b32 s4, 0x3e230000
-; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
-; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+; GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: s_mov_b32 s4, 0x3e230000
+; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; SDAG-GFX9GEN: ; %bb.0:
-; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX9GEN-NEXT: v_madak_f32 v0, v0, v1, 0x3e230000
-; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-VI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_madak_f32 v0, v0, v1, 0x3e230000
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; GFX9GEN: ; %bb.0:
+; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9GEN-NEXT: v_madak_f32 v0, v0, v1, 0x3e230000
+; GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_madak_f32 v0, v0, v1, 0x3e230000
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
; SDAG-CI: ; %bb.0:
@@ -956,46 +894,6 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi(half %src0, half %src1)
; SDAG-CI-NEXT: v_madak_f32 v0, v0, v1, 0x3e230000
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v2, 0x3e230000
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; GISEL-GFX900: ; %bb.0:
-; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX900-NEXT: v_mov_b32_e32 v2, 0x3e230000
-; GISEL-GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; GISEL-GFX906: ; %bb.0:
-; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX906-NEXT: v_mov_b32_e32 v2, 0x3e230000
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; GISEL-GFX9GEN: ; %bb.0:
-; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX9GEN-NEXT: v_mov_b32_e32 v0, 0x3e230000
-; GISEL-GFX9GEN-NEXT: v_mac_f32_e32 v0, v2, v1
-; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-VI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x3e230000
-; GISEL-VI-NEXT: v_mac_f32_e32 v0, v2, v1
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1013,43 +911,43 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi(half %src0, half %src1)
define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imm63(half %src0, half %src1) #0 {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0x367c0000
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_mov_b32 s0, 0x367c0000
+; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; SDAG-GFX900: ; %bb.0:
-; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX900-NEXT: s_mov_b32 s4, 0x367c0000
-; SDAG-GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
-; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x367c0000
+; GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
+; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; SDAG-GFX906: ; %bb.0:
-; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX906-NEXT: s_mov_b32 s4, 0x367c0000
-; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
-; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+; GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: s_mov_b32 s4, 0x367c0000
+; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, s4 op_sel_hi:[1,1,0]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; SDAG-GFX9GEN: ; %bb.0:
-; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX9GEN-NEXT: v_madak_f32 v0, v0, v1, 0x367c0000
-; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-VI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_madak_f32 v0, v0, v1, 0x367c0000
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; GFX9GEN: ; %bb.0:
+; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9GEN-NEXT: v_madak_f32 v0, v0, v1, 0x367c0000
+; GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_madak_f32 v0, v0, v1, 0x367c0000
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
; SDAG-CI: ; %bb.0:
@@ -1059,46 +957,6 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imm63(half %src0, half %src1) #0 {
; SDAG-CI-NEXT: v_madak_f32 v0, v0, v1, 0x367c0000
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v2, 0x367c0000
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; GISEL-GFX900: ; %bb.0:
-; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX900-NEXT: v_mov_b32_e32 v2, 0x367c0000
-; GISEL-GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; GISEL-GFX906: ; %bb.0:
-; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX906-NEXT: v_mov_b32_e32 v2, 0x367c0000
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; GISEL-GFX9GEN: ; %bb.0:
-; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX9GEN-NEXT: v_mov_b32_e32 v0, 0x367c0000
-; GISEL-GFX9GEN-NEXT: v_mac_f32_e32 v0, v2, v1
-; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-VI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x367c0000
-; GISEL-VI-NEXT: v_mac_f32_e32 v0, v2, v1
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1905,23 +1763,23 @@ define float @v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo(i32 %src0.arg, half %src1
; GFX906-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
-; SDAG-GFX9GEN: ; %bb.0:
-; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SDAG-GFX9GEN-NEXT: v_mad_f32 v0, -v0, v1, v2
-; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-VI-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SDAG-VI-NEXT: v_mad_f32 v0, -v0, v1, v2
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
+; GFX9GEN: ; %bb.0:
+; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX9GEN-NEXT: v_mad_f32 v0, -v0, v1, v2
+; GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; VI-NEXT: v_mad_f32 v0, -v0, v1, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
; SDAG-CI: ; %bb.0:
@@ -1932,24 +1790,6 @@ define float @v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo(i32 %src0.arg, half %src1
; SDAG-CI-NEXT: v_mad_f32 v0, -v0, v1, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
-; GISEL-GFX9GEN: ; %bb.0:
-; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v3, -v0
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v2
-; GISEL-GFX9GEN-NEXT: v_mac_f32_e32 v0, v3, v1
-; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-VI-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v3, -v0
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v2
-; GISEL-VI-NEXT: v_mac_f32_e32 v0, v3, v1
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2581,41 +2421,41 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_add(<2 x half> %src0, <2 x half>
}
define float @v_mad_mix_f32_negf16lo_add_f16lo(half %src0, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX900-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; SDAG-GFX900: ; %bb.0:
-; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
-; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX906-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; SDAG-GFX906: ; %bb.0:
-; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+; GFX906-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; SDAG-GFX9GEN: ; %bb.0:
-; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0
-; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-VI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; GFX9GEN: ; %bb.0:
+; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
; SDAG-CI: ; %bb.0:
@@ -2625,42 +2465,6 @@ define float @v_mad_mix_f32_negf16lo_add_f16lo(half %src0, half %src1) {
; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX900-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; GISEL-GFX900: ; %bb.0:
-; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX906-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; GISEL-GFX906: ; %bb.0:
-; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1]
-; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; GISEL-GFX9GEN: ; %bb.0:
-; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-VI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3116,41 +2920,41 @@ define float @v_mad_mix_clamp_f32_f16hi_add_f16hi(<2 x half> %src0, <2 x half> %
}
define float @v_mad_mix_f32_negprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; SDAG-GFX900: ; %bb.0:
-; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
-; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX906-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; SDAG-GFX906: ; %bb.0:
-; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+; GFX906-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; SDAG-GFX9GEN: ; %bb.0:
-; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0
-; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-VI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; GFX9GEN: ; %bb.0:
+; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
; SDAG-CI: ; %bb.0:
@@ -3160,42 +2964,6 @@ define float @v_mad_mix_f32_negprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1)
; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; GISEL-GFX900: ; %bb.0:
-; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX906-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; GISEL-GFX906: ; %bb.0:
-; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1]
-; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; GISEL-GFX9GEN: ; %bb.0:
-; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-VI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3266,41 +3034,41 @@ define float @v_mad_mix_f32_absprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_negabsprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX900-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; SDAG-GFX900: ; %bb.0:
-; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX900-NEXT: v_cvt_f32_f16_e64 v0, |v0|
-; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
-; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX906-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; SDAG-GFX906: ; %bb.0:
-; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+; GFX906-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; SDAG-GFX9GEN: ; %bb.0:
-; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, |v0|
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0
-; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-VI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; GFX9GEN-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; GFX9GEN: ; %bb.0:
+; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
; SDAG-CI: ; %bb.0:
@@ -3310,42 +3078,6 @@ define float @v_mad_mix_f32_negabsprecvtf16lo_add_f16lo(i32 %src0.arg, half %src
; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX900-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; GISEL-GFX900: ; %bb.0:
-; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
-; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX906-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; GISEL-GFX906: ; %bb.0:
-; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel_hi:[1,1,1]
-; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; GISEL-GFX9GEN: ; %bb.0:
-; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-VI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3496,11 +3228,11 @@ define float @v_mad_mix_f32_precvtabsf16hi_add_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
; GFX900: ; %bb.0:
@@ -3510,11 +3242,11 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %
; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX906-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
-; SDAG-GFX906: ; %bb.0:
-; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+; GFX906-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
;
; GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
; GFX9GEN: ; %bb.0:
@@ -3540,18 +3272,6 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX906-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
-; GISEL-GFX906: ; %bb.0:
-; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%fneg = fneg <2 x half> %src0.arg.bc
%src0 = extractelement <2 x half> %fneg, i32 1
@@ -3616,11 +3336,11 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
; GFX900: ; %bb.0:
@@ -3630,11 +3350,11 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, ha
; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX906-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
-; SDAG-GFX906: ; %bb.0:
-; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+; GFX906-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
;
; GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
; GFX9GEN: ; %bb.0:
@@ -3660,18 +3380,6 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, ha
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX906-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
-; GISEL-GFX906: ; %bb.0:
-; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
%fneg.fabs = fneg <2 x half> %fabs
@@ -3991,13 +3699,13 @@ define float @v_mad_mix_f32_negf16lo_mul_f16lo(half %src0, half %src1) {
; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX900-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
-; SDAG-GFX900: ; %bb.0:
-; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SDAG-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
-; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX906-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
; GFX906: ; %bb.0:
@@ -4005,21 +3713,21 @@ define float @v_mad_mix_f32_negf16lo_mul_f16lo(half %src0, half %src1) {
; GFX906-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
-; SDAG-GFX9GEN: ; %bb.0:
-; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1
-; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-VI-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SDAG-VI-NEXT: v_mul_f32_e32 v0, v0, v1
-; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+; GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
+; GFX9GEN: ; %bb.0:
+; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-CI-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
; SDAG-CI: ; %bb.0:
@@ -4029,30 +3737,6 @@ define float @v_mad_mix_f32_negf16lo_mul_f16lo(half %src0, half %src1) {
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX900-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
-; GISEL-GFX900: ; %bb.0:
-; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
-; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
-; GISEL-GFX9GEN: ; %bb.0:
-; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1
-; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-VI-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_mul_f32_e32 v0, v0, v1
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5202,3 +4886,7 @@ attributes #1 = { nounwind denormal_fpenv(float: ieee|ieee) }
attributes #2 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GISEL-GFX1100-FAKE16: {{.*}}
+; GISEL-GFX9GEN: {{.*}}
+; GISEL-VI: {{.*}}
+; SDAG-GFX9GEN: {{.*}}
+; SDAG-VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
index 757f7f3ce9dae..313cc17f72c05 100644
--- a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
@@ -253,24 +253,23 @@ define amdgpu_ps void @s_test_minmax_f16(half inreg %a, half inreg %b, half inre
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: s_maximum_f16 s0, s0, s1
; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GISEL-TRUE16-NEXT: s_mov_b32 s6, s3
-; GFX12-GISEL-TRUE16-NEXT: s_mov_b32 s7, s4
+; GFX12-GISEL-TRUE16-NEXT: s_mov_b32 s5, s4
+; GFX12-GISEL-TRUE16-NEXT: s_mov_b32 s4, s3
; GFX12-GISEL-TRUE16-NEXT: s_minimum_f16 s0, s0, s2
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
;
; GFX12-GISEL-FAKE16-LABEL: s_test_minmax_f16:
; GFX12-GISEL-FAKE16: ; %bb.0:
; GFX12-GISEL-FAKE16-NEXT: s_maximum_f16 s0, s0, s1
-; GFX12-GISEL-FAKE16-NEXT: s_mov_b32 s6, s3
-; GFX12-GISEL-FAKE16-NEXT: s_mov_b32 s7, s4
-; GFX12-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-GISEL-FAKE16-NEXT: s_mov_b32 s5, s4
+; GFX12-GISEL-FAKE16-NEXT: s_mov_b32 s4, s3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX12-GISEL-FAKE16-NEXT: s_minimum_f16 s0, s0, s2
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GFX12-GISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX12-GISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[4:5]
; GFX12-GISEL-FAKE16-NEXT: s_endpgm
%smax = call half @llvm.maximum.f16(half %a, half %b)
%sminmax = call half @llvm.minimum.f16(half %smax, half %c)
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index 25bd9479ae722..bda039e3f9a0c 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -1073,24 +1073,21 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; GISEL-GFX1170-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; GISEL-GFX1170-TRUE16: ; %bb.0:
-; GISEL-GFX1170-TRUE16-NEXT: s_max_f16 s0, s0, s1
+; GISEL-GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GISEL-GFX1170-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX1170-TRUE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX1170-TRUE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX1170-TRUE16-NEXT: s_min_f16 s0, s0, s2
-; GISEL-GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GISEL-GFX1170-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GISEL-GFX1170-TRUE16-NEXT: s_mov_b32 s5, s4
+; GISEL-GFX1170-TRUE16-NEXT: s_mov_b32 s4, s3
+; GISEL-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
+; GISEL-GFX1170-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
; GISEL-GFX1170-TRUE16-NEXT: s_endpgm
;
; GISEL-GFX1170-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
; GISEL-GFX1170-FAKE16: ; %bb.0:
-; GISEL-GFX1170-FAKE16-NEXT: s_max_f16 s0, s0, s1
-; GISEL-GFX1170-FAKE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX1170-FAKE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX1170-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX1170-FAKE16-NEXT: s_min_f16 s0, s0, s2
-; GISEL-GFX1170-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX1170-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GISEL-GFX1170-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
+; GISEL-GFX1170-FAKE16-NEXT: s_mov_b32 s5, s4
+; GISEL-GFX1170-FAKE16-NEXT: s_mov_b32 s4, s3
+; GISEL-GFX1170-FAKE16-NEXT: v_maxmin_num_f16 v0, s0, s1, v0
+; GISEL-GFX1170-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
; GISEL-GFX1170-FAKE16-NEXT: s_endpgm
;
; SDAG-GFX12-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
@@ -1114,24 +1111,21 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; GISEL-GFX12-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; GISEL-GFX12-TRUE16: ; %bb.0:
-; GISEL-GFX12-TRUE16-NEXT: s_max_num_f16 s0, s0, s1
+; GISEL-GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GISEL-GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX12-TRUE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX12-TRUE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX12-TRUE16-NEXT: s_min_num_f16 s0, s0, s2
-; GISEL-GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GISEL-GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GISEL-GFX12-TRUE16-NEXT: s_mov_b32 s5, s4
+; GISEL-GFX12-TRUE16-NEXT: s_mov_b32 s4, s3
+; GISEL-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
+; GISEL-GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
; GISEL-GFX12-TRUE16-NEXT: s_endpgm
;
; GISEL-GFX12-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
; GISEL-GFX12-FAKE16: ; %bb.0:
-; GISEL-GFX12-FAKE16-NEXT: s_max_num_f16 s0, s0, s1
-; GISEL-GFX12-FAKE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX12-FAKE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX12-FAKE16-NEXT: s_min_num_f16 s0, s0, s2
-; GISEL-GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX12-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GISEL-GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
+; GISEL-GFX12-FAKE16-NEXT: s_mov_b32 s5, s4
+; GISEL-GFX12-FAKE16-NEXT: s_mov_b32 s4, s3
+; GISEL-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, s0, s1, v0
+; GISEL-GFX12-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
; GISEL-GFX12-FAKE16-NEXT: s_endpgm
;
; SDAG-GFX1250-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
@@ -1158,25 +1152,22 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
; GISEL-GFX1250-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; GISEL-GFX1250-TRUE16: ; %bb.0:
; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-TRUE16-NEXT: s_max_num_f16 s0, s0, s1
+; GISEL-GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GISEL-GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX1250-TRUE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX1250-TRUE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX1250-TRUE16-NEXT: s_min_num_f16 s0, s0, s2
-; GISEL-GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GISEL-GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GISEL-GFX1250-TRUE16-NEXT: s_mov_b32 s5, s4
+; GISEL-GFX1250-TRUE16-NEXT: s_mov_b32 s4, s3
+; GISEL-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
+; GISEL-GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
; GISEL-GFX1250-TRUE16-NEXT: s_endpgm
;
; GISEL-GFX1250-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
; GISEL-GFX1250-FAKE16: ; %bb.0:
; GISEL-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-FAKE16-NEXT: s_max_num_f16 s0, s0, s1
-; GISEL-GFX1250-FAKE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX1250-FAKE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX1250-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX1250-FAKE16-NEXT: s_min_num_f16 s0, s0, s2
-; GISEL-GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX1250-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GISEL-GFX1250-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
+; GISEL-GFX1250-FAKE16-NEXT: s_mov_b32 s5, s4
+; GISEL-GFX1250-FAKE16-NEXT: s_mov_b32 s4, s3
+; GISEL-GFX1250-FAKE16-NEXT: v_maxmin_num_f16 v0, s0, s1, v0
+; GISEL-GFX1250-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
; GISEL-GFX1250-FAKE16-NEXT: s_endpgm
%smax = call half @llvm.maxnum.f16(half %a, half %b)
%sminmax = call half @llvm.minnum.f16(half %smax, half %c)
@@ -1215,8 +1206,8 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX11-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
; GISEL-GFX11-FAKE16: ; %bb.0:
; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
+; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
; GISEL-GFX11-FAKE16-NEXT: v_maxmin_f16 v0, v0, v1, v2
; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1251,8 +1242,8 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1170-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
; GISEL-GFX1170-FAKE16: ; %bb.0:
; GISEL-GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX1170-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; GISEL-GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1303,8 +1294,8 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; GISEL-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1343,8 +1334,8 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1250-FAKE16: ; %bb.0:
; GISEL-GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX1250-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; GISEL-GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
@@ -1473,8 +1464,8 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX11-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; GISEL-GFX11-FAKE16: ; %bb.0:
; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
+; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
; GISEL-GFX11-FAKE16-NEXT: v_minmax_f16 v0, v0, v1, v2
; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1509,8 +1500,8 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1170-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; GISEL-GFX1170-FAKE16: ; %bb.0:
; GISEL-GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX1170-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; GISEL-GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1561,8 +1552,8 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; GISEL-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1601,8 +1592,8 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1250-FAKE16: ; %bb.0:
; GISEL-GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX1250-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; GISEL-GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
index bb2db9f456e6e..8adfed45e2514 100644
--- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
+++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX9 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX10 %s
; Test case looks at the allocated offset of @used_by_both. It's at zero when
; allocated by itself, but at 8 when allocated in combination with the double.
@@ -147,28 +147,32 @@ define amdgpu_kernel void @withcall() {
; G_GFX9-NEXT: s_mov_b32 s23, 0xe00000
; G_GFX9-NEXT: s_add_u32 s20, s20, s11
; G_GFX9-NEXT: s_addc_u32 s21, s21, 0
-; G_GFX9-NEXT: s_mov_b32 s12, s8
+; G_GFX9-NEXT: s_mov_b32 s16, s8
; G_GFX9-NEXT: s_add_u32 s8, s4, 36
-; G_GFX9-NEXT: s_mov_b32 s13, s9
+; G_GFX9-NEXT: s_mov_b32 s15, s9
; G_GFX9-NEXT: s_addc_u32 s9, s5, 0
-; G_GFX9-NEXT: s_getpc_b64 s[4:5]
-; G_GFX9-NEXT: s_add_u32 s4, s4, nonkernel at gotpcrel32@lo+4
-; G_GFX9-NEXT: s_addc_u32 s5, s5, nonkernel at gotpcrel32@hi+12
-; G_GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; G_GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; G_GFX9-NEXT: s_mov_b64 s[12:13], s[0:1]
+; G_GFX9-NEXT: s_getpc_b64 s[0:1]
+; G_GFX9-NEXT: s_add_u32 s0, s0, nonkernel at gotpcrel32@lo+4
+; G_GFX9-NEXT: s_addc_u32 s1, s1, nonkernel at gotpcrel32@hi+12
+; G_GFX9-NEXT: s_load_dwordx2 s[18:19], s[0:1], 0x0
; G_GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; G_GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; G_GFX9-NEXT: s_mov_b32 s14, s10
; G_GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; G_GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; G_GFX9-NEXT: v_mov_b32_e32 v3, 0
+; G_GFX9-NEXT: v_mov_b32_e32 v4, 8
; G_GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
-; G_GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
-; G_GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; G_GFX9-NEXT: s_mov_b64 s[0:1], s[20:21]
; G_GFX9-NEXT: s_mov_b64 s[2:3], s[22:23]
+; G_GFX9-NEXT: s_mov_b64 s[4:5], s[12:13]
+; G_GFX9-NEXT: s_mov_b32 s12, s16
+; G_GFX9-NEXT: s_mov_b32 s13, s15
; G_GFX9-NEXT: s_mov_b32 s32, 0
-; G_GFX9-NEXT: ds_write_b32 v3, v3 offset:8
+; G_GFX9-NEXT: ds_write_b32 v4, v3
; G_GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; G_GFX9-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; G_GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; G_GFX9-NEXT: s_endpgm
;
; G_GFX10-LABEL: withcall:
@@ -179,28 +183,32 @@ define amdgpu_kernel void @withcall() {
; G_GFX10-NEXT: s_mov_b32 s23, 0x31c16000
; G_GFX10-NEXT: s_add_u32 s20, s20, s11
; G_GFX10-NEXT: s_addc_u32 s21, s21, 0
-; G_GFX10-NEXT: s_mov_b32 s12, s8
+; G_GFX10-NEXT: s_mov_b32 s16, s8
; G_GFX10-NEXT: s_add_u32 s8, s4, 36
-; G_GFX10-NEXT: s_mov_b32 s13, s9
+; G_GFX10-NEXT: s_mov_b32 s15, s9
; G_GFX10-NEXT: s_addc_u32 s9, s5, 0
-; G_GFX10-NEXT: s_getpc_b64 s[4:5]
-; G_GFX10-NEXT: s_add_u32 s4, s4, nonkernel at gotpcrel32@lo+4
-; G_GFX10-NEXT: s_addc_u32 s5, s5, nonkernel at gotpcrel32@hi+12
-; G_GFX10-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; G_GFX10-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
+; G_GFX10-NEXT: s_mov_b64 s[12:13], s[0:1]
+; G_GFX10-NEXT: s_getpc_b64 s[0:1]
+; G_GFX10-NEXT: s_add_u32 s0, s0, nonkernel at gotpcrel32@lo+4
+; G_GFX10-NEXT: s_addc_u32 s1, s1, nonkernel at gotpcrel32@hi+12
; G_GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; G_GFX10-NEXT: s_load_dwordx2 s[18:19], s[0:1], 0x0
+; G_GFX10-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; G_GFX10-NEXT: v_mov_b32_e32 v3, 0
+; G_GFX10-NEXT: v_mov_b32_e32 v4, 8
; G_GFX10-NEXT: s_mov_b32 s14, s10
; G_GFX10-NEXT: s_mov_b64 s[10:11], s[6:7]
-; G_GFX10-NEXT: s_mov_b64 s[4:5], s[0:1]
; G_GFX10-NEXT: v_or3_b32 v31, v0, v1, v2
; G_GFX10-NEXT: s_mov_b64 s[6:7], s[2:3]
; G_GFX10-NEXT: s_mov_b64 s[0:1], s[20:21]
; G_GFX10-NEXT: s_mov_b64 s[2:3], s[22:23]
+; G_GFX10-NEXT: s_mov_b64 s[4:5], s[12:13]
+; G_GFX10-NEXT: s_mov_b32 s12, s16
+; G_GFX10-NEXT: s_mov_b32 s13, s15
; G_GFX10-NEXT: s_mov_b32 s32, 0
-; G_GFX10-NEXT: ds_write_b32 v3, v3 offset:8
+; G_GFX10-NEXT: ds_write_b32 v4, v3
; G_GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; G_GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; G_GFX10-NEXT: s_swappc_b64 s[30:31], s[18:19]
; G_GFX10-NEXT: s_endpgm
store i32 0, ptr addrspace(3) @used_by_both
call void @nonkernel()
diff --git a/llvm/test/CodeGen/AMDGPU/roundeven.ll b/llvm/test/CodeGen/AMDGPU/roundeven.ll
index 203b64e1a647a..697f9b7524cb0 100644
--- a/llvm/test/CodeGen/AMDGPU/roundeven.ll
+++ b/llvm/test/CodeGen/AMDGPU/roundeven.ll
@@ -4,7 +4,7 @@
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SDAG_GFX6 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefix=SDAG_GFX7 %s
diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
index 09c7434a6b835..f238ea361ba41 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 < %s | FileCheck -check-prefixes=CHECK,GFX1150 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX1150 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefixes=CHECK,GFX1150 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=CHECK,GFX12 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefixes=CHECK,GFX12 %s
define amdgpu_vs float @fadd_f32(float inreg %a, float inreg %b) {
; CHECK-LABEL: fadd_f32:
@@ -44,6 +44,7 @@ define amdgpu_vs float @fmin_f32(float inreg %a, float inreg %b) {
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-NEXT: v_mov_b32_e32 v0, s0
; GFX1150-NEXT: ; return to shader part epilog
+;
; GFX12-LABEL: fmin_f32:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_min_num_f32 s0, s0, s1
@@ -61,6 +62,7 @@ define amdgpu_vs float @fmax_f32(float inreg %a, float inreg %b) {
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-NEXT: v_mov_b32_e32 v0, s0
; GFX1150-NEXT: ; return to shader part epilog
+;
; GFX12-LABEL: fmax_f32:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_max_num_f32 s0, s0, s1
@@ -111,6 +113,7 @@ define amdgpu_vs half @fmin_f16(half inreg %a, half inreg %b) {
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-NEXT: v_mov_b32_e32 v0, s0
; GFX1150-NEXT: ; return to shader part epilog
+;
; GFX12-LABEL: fmin_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_min_num_f16 s0, s0, s1
@@ -128,6 +131,7 @@ define amdgpu_vs half @fmax_f16(half inreg %a, half inreg %b) {
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-NEXT: v_mov_b32_e32 v0, s0
; GFX1150-NEXT: ; return to shader part epilog
+;
; GFX12-LABEL: fmax_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_max_num_f16 s0, s0, s1
@@ -219,6 +223,7 @@ define amdgpu_ps float @_amdgpu_ps_main() {
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-NEXT: v_mov_b32_e32 v0, s0
; GFX1150-NEXT: ; return to shader part epilog
+;
; GFX12-LABEL: _amdgpu_ps_main:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_mov_b32 s0, 0
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
index b9bcad4016495..a92fae83c8690 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
@@ -4,13 +4,13 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefixes=VI,VI-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefixes=VI,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; Test that add/sub with a constant is swapped to sub/add with negated
; constant to minimize code size.
diff --git a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
index d35857c6c9d08..ce9b5861a8e45 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
@@ -18,23 +18,23 @@
; }
define half @test_ldexp_f16_i32(ptr addrspace(1) %out, half %a, i32 %b) #0 {
-; GFX8-SDAG-LABEL: test_ldexp_f16_i32:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff
-; GFX8-SDAG-NEXT: v_med3_i32 v0, v3, s4, v0
-; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_ldexp_f16_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_movk_i32 s4, 0x8000
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fff
+; GFX8-NEXT: v_med3_i32 v0, v3, s4, v0
+; GFX8-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_ldexp_f16_i32:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff
-; GFX9-SDAG-NEXT: v_med3_i32 v0, v3, s4, v0
-; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_ldexp_f16_i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x8000
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fff
+; GFX9-NEXT: v_med3_i32 v0, v3, s4, v0
+; GFX9-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_ldexp_f16_i32:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -54,24 +54,6 @@ define half @test_ldexp_f16_i32(ptr addrspace(1) %out, half %a, i32 %b) #0 {
; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-GISEL-LABEL: test_ldexp_f16_i32:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 0xffff8000
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 0x7fff
-; GFX8-GISEL-NEXT: v_med3_i32 v0, v3, v0, v1
-; GFX8-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_ldexp_f16_i32:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0xffff8000
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7fff
-; GFX9-GISEL-NEXT: v_med3_i32 v0, v3, v0, v1
-; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-GISEL-TRUE16-LABEL: test_ldexp_f16_i32:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -84,9 +66,9 @@ define half @test_ldexp_f16_i32(ptr addrspace(1) %out, half %a, i32 %b) #0 {
; GFX11-GISEL-FAKE16-LABEL: test_ldexp_f16_i32:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7fff
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v3, v0
+; GFX11-GISEL-FAKE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, v3, s0, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.experimental.constrained.ldexp.f16.i32(half %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -455,3 +437,7 @@ attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessib
; GFX11: {{.*}}
; GFX11-GISEL: {{.*}}
; GFX11-SDAG: {{.*}}
+; GFX8-GISEL: {{.*}}
+; GFX8-SDAG: {{.*}}
+; GFX9-GISEL: {{.*}}
+; GFX9-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
index 7ec47be231ccf..52b3398c5fa81 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
@@ -9,11 +9,11 @@
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define i8 @test_vector_reduce_add_v2i8(<2 x i8> %v) {
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
index c8bccc5aa9a99..af05ba16ab7e0 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
@@ -9,15 +9,15 @@
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
index 7dcae2c9fb59a..746b93daaf5b5 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
@@ -9,15 +9,15 @@
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index 88799270dd09e..64ee3043f9290 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -7,11 +7,11 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
diff --git a/llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll b/llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
index 04b72226e93c6..f7324a36523eb 100644
--- a/llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1200 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX1200 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=1 < %s | FileCheck -check-prefixes=GFX1200 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
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