[llvm-branch-commits] [llvm] [AArch64] NFCI: Simplify LowerVectorFP_TO_INT_SAT (part 2) (PR #207199)

[Gaëtan Bossu via llvm-branch-commits]

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@@ -5205,55 +5205,75 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
     return SDValue();
 
   EVT SrcElementVT = SrcVT.getVectorElementType();
+  if (SrcElementVT != MVT::f64 && SrcElementVT != MVT::f32 &&
+      SrcElementVT != MVT::f16 && SrcElementVT != MVT::bf16)
+    return SDValue();
+
+  // Returns true if the operation can be matched by an isel pattern directly.
+  auto CanHandleNatively = [&DstVT, &SatWidth](EVT SrcVT) -> bool {
+    return SrcVT.getScalarSizeInBits() == DstVT.getScalarSizeInBits() &&
+           SrcVT.getScalarSizeInBits() == SatWidth;
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gbossu wrote:

Nit: I wonder if it's worth asserting that `SrcVT.getSizeInBits() <= 128`? I assume we are expecting legal types at this stage.

https://github.com/llvm/llvm-project/pull/207199