[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Switch RegBankLegalize lowering to extended LLTs (PR #208270)

[Chinmay Deshpande via llvm-branch-commits]

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@@ -1444,17 +1448,18 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
     MachineInstrBuilder Hi;
     switch (MI.getOpcode()) {
     case AMDGPU::G_ZEXT: {
-      Hi = B.buildConstant({RB, S32}, 0);
+      Hi = B.buildConstant({RB, LLT::integer(32)}, 0);
       break;
     }
     case AMDGPU::G_SEXT: {
       // Replicate sign bit from 32-bit extended part.
-      auto ShiftAmt = B.buildConstant({RB, S32}, 31);
-      Hi = B.buildAShr({RB, S32}, MI.getOperand(1).getReg(), ShiftAmt);
+      auto ShiftAmt = B.buildConstant({RB, LLT::integer(32)}, 31);
+      Hi = B.buildAShr({RB, MRI.getType(MI.getOperand(1).getReg())},
+                       MI.getOperand(1).getReg(), ShiftAmt);
       break;
     }
     case AMDGPU::G_ANYEXT: {
-      Hi = B.buildUndef({RB, S32});
+      Hi = B.buildUndef({RB, LLT::integer(32)});
----------------
chinmaydd wrote:

```suggestion
      Hi = B.buildUndef({RB, I32});
```

https://github.com/llvm/llvm-project/pull/208270