[llvm-branch-commits] [llvm] [LoongArch] Add DAG combines for vector widening extends (PR #207316)

[via llvm-branch-commits]

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@@ -6463,7 +6466,7 @@ static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
   if (!LHS.hasOneUse())
     return SDValue();
 
-  SDValue Vec = matchLowHalfOf128BitLanes(LHS.getOperand(0));
+  SDValue Vec = matchHalfOf128BitLanes(LHS.getOperand(0), true);
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wangleiat wrote:

Please add a parameter name for the boolean literal, e.g. /*isLow=*/true.

https://github.com/llvm/llvm-project/pull/207316