[llvm-branch-commits] [llvm] [AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (PR #207201)
Sander de Smalen via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Jul 2 07:53:53 PDT 2026
https://github.com/sdesmalen-arm created https://github.com/llvm/llvm-project/pull/207201
Fixed-length lowering will be added in a separate PR.
>From 4fca98968059bce8b0cb3a75c312b2be399fd63c Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Tue, 23 Jun 2026 14:38:52 +0000
Subject: [PATCH] [AArch64] Add SVE lowering for FP_TO_[US]INT_SAT.
Fixed-length lowering will be added in a separate PR.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 27 +-
.../CodeGen/AArch64/sve-fixed-vector-lrint.ll | 289 +--
.../AArch64/sve-fptosi-sat-scalable-types.ll | 144 ++
llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll | 446 ++---
llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll | 356 +---
llvm/test/CodeGen/AArch64/sve-llrint.ll | 1599 ++++-------------
llvm/test/CodeGen/AArch64/sve-lrint.ll | 1599 ++++-------------
7 files changed, 1081 insertions(+), 3379 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/sve-fptosi-sat-scalable-types.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 4e61612aca96a..46effe123d1dc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1671,6 +1671,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SINT_TO_FP, VT, Custom);
setOperationAction(ISD::FP_TO_UINT, VT, Custom);
setOperationAction(ISD::FP_TO_SINT, VT, Custom);
+ setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
+ setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
setOperationAction(ISD::MLOAD, VT, Custom);
setOperationAction(ISD::MSTORE, VT, Legal);
setOperationAction(ISD::MUL, VT, Custom);
@@ -5178,17 +5180,14 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
assert(SatWidth <= DstElementWidth &&
"Saturation width cannot exceed result width");
- // TODO: Consider lowering to SVE operations, as in LowerVectorFP_TO_INT.
- // Currently, the `llvm.fpto[su]i.sat.*` intrinsics don't accept scalable
- // types, so this is hard to reach.
- if (DstVT.isScalableVector())
- return SDValue();
-
EVT SrcElementVT = SrcVT.getVectorElementType();
if (SrcElementVT != MVT::f64 && SrcElementVT != MVT::f32 &&
SrcElementVT != MVT::f16 && SrcElementVT != MVT::bf16)
return SDValue();
+ if (SDValue Res = tryLowerFPToIntToSVE(Op, DAG))
+ return Res;
+
// Returns true if the operation can be matched by an isel pattern directly.
auto CanHandleNatively = [&DstVT, &SatWidth](EVT SrcVT) -> bool {
return SrcVT.getScalarSizeInBits() == DstVT.getScalarSizeInBits() &&
@@ -5201,7 +5200,8 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
(SrcVT.getScalarSizeInBits() < SatWidth ||
// NEON has no vector MIN/MAX for i64, so it's simpler to scalarize
// (at least until sqxtn is selected).
- SrcVT.getVectorElementType() == MVT::f64);
+ (SrcVT.getVectorElementType() == MVT::f64 &&
+ !SrcVT.isScalableVector()));
};
// Try to promote the operation to a wider type if SrcVT < DstVT,
@@ -5210,7 +5210,8 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
switch (SrcVT.getVectorElementType().getSimpleVT().SimpleTy) {
case MVT::f16:
case MVT::bf16:
- if (DstVT.getScalarSizeInBits() == 32 || !Subtarget->hasFullFP16()) {
+ if (SrcVT.getVectorElementCount() != ElementCount::getScalable(2) &&
+ (DstVT.getScalarSizeInBits() == 32 || !Subtarget->hasFullFP16())) {
PromVT = MVT::getVectorVT(MVT::f32, SrcVT.getVectorElementCount());
break;
}
@@ -33939,10 +33940,20 @@ SDValue AArch64TargetLowering::tryLowerFPToIntToSVE(SDValue Op,
unsigned NewOpcode;
switch (Op.getOpcode()) {
+ case ISD::FP_TO_UINT_SAT:
+ // Only saturation to the destination type is natively supported.
+ if (VT.getVectorElementType() != cast<VTSDNode>(Op.getOperand(1))->getVT())
+ return SDValue();
+ [[fallthrough]];
case ISD::FP_TO_UINT:
case ISD::STRICT_FP_TO_UINT:
NewOpcode = AArch64ISD::FCVTZU_MERGE_PASSTHRU;
break;
+ case ISD::FP_TO_SINT_SAT:
+ // Only saturation to the destination type is natively supported.
+ if (VT.getVectorElementType() != cast<VTSDNode>(Op.getOperand(1))->getVT())
+ return SDValue();
+ [[fallthrough]];
case ISD::FP_TO_SINT:
case ISD::STRICT_FP_TO_SINT:
NewOpcode = AArch64ISD::FCVTZS_MERGE_PASSTHRU;
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll b/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
index 9b6aab6d33db7..c12e3595cf798 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
@@ -1018,19 +1018,10 @@ define <4 x iXLen> @lrint_v4f64(<4 x double> %x) nounwind {
; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-i32-NEXT: ptrue p0.d, vl4
-; CHECK-i32-NEXT: movprfx z1, z0
-; CHECK-i32-NEXT: frintx z1.d, p0/m, z0.d
-; CHECK-i32-NEXT: mov z0.d, z1.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d1
-; CHECK-i32-NEXT: mov z2.d, z1.d[2]
-; CHECK-i32-NEXT: mov z1.d, z1.d[3]
-; CHECK-i32-NEXT: fcvtzs w9, d0
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fcvtzs w8, d2
-; CHECK-i32-NEXT: mov v0.s[1], w9
-; CHECK-i32-NEXT: mov v0.s[2], w8
-; CHECK-i32-NEXT: fcvtzs w8, d1
-; CHECK-i32-NEXT: mov v0.s[3], w8
+; CHECK-i32-NEXT: frintx z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v4f64:
@@ -1064,34 +1055,17 @@ define <8 x iXLen> @lrint_v8f64(<8 x double> %x) nounwind {
; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-i32-NEXT: splice z2.d, p0, z2.d, z3.d
+; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-i32-NEXT: ptrue p0.d, vl4
-; CHECK-i32-NEXT: movprfx z3, z0
-; CHECK-i32-NEXT: frintx z3.d, p0/m, z0.d
+; CHECK-i32-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-i32-NEXT: frintx z2.d, p0/m, z2.d
-; CHECK-i32-NEXT: mov z0.d, z3.d[1]
-; CHECK-i32-NEXT: mov z1.d, z2.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d3
-; CHECK-i32-NEXT: fcvtzs w9, d2
-; CHECK-i32-NEXT: mov z4.d, z3.d[2]
-; CHECK-i32-NEXT: mov z5.d, z2.d[2]
-; CHECK-i32-NEXT: mov z3.d, z3.d[3]
-; CHECK-i32-NEXT: mov z2.d, z2.d[3]
-; CHECK-i32-NEXT: fcvtzs w10, d0
-; CHECK-i32-NEXT: fcvtzs w11, d1
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fcvtzs w8, d4
-; CHECK-i32-NEXT: fmov s1, w9
-; CHECK-i32-NEXT: fcvtzs w9, d5
-; CHECK-i32-NEXT: mov v0.s[1], w10
-; CHECK-i32-NEXT: mov v1.s[1], w11
-; CHECK-i32-NEXT: mov v0.s[2], w8
-; CHECK-i32-NEXT: fcvtzs w8, d3
-; CHECK-i32-NEXT: mov v1.s[2], w9
-; CHECK-i32-NEXT: fcvtzs w9, d2
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: mov v1.s[3], w9
+; CHECK-i32-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-i32-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-i32-NEXT: uzp1 z1.s, z2.s, z2.s
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v8f64:
@@ -1133,70 +1107,36 @@ declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double>)
define <16 x iXLen> @lrint_v16f64(<16 x double> %x) nounwind {
; CHECK-i32-LABEL: lrint_v16f64:
; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: ptrue p1.d, vl2
-; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-i32-NEXT: ptrue p0.d, vl2
; CHECK-i32-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-i32-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-i32-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-i32-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-i32-NEXT: // kill: def $q5 killed $q5 def $z5
; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-i32-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-i32-NEXT: splice z4.d, p0, z4.d, z5.d
+; CHECK-i32-NEXT: splice z2.d, p0, z2.d, z3.d
; CHECK-i32-NEXT: ptrue p0.d, vl4
-; CHECK-i32-NEXT: splice z0.d, p1, z0.d, z1.d
-; CHECK-i32-NEXT: splice z2.d, p1, z2.d, z3.d
-; CHECK-i32-NEXT: splice z4.d, p1, z4.d, z5.d
-; CHECK-i32-NEXT: splice z6.d, p1, z6.d, z7.d
-; CHECK-i32-NEXT: movprfx z5, z0
-; CHECK-i32-NEXT: frintx z5.d, p0/m, z0.d
-; CHECK-i32-NEXT: movprfx z7, z2
-; CHECK-i32-NEXT: frintx z7.d, p0/m, z2.d
+; CHECK-i32-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-i32-NEXT: frintx z4.d, p0/m, z4.d
; CHECK-i32-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-i32-NEXT: fcvtzs w8, d5
-; CHECK-i32-NEXT: mov z0.d, z5.d[1]
-; CHECK-i32-NEXT: mov z1.d, z7.d[1]
-; CHECK-i32-NEXT: fcvtzs w9, d7
-; CHECK-i32-NEXT: mov z3.d, z4.d[1]
-; CHECK-i32-NEXT: fcvtzs w10, d4
-; CHECK-i32-NEXT: mov z16.d, z6.d[1]
-; CHECK-i32-NEXT: fcvtzs w12, d6
-; CHECK-i32-NEXT: mov z2.d, z5.d[2]
-; CHECK-i32-NEXT: fcvtzs w11, d0
-; CHECK-i32-NEXT: fcvtzs w13, d1
-; CHECK-i32-NEXT: mov z17.d, z7.d[2]
-; CHECK-i32-NEXT: fcvtzs w14, d3
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: mov z18.d, z4.d[2]
-; CHECK-i32-NEXT: fcvtzs w8, d16
-; CHECK-i32-NEXT: mov z19.d, z6.d[2]
-; CHECK-i32-NEXT: fcvtzs w15, d2
-; CHECK-i32-NEXT: fmov s1, w9
-; CHECK-i32-NEXT: fmov s2, w10
-; CHECK-i32-NEXT: fmov s3, w12
-; CHECK-i32-NEXT: fcvtzs w9, d17
-; CHECK-i32-NEXT: fcvtzs w10, d18
-; CHECK-i32-NEXT: mov v0.s[1], w11
-; CHECK-i32-NEXT: fcvtzs w11, d19
-; CHECK-i32-NEXT: mov z5.d, z5.d[3]
-; CHECK-i32-NEXT: mov z7.d, z7.d[3]
-; CHECK-i32-NEXT: mov v1.s[1], w13
-; CHECK-i32-NEXT: mov v2.s[1], w14
-; CHECK-i32-NEXT: mov v3.s[1], w8
-; CHECK-i32-NEXT: mov z4.d, z4.d[3]
-; CHECK-i32-NEXT: mov z6.d, z6.d[3]
-; CHECK-i32-NEXT: mov v0.s[2], w15
-; CHECK-i32-NEXT: fcvtzs w8, d5
-; CHECK-i32-NEXT: mov v1.s[2], w9
-; CHECK-i32-NEXT: fcvtzs w9, d7
-; CHECK-i32-NEXT: mov v2.s[2], w10
-; CHECK-i32-NEXT: fcvtzs w10, d4
-; CHECK-i32-NEXT: mov v3.s[2], w11
-; CHECK-i32-NEXT: fcvtzs w11, d6
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: mov v1.s[3], w9
-; CHECK-i32-NEXT: mov v2.s[3], w10
-; CHECK-i32-NEXT: mov v3.s[3], w11
+; CHECK-i32-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-i32-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-i32-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-i32-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-i32-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-i32-NEXT: uzp1 z3.s, z6.s, z6.s
+; CHECK-i32-NEXT: uzp1 z1.s, z2.s, z2.s
+; CHECK-i32-NEXT: uzp1 z2.s, z4.s, z4.s
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i32-NEXT: // kill: def $q2 killed $q2 killed $z2
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v16f64:
@@ -1264,130 +1204,61 @@ declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f64(<16 x double>)
define <32 x iXLen> @lrint_v32f64(<32 x double> %x) nounwind {
; CHECK-i32-LABEL: lrint_v32f64:
; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: ptrue p1.d, vl2
-; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-i32-NEXT: ldp q16, q17, [sp, #96]
+; CHECK-i32-NEXT: ptrue p0.d, vl2
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-i32-NEXT: // kill: def $q2 killed $q2 def $z2
; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-i32-NEXT: ldp q20, q19, [sp]
+; CHECK-i32-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-i32-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-i32-NEXT: // kill: def $q7 killed $q7 def $z7
-; CHECK-i32-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-i32-NEXT: // kill: def $q5 killed $q5 def $z5
+; CHECK-i32-NEXT: splice z2.d, p0, z2.d, z3.d
+; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-i32-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-i32-NEXT: splice z16.d, p0, z16.d, z17.d
+; CHECK-i32-NEXT: ldp q18, q17, [sp, #64]
+; CHECK-i32-NEXT: ldp q3, q1, [sp, #32]
+; CHECK-i32-NEXT: splice z20.d, p0, z20.d, z19.d
+; CHECK-i32-NEXT: splice z4.d, p0, z4.d, z5.d
+; CHECK-i32-NEXT: splice z18.d, p0, z18.d, z17.d
+; CHECK-i32-NEXT: splice z3.d, p0, z3.d, z1.d
; CHECK-i32-NEXT: ptrue p0.d, vl4
-; CHECK-i32-NEXT: splice z0.d, p1, z0.d, z1.d
-; CHECK-i32-NEXT: splice z2.d, p1, z2.d, z3.d
-; CHECK-i32-NEXT: splice z4.d, p1, z4.d, z5.d
-; CHECK-i32-NEXT: ldp q1, q3, [sp]
-; CHECK-i32-NEXT: splice z6.d, p1, z6.d, z7.d
; CHECK-i32-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-i32-NEXT: movprfx z18, z2
-; CHECK-i32-NEXT: frintx z18.d, p0/m, z2.d
-; CHECK-i32-NEXT: splice z1.d, p1, z1.d, z3.d
-; CHECK-i32-NEXT: ldp q5, q3, [sp, #96]
+; CHECK-i32-NEXT: frintx z2.d, p0/m, z2.d
; CHECK-i32-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-i32-NEXT: ldp q2, q7, [sp, #64]
-; CHECK-i32-NEXT: movprfx z16, z6
-; CHECK-i32-NEXT: frintx z16.d, p0/m, z6.d
-; CHECK-i32-NEXT: mov z19.d, z0.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d0
-; CHECK-i32-NEXT: splice z5.d, p1, z5.d, z3.d
-; CHECK-i32-NEXT: splice z2.d, p1, z2.d, z7.d
-; CHECK-i32-NEXT: ldp q3, q7, [sp, #32]
-; CHECK-i32-NEXT: mov z20.d, z18.d[1]
-; CHECK-i32-NEXT: fcvtzs w9, d18
-; CHECK-i32-NEXT: movprfx z17, z1
-; CHECK-i32-NEXT: frintx z17.d, p0/m, z1.d
-; CHECK-i32-NEXT: mov z1.d, z0.d[2]
-; CHECK-i32-NEXT: fcvtzs w10, d19
-; CHECK-i32-NEXT: mov z6.d, z18.d[2]
-; CHECK-i32-NEXT: splice z3.d, p1, z3.d, z7.d
-; CHECK-i32-NEXT: mov z7.d, z0.d[3]
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fcvtzs w11, d20
-; CHECK-i32-NEXT: mov z20.d, z18.d[3]
-; CHECK-i32-NEXT: mov z18.d, z4.d[1]
-; CHECK-i32-NEXT: fcvtzs w12, d4
-; CHECK-i32-NEXT: mov z21.d, z4.d[2]
-; CHECK-i32-NEXT: fcvtzs w13, d1
-; CHECK-i32-NEXT: fmov s1, w9
-; CHECK-i32-NEXT: mov v0.s[1], w10
-; CHECK-i32-NEXT: movprfx z19, z2
-; CHECK-i32-NEXT: frintx z19.d, p0/m, z2.d
-; CHECK-i32-NEXT: fcvtzs w15, d18
-; CHECK-i32-NEXT: movprfx z18, z3
-; CHECK-i32-NEXT: frintx z18.d, p0/m, z3.d
-; CHECK-i32-NEXT: mov z3.d, z4.d[3]
-; CHECK-i32-NEXT: fcvtzs w16, d16
-; CHECK-i32-NEXT: mov z4.d, z16.d[1]
-; CHECK-i32-NEXT: fcvtzs w14, d6
-; CHECK-i32-NEXT: mov v1.s[1], w11
-; CHECK-i32-NEXT: fcvtzs w11, d21
-; CHECK-i32-NEXT: movprfx z21, z5
-; CHECK-i32-NEXT: frintx z21.d, p0/m, z5.d
-; CHECK-i32-NEXT: fcvtzs w8, d7
-; CHECK-i32-NEXT: fmov s2, w12
-; CHECK-i32-NEXT: mov z7.d, z17.d[1]
-; CHECK-i32-NEXT: mov z6.d, z16.d[2]
-; CHECK-i32-NEXT: mov v0.s[2], w13
-; CHECK-i32-NEXT: fcvtzs w12, d4
-; CHECK-i32-NEXT: fcvtzs w13, d17
-; CHECK-i32-NEXT: fcvtzs w10, d3
-; CHECK-i32-NEXT: fmov s3, w16
-; CHECK-i32-NEXT: mov v2.s[1], w15
-; CHECK-i32-NEXT: mov z4.d, z18.d[1]
-; CHECK-i32-NEXT: fcvtzs w15, d7
-; CHECK-i32-NEXT: mov z5.d, z19.d[1]
-; CHECK-i32-NEXT: fcvtzs w17, d18
-; CHECK-i32-NEXT: fcvtzs w0, d19
-; CHECK-i32-NEXT: mov z7.d, z21.d[1]
-; CHECK-i32-NEXT: fcvtzs w2, d21
-; CHECK-i32-NEXT: fcvtzs w9, d20
-; CHECK-i32-NEXT: mov v1.s[2], w14
-; CHECK-i32-NEXT: mov z20.d, z17.d[2]
-; CHECK-i32-NEXT: fcvtzs w14, d6
-; CHECK-i32-NEXT: mov z6.d, z18.d[2]
-; CHECK-i32-NEXT: fcvtzs w18, d4
-; CHECK-i32-NEXT: fmov s4, w13
-; CHECK-i32-NEXT: fcvtzs w13, d5
-; CHECK-i32-NEXT: mov v3.s[1], w12
-; CHECK-i32-NEXT: fcvtzs w12, d7
-; CHECK-i32-NEXT: fcvtzs w16, d20
-; CHECK-i32-NEXT: mov z20.d, z19.d[2]
-; CHECK-i32-NEXT: mov z22.d, z21.d[2]
-; CHECK-i32-NEXT: fcvtzs w1, d6
-; CHECK-i32-NEXT: fmov s5, w17
-; CHECK-i32-NEXT: fmov s6, w0
-; CHECK-i32-NEXT: fmov s7, w2
-; CHECK-i32-NEXT: mov v4.s[1], w15
-; CHECK-i32-NEXT: mov z16.d, z16.d[3]
-; CHECK-i32-NEXT: fcvtzs w15, d20
-; CHECK-i32-NEXT: mov z17.d, z17.d[3]
-; CHECK-i32-NEXT: mov z18.d, z18.d[3]
-; CHECK-i32-NEXT: mov v5.s[1], w18
-; CHECK-i32-NEXT: mov v6.s[1], w13
-; CHECK-i32-NEXT: fcvtzs w13, d22
-; CHECK-i32-NEXT: mov v7.s[1], w12
-; CHECK-i32-NEXT: mov z19.d, z19.d[3]
-; CHECK-i32-NEXT: mov z20.d, z21.d[3]
-; CHECK-i32-NEXT: mov v2.s[2], w11
-; CHECK-i32-NEXT: mov v3.s[2], w14
-; CHECK-i32-NEXT: fcvtzs w11, d16
-; CHECK-i32-NEXT: mov v4.s[2], w16
-; CHECK-i32-NEXT: fcvtzs w12, d17
-; CHECK-i32-NEXT: fcvtzs w14, d18
-; CHECK-i32-NEXT: mov v5.s[2], w1
-; CHECK-i32-NEXT: mov v6.s[2], w15
-; CHECK-i32-NEXT: fcvtzs w15, d19
-; CHECK-i32-NEXT: mov v7.s[2], w13
-; CHECK-i32-NEXT: fcvtzs w13, d20
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: mov v1.s[3], w9
-; CHECK-i32-NEXT: mov v2.s[3], w10
-; CHECK-i32-NEXT: mov v3.s[3], w11
-; CHECK-i32-NEXT: mov v4.s[3], w12
-; CHECK-i32-NEXT: mov v5.s[3], w14
-; CHECK-i32-NEXT: mov v6.s[3], w15
-; CHECK-i32-NEXT: mov v7.s[3], w13
+; CHECK-i32-NEXT: frintx z6.d, p0/m, z6.d
+; CHECK-i32-NEXT: frintx z20.d, p0/m, z20.d
+; CHECK-i32-NEXT: frintx z18.d, p0/m, z18.d
+; CHECK-i32-NEXT: frintx z3.d, p0/m, z3.d
+; CHECK-i32-NEXT: frintx z16.d, p0/m, z16.d
+; CHECK-i32-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-i32-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-i32-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-i32-NEXT: fcvtzs z20.d, p0/m, z20.d
+; CHECK-i32-NEXT: fcvtzs z18.d, p0/m, z18.d
+; CHECK-i32-NEXT: movprfx z5, z3
+; CHECK-i32-NEXT: fcvtzs z5.d, p0/m, z3.d
+; CHECK-i32-NEXT: fcvtzs z16.d, p0/m, z16.d
+; CHECK-i32-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-i32-NEXT: uzp1 z1.s, z2.s, z2.s
+; CHECK-i32-NEXT: uzp1 z2.s, z4.s, z4.s
+; CHECK-i32-NEXT: uzp1 z3.s, z6.s, z6.s
+; CHECK-i32-NEXT: uzp1 z4.s, z20.s, z20.s
+; CHECK-i32-NEXT: uzp1 z6.s, z18.s, z18.s
+; CHECK-i32-NEXT: uzp1 z5.s, z5.s, z5.s
+; CHECK-i32-NEXT: uzp1 z7.s, z16.s, z16.s
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i32-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-i32-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-i32-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-i32-NEXT: // kill: def $q5 killed $q5 killed $z5
+; CHECK-i32-NEXT: // kill: def $q7 killed $q7 killed $z7
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v32f64:
diff --git a/llvm/test/CodeGen/AArch64/sve-fptosi-sat-scalable-types.ll b/llvm/test/CodeGen/AArch64/sve-fptosi-sat-scalable-types.ll
new file mode 100644
index 0000000000000..3ee72a6cace04
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-fptosi-sat-scalable-types.ll
@@ -0,0 +1,144 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s
+
+;define <vscale x 2 x i32> @fptosi_nxv2f64_to_nxv2i32(<vscale x 2 x double> %f) {
+; %res = call <vscale x 2 x i32> @llvm.fptosi.sat(<vscale x 2 x double> %f)
+; ret <vscale x 2 x i32> %res
+;}
+;
+;define <vscale x 4 x i32> @fptosi_nxv4f64_to_nxv4i32(<vscale x 4 x double> %f) {
+; %res = call <vscale x 4 x i32> @llvm.fptosi.sat(<vscale x 4 x double> %f)
+; ret <vscale x 4 x i32> %res
+;}
+;
+;define <vscale x 8 x i32> @fptosi_nxv8f64_to_nxv8i32(<vscale x 8 x double> %f) {
+; %res = call <vscale x 8 x i32> @llvm.fptosi.sat(<vscale x 8 x double> %f)
+; ret <vscale x 8 x i32> %res
+;}
+;
+;define <vscale x 4 x i16> @fptosi_nxv4f64_to_nxv4i16(<vscale x 4 x double> %f) {
+; %res = call <vscale x 4 x i16> @llvm.fptosi.sat(<vscale x 4 x double> %f)
+; ret <vscale x 4 x i16> %res
+;}
+;
+;define <vscale x 8 x i16> @fptosi_nxv8f64_to_nxv8i16(<vscale x 8 x double> %f) {
+; %res = call <vscale x 8 x i16> @llvm.fptosi.sat(<vscale x 8 x double> %f)
+; ret <vscale x 8 x i16> %res
+;}
+
+define <vscale x 2 x i64> @fptosi_nxv2f64_to_nxv2i64(<vscale x 2 x double> %f) {
+; CHECK-LABEL: fptosi_nxv2f64_to_nxv2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x i64> @llvm.fptosi.sat(<vscale x 2 x double> %f)
+ ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 4 x i64> @fptosi_nxv4f64_to_nxv4i64(<vscale x 4 x double> %f) {
+; CHECK-LABEL: fptosi_nxv4f64_to_nxv4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i64> @llvm.fptosi.sat(<vscale x 4 x double> %f)
+ ret <vscale x 4 x i64> %res
+}
+
+;define <vscale x 2 x i32> @fptosi_nxv2f32_to_nxv2i32(<vscale x 2 x float> %f) {
+; %res = call <vscale x 2 x i32> @llvm.fptosi.sat(<vscale x 2 x float> %f)
+; ret <vscale x 2 x i32> %res
+;}
+
+define <vscale x 4 x i32> @fptosi_nxv4f32_to_nxv4i32(<vscale x 4 x float> %f) {
+; CHECK-LABEL: fptosi_nxv4f32_to_nxv4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i32> @llvm.fptosi.sat(<vscale x 4 x float> %f)
+ ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 8 x i32> @fptosi_nxv8f32_to_nxv8i32(<vscale x 8 x float> %f) {
+; CHECK-LABEL: fptosi_nxv8f32_to_nxv8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
+; CHECK-NEXT: ret
+ %res = call <vscale x 8 x i32> @llvm.fptosi.sat(<vscale x 8 x float> %f)
+ ret <vscale x 8 x i32> %res
+}
+
+;define <vscale x 4 x i16> @fptosi_nxv4f32_to_nxv4i16(<vscale x 4 x float> %f) {
+; %res = call <vscale x 4 x i16> @llvm.fptosi.sat(<vscale x 4 x float> %f)
+; ret <vscale x 4 x i16> %res
+;}
+;
+;define <vscale x 8 x i16> @fptosi_nxv8f32_to_nxv8i16(<vscale x 8 x float> %f) {
+; %res = call <vscale x 8 x i16> @llvm.fptosi.sat(<vscale x 8 x float> %f)
+; ret <vscale x 8 x i16> %res
+;}
+;
+;define <vscale x 2 x i64> @fptosi_nxv2f32_to_nxv2i64(<vscale x 2 x float> %f) {
+; %res = call <vscale x 2 x i64> @llvm.fptosi.sat(<vscale x 2 x float> %f)
+; ret <vscale x 2 x i64> %res
+;}
+;
+;define <vscale x 4 x i64> @fptosi_nxv4f32_to_nxv4i64(<vscale x 4 x float> %f) {
+; %res = call <vscale x 4 x i64> @llvm.fptosi.sat(<vscale x 4 x float> %f)
+; ret <vscale x 4 x i64> %res
+;}
+;
+define <vscale x 2 x i32> @fptosi_nxv2f16_to_nxv2i32(<vscale x 2 x half> %f) {
+; CHECK-LABEL: fptosi_nxv2f16_to_nxv2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: mov z1.d, #0x7fffffff
+; CHECK-NEXT: mov z2.d, #0xffffffff80000000
+; CHECK-NEXT: fcvt z0.d, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x i32> @llvm.fptosi.sat(<vscale x 2 x half> %f)
+ ret <vscale x 2 x i32> %res
+}
+;
+;define <vscale x 4 x i32> @fptosi_nxv4f16_to_nxv4i32(<vscale x 4 x half> %f) {
+; %res = call <vscale x 4 x i32> @llvm.fptosi.sat(<vscale x 4 x half> %f)
+; ret <vscale x 4 x i32> %res
+;}
+;
+;define <vscale x 8 x i32> @fptosi_nxv8f16_to_nxv8i32(<vscale x 8 x half> %f) {
+; %res = call <vscale x 8 x i32> @llvm.fptosi.sat(<vscale x 8 x half> %f)
+; ret <vscale x 8 x i32> %res
+;}
+;
+;define <vscale x 4 x i16> @fptosi_nxv4f16_to_nxv4i16(<vscale x 4 x half> %f) {
+; %res = call <vscale x 4 x i16> @llvm.fptosi.sat(<vscale x 4 x half> %f)
+; ret <vscale x 4 x i16> %res
+;}
+
+define <vscale x 8 x i16> @fptosi_nxv8f16_to_nxv8i16(<vscale x 8 x half> %f) {
+; CHECK-LABEL: fptosi_nxv8f16_to_nxv8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
+; CHECK-NEXT: ret
+ %res = call <vscale x 8 x i16> @llvm.fptosi.sat(<vscale x 8 x half> %f)
+ ret <vscale x 8 x i16> %res
+}
+;
+;define <vscale x 2 x i64> @fptosi_nxv2f16_to_nxv2i64(<vscale x 2 x half> %f) {
+; %res = call <vscale x 2 x i64> @llvm.fptosi.sat(<vscale x 2 x half> %f)
+; ret <vscale x 2 x i64> %res
+;}
+;
+;define <vscale x 4 x i64> @fptosi_nxv4f16_to_nxv4i64(<vscale x 4 x half> %f) {
+; %res = call <vscale x 4 x i64> @llvm.fptosi.sat(<vscale x 4 x half> %f)
+; ret <vscale x 4 x i64> %res
+;}
diff --git a/llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll b/llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
index e9db8434869bb..1091407030693 100644
--- a/llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
@@ -14,19 +14,13 @@ declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float>
define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584 // =0xcf000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0xffffffff80000000
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.d, #0x7fffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.s
-; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: mov z1.d, #0x7fffffff
+; CHECK-NEXT: mov z2.d, #0xffffffff80000000
+; CHECK-NEXT: fcvt z0.d, p0/m, z0.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f32.nxv2i32(<vscale x 2 x float> %f)
ret <vscale x 2 x i32> %x
@@ -35,19 +29,8 @@ define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {
define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584 // =0xcf000000
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, #0x80000000
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.s, #0x7fffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: fcvtzs z1.s, p1/m, z0.s
-; CHECK-NEXT: sel z0.s, p2, z2.s, z1.s
-; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f32.nxv4i32(<vscale x 4 x float> %f)
ret <vscale x 4 x i32> %x
@@ -56,26 +39,9 @@ define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {
define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584 // =0xcf000000
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z3.s, #0x80000000
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff
-; CHECK-NEXT: mov z4.s, #0x80000000
-; CHECK-NEXT: mov z5.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: mov z2.s, #0x7fffffff
-; CHECK-NEXT: fcmgt p3.s, p0/z, z1.s, z5.s
-; CHECK-NEXT: fcvtzs z3.s, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z5.s
-; CHECK-NEXT: fcvtzs z4.s, p2/m, z1.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z0.s, p1, z2.s, z3.s
-; CHECK-NEXT: sel z1.s, p3, z2.s, z4.s
-; CHECK-NEXT: mov z0.s, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
ret <vscale x 8 x i32> %x
@@ -84,18 +50,12 @@ define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {
define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-956301312 // =0xc7000000
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #65024 // =0xfe00
-; CHECK-NEXT: movk w8, #18175, lsl #16
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fmaxnm z1.s, p0/m, z1.s, z0.s
-; CHECK-NEXT: fminnm z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: mov z1.s, #32767 // =0x7fff
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: mov z1.s, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
ret <vscale x 4 x i16> %x
@@ -104,24 +64,16 @@ define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-956301312 // =0xc7000000
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: mov w8, #65024 // =0xfe00
-; CHECK-NEXT: movk w8, #18175, lsl #16
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: movprfx z3, z1
-; CHECK-NEXT: fmaxnm z3.s, p0/m, z3.s, z2.s
-; CHECK-NEXT: fmaxnm z2.s, p0/m, z2.s, z0.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fminnm z3.s, p0/m, z3.s, z4.s
-; CHECK-NEXT: fminnm z2.s, p0/m, z2.s, z4.s
-; CHECK-NEXT: fcvtzs z3.s, p0/m, z3.s
-; CHECK-NEXT: fcvtzs z2.s, p0/m, z2.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: mov z3.s, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.s, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.h, z2.h, z3.h
+; CHECK-NEXT: mov z2.s, #32767 // =0x7fff
+; CHECK-NEXT: mov z3.s, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: smin z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: smin z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT: smax z1.s, p0/m, z1.s, z3.s
+; CHECK-NEXT: smax z0.s, p0/m, z0.s, z3.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
ret <vscale x 8 x i16> %x
@@ -130,19 +82,8 @@ define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x8000000000000000
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.s
-; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
ret <vscale x 2 x i64> %x
@@ -151,28 +92,13 @@ define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: uunpklo z1.d, z0.s
-; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov z2.s, w8
+; CHECK-NEXT: uunpkhi z2.d, z0.s
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p3.s, p0/z, z0.s, z5.s
-; CHECK-NEXT: fcvtzs z3.d, p1/m, z1.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z5.s
-; CHECK-NEXT: fcvtzs z4.d, p2/m, z0.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z2.d, z3.d
-; CHECK-NEXT: sel z1.d, p3, z2.d, z4.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
ret <vscale x 4 x i64> %x
@@ -191,18 +117,12 @@ declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double
define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000
-; CHECK-NEXT: movk x8, #16863, lsl #48
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fmaxnm z1.d, p0/m, z1.d, z0.d
-; CHECK-NEXT: fminnm z1.d, p0/m, z1.d, z2.d
-; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: mov z1.d, #0x7fffffff
+; CHECK-NEXT: mov z2.d, #0xffffffff80000000
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
ret <vscale x 2 x i32> %x
@@ -211,24 +131,16 @@ define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000
-; CHECK-NEXT: movk x8, #16863, lsl #48
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: movprfx z3, z1
-; CHECK-NEXT: fmaxnm z3.d, p0/m, z3.d, z2.d
-; CHECK-NEXT: fmaxnm z2.d, p0/m, z2.d, z0.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fminnm z3.d, p0/m, z3.d, z4.d
-; CHECK-NEXT: fminnm z2.d, p0/m, z2.d, z4.d
-; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
-; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z3.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z2.s, z3.s
+; CHECK-NEXT: mov z2.d, #0x7fffffff
+; CHECK-NEXT: mov z3.d, #0xffffffff80000000
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z3.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
ret <vscale x 4 x i32> %x
@@ -237,37 +149,23 @@ define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000
-; CHECK-NEXT: movk x8, #16863, lsl #48
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: movprfx z6, z1
-; CHECK-NEXT: fmaxnm z6.d, p0/m, z6.d, z4.d
-; CHECK-NEXT: movprfx z7, z0
-; CHECK-NEXT: fmaxnm z7.d, p0/m, z7.d, z4.d
-; CHECK-NEXT: movprfx z24, z3
-; CHECK-NEXT: fmaxnm z24.d, p0/m, z24.d, z4.d
-; CHECK-NEXT: fmaxnm z4.d, p0/m, z4.d, z2.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fminnm z6.d, p0/m, z6.d, z5.d
-; CHECK-NEXT: fminnm z7.d, p0/m, z7.d, z5.d
-; CHECK-NEXT: fminnm z24.d, p0/m, z24.d, z5.d
-; CHECK-NEXT: fminnm z4.d, p0/m, z4.d, z5.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
-; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
-; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.d
-; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: mov z6.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z24.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z4.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z7.s, z6.s
-; CHECK-NEXT: uzp1 z1.s, z4.s, z24.s
+; CHECK-NEXT: mov z4.d, #0x7fffffff
+; CHECK-NEXT: mov z5.d, #0xffffffff80000000
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z4.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z4.d
+; CHECK-NEXT: smin z3.d, p0/m, z3.d, z4.d
+; CHECK-NEXT: smin z2.d, p0/m, z2.d, z4.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z5.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z5.d
+; CHECK-NEXT: smax z3.d, p0/m, z3.d, z5.d
+; CHECK-NEXT: smax z2.d, p0/m, z2.d, z5.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: uzp1 z1.s, z2.s, z3.s
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
ret <vscale x 8 x i32> %x
@@ -276,24 +174,16 @@ define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4548635623644200960 // =0xc0e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov x8, #281200098803712 // =0xffc000000000
-; CHECK-NEXT: movk x8, #16607, lsl #48
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: movprfx z3, z1
-; CHECK-NEXT: fmaxnm z3.d, p0/m, z3.d, z2.d
-; CHECK-NEXT: fmaxnm z2.d, p0/m, z2.d, z0.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fminnm z3.d, p0/m, z3.d, z4.d
-; CHECK-NEXT: fminnm z2.d, p0/m, z2.d, z4.d
-; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
-; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z3.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z2.s, z3.s
+; CHECK-NEXT: mov z2.d, #32767 // =0x7fff
+; CHECK-NEXT: mov z3.d, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z3.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double> %f)
ret <vscale x 4 x i16> %x
@@ -302,38 +192,24 @@ define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4548635623644200960 // =0xc0e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: mov x8, #281200098803712 // =0xffc000000000
-; CHECK-NEXT: movk x8, #16607, lsl #48
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: movprfx z6, z3
-; CHECK-NEXT: fmaxnm z6.d, p0/m, z6.d, z4.d
-; CHECK-NEXT: movprfx z7, z2
-; CHECK-NEXT: fmaxnm z7.d, p0/m, z7.d, z4.d
-; CHECK-NEXT: movprfx z24, z1
-; CHECK-NEXT: fmaxnm z24.d, p0/m, z24.d, z4.d
-; CHECK-NEXT: fmaxnm z4.d, p0/m, z4.d, z0.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: fminnm z6.d, p0/m, z6.d, z5.d
-; CHECK-NEXT: fminnm z7.d, p0/m, z7.d, z5.d
-; CHECK-NEXT: fminnm z24.d, p0/m, z24.d, z5.d
-; CHECK-NEXT: fminnm z4.d, p0/m, z4.d, z5.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
-; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
-; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.d
-; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z6.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z24.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z4.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z7.s, z6.s
-; CHECK-NEXT: uzp1 z1.s, z4.s, z24.s
-; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
+; CHECK-NEXT: mov z4.d, #32767 // =0x7fff
+; CHECK-NEXT: mov z5.d, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z3.d, p0/m, z3.d, z4.d
+; CHECK-NEXT: smin z2.d, p0/m, z2.d, z4.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z4.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z4.d
+; CHECK-NEXT: smax z3.d, p0/m, z3.d, z5.d
+; CHECK-NEXT: smax z2.d, p0/m, z2.d, z5.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z5.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z5.d
+; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double> %f)
ret <vscale x 8 x i16> %x
@@ -342,19 +218,8 @@ define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {
define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x8000000000000000
-; CHECK-NEXT: fcmgt p2.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.d
-; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double> %f)
ret <vscale x 2 x i64> %x
@@ -363,26 +228,9 @@ define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {
define <vscale x 4 x i64> @test_signed_v4f64_v4i64(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z5.d
-; CHECK-NEXT: fcvtzs z3.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z5.d
-; CHECK-NEXT: fcvtzs z4.d, p2/m, z1.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z0.d, p1, z2.d, z3.d
-; CHECK-NEXT: sel z1.d, p3, z2.d, z4.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double> %f)
ret <vscale x 4 x i64> %x
@@ -402,18 +250,13 @@ declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: mov z2.d, #0xffffffff80000000
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
; CHECK-NEXT: mov z1.d, #0x7fffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: mov z2.d, #0xffffffff80000000
+; CHECK-NEXT: fcvt z0.d, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
ret <vscale x 2 x i32> %x
@@ -422,18 +265,8 @@ define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: mov z2.s, #0x80000000
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.s, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.s, #0x7fffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.s, p1, z1.s, z2.s
-; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
ret <vscale x 4 x i32> %x
@@ -442,27 +275,13 @@ define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: uunpklo z2.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z0.h
+; CHECK-NEXT: uunpkhi z2.s, z0.h
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z3.s, #0x80000000
-; CHECK-NEXT: mov z4.s, #0x80000000
-; CHECK-NEXT: mov z5.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z1.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.s, #0x7fffffff
-; CHECK-NEXT: fcmgt p3.h, p0/z, z0.h, z5.h
-; CHECK-NEXT: fcvtzs z3.s, p1/m, z2.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z5.h
-; CHECK-NEXT: fcvtzs z4.s, p2/m, z0.h
-; CHECK-NEXT: fcmuo p2.h, p0/z, z2.h, z2.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.s, p1, z1.s, z3.s
-; CHECK-NEXT: sel z1.s, p3, z1.s, z4.s
-; CHECK-NEXT: mov z0.s, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
ret <vscale x 8 x i32> %x
@@ -471,18 +290,13 @@ define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: dupm z1.h, #0xf800
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #30719 // =0x77ff
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: mov z1.s, #32767 // =0x7fff
+; CHECK-NEXT: fcvt z0.s, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: mov z1.s, #-32768 // =0xffffffffffff8000
-; CHECK-NEXT: fcvtzs z1.s, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: mov z2.s, #32767 // =0x7fff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.s, p1, z2.s, z1.s
-; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
+; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f16.nxv4i16(<vscale x 4 x half> %f)
ret <vscale x 4 x i16> %x
@@ -491,18 +305,8 @@ define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: dupm z1.h, #0xf800
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: mov w8, #30719 // =0x77ff
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, #-32768 // =0xffffffffffff8000
-; CHECK-NEXT: fcvtzs z1.h, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: mov z2.h, #32767 // =0x7fff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.h, p1, z2.h, z1.h
-; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
ret <vscale x 8 x i16> %x
@@ -511,18 +315,8 @@ define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
ret <vscale x 2 x i64> %x
@@ -531,27 +325,13 @@ define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z1.d, z0.s
+; CHECK-NEXT: uunpkhi z2.d, z0.s
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z1.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p3.h, p0/z, z0.h, z5.h
-; CHECK-NEXT: fcvtzs z3.d, p1/m, z2.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z5.h
-; CHECK-NEXT: fcvtzs z4.d, p2/m, z0.h
-; CHECK-NEXT: fcmuo p2.h, p0/z, z2.h, z2.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z3.d
-; CHECK-NEXT: sel z1.d, p3, z1.d, z4.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
ret <vscale x 4 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll b/llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
index 61620fbdf0826..be3a0c21e8611 100644
--- a/llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
@@ -15,14 +15,10 @@ define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #1333788671 // =0x4f7fffff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.0
-; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.s
-; CHECK-NEXT: mov z0.d, #0xffffffff
-; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: mov z1.d, #0xffffffff
+; CHECK-NEXT: fcvt z0.d, p0/m, z0.s
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f32.nxv2i32(<vscale x 2 x float> %f)
ret <vscale x 2 x i32> %x
@@ -32,14 +28,7 @@ define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #1333788671 // =0x4f7fffff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.0
-; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.s
-; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f32.nxv4i32(<vscale x 4 x float> %f)
ret <vscale x 4 x i32> %x
@@ -49,20 +38,8 @@ define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #1333788671 // =0x4f7fffff
-; CHECK-NEXT: movi v2.2d, #0000000000000000
-; CHECK-NEXT: movi v3.2d, #0000000000000000
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.0
-; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, #0.0
-; CHECK-NEXT: fcvtzu z2.s, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z4.s
-; CHECK-NEXT: fcvtzu z3.s, p2/m, z1.s
-; CHECK-NEXT: fcmgt p0.s, p0/z, z1.s, z4.s
-; CHECK-NEXT: mov z2.s, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z3.s, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z2.d
-; CHECK-NEXT: mov z1.d, z3.d
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
ret <vscale x 8 x i32> %x
@@ -72,16 +49,9 @@ define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #65280 // =0xff00
-; CHECK-NEXT: movk w8, #18303, lsl #16
-; CHECK-NEXT: movprfx z1, z0
-; CHECK-NEXT: fmaxnm z1.s, p0/m, z1.s, #0.0
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fminnm z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: mov z1.s, #65535 // =0xffff
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
ret <vscale x 4 x i16> %x
@@ -91,22 +61,12 @@ define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #65280 // =0xff00
-; CHECK-NEXT: movk w8, #18303, lsl #16
-; CHECK-NEXT: movprfx z2, z1
-; CHECK-NEXT: fmaxnm z2.s, p0/m, z2.s, #0.0
-; CHECK-NEXT: movprfx z3, z0
-; CHECK-NEXT: fmaxnm z3.s, p0/m, z3.s, #0.0
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: fcmuo p1.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fminnm z2.s, p0/m, z2.s, z4.s
-; CHECK-NEXT: fminnm z3.s, p0/m, z3.s, z4.s
-; CHECK-NEXT: fcvtzu z2.s, p0/m, z2.s
-; CHECK-NEXT: fcvtzu z3.s, p0/m, z3.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: mov z2.s, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z3.s, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.h, z3.h, z2.h
+; CHECK-NEXT: mov z2.s, #65535 // =0xffff
+; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT: umin z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: umin z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
ret <vscale x 8 x i16> %x
@@ -116,14 +76,7 @@ define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #1602224127 // =0x5f7fffff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.0
-; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.s
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
ret <vscale x 2 x i64> %x
@@ -132,21 +85,13 @@ define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: uunpkhi z3.d, z0.s
-; CHECK-NEXT: mov w8, #1602224127 // =0x5f7fffff
+; CHECK-NEXT: uunpklo z1.d, z0.s
+; CHECK-NEXT: uunpkhi z2.d, z0.s
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z2.s, #0.0
-; CHECK-NEXT: fcmge p2.s, p0/z, z3.s, #0.0
-; CHECK-NEXT: fcvtzu z0.d, p1/m, z2.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z2.s, z4.s
-; CHECK-NEXT: fcvtzu z1.d, p2/m, z3.s
-; CHECK-NEXT: fcmgt p0.s, p0/z, z3.s, z4.s
-; CHECK-NEXT: mov z0.d, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.s
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z2.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
ret <vscale x 4 x i64> %x
@@ -166,16 +111,9 @@ define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281474974613504 // =0xffffffe00000
-; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: movprfx z1, z0
-; CHECK-NEXT: fmaxnm z1.d, p0/m, z1.d, #0.0
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fminnm z1.d, p0/m, z1.d, z2.d
-; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: mov z1.d, #0xffffffff
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
ret <vscale x 2 x i32> %x
@@ -185,22 +123,12 @@ define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281474974613504 // =0xffffffe00000
-; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: movprfx z2, z1
-; CHECK-NEXT: fmaxnm z2.d, p0/m, z2.d, #0.0
-; CHECK-NEXT: movprfx z3, z0
-; CHECK-NEXT: fmaxnm z3.d, p0/m, z3.d, #0.0
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fminnm z2.d, p0/m, z2.d, z4.d
-; CHECK-NEXT: fminnm z3.d, p0/m, z3.d, z4.d
-; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
-; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z2.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z3.s, z2.s
+; CHECK-NEXT: mov z2.d, #0xffffffff
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
ret <vscale x 4 x i32> %x
@@ -210,35 +138,17 @@ define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281474974613504 // =0xffffffe00000
-; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: movprfx z5, z1
-; CHECK-NEXT: fmaxnm z5.d, p0/m, z5.d, #0.0
-; CHECK-NEXT: movprfx z6, z0
-; CHECK-NEXT: fmaxnm z6.d, p0/m, z6.d, #0.0
-; CHECK-NEXT: movprfx z7, z3
-; CHECK-NEXT: fmaxnm z7.d, p0/m, z7.d, #0.0
-; CHECK-NEXT: movprfx z24, z2
-; CHECK-NEXT: fmaxnm z24.d, p0/m, z24.d, #0.0
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fminnm z5.d, p0/m, z5.d, z4.d
-; CHECK-NEXT: fminnm z6.d, p0/m, z6.d, z4.d
-; CHECK-NEXT: fminnm z7.d, p0/m, z7.d, z4.d
-; CHECK-NEXT: fminnm z4.d, p0/m, z4.d, z24.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: fcvtzu z5.d, p0/m, z5.d
-; CHECK-NEXT: fcvtzu z6.d, p0/m, z6.d
-; CHECK-NEXT: fcvtzu z7.d, p0/m, z7.d
-; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: mov z5.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z4.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z6.s, z5.s
-; CHECK-NEXT: uzp1 z1.s, z4.s, z7.s
+; CHECK-NEXT: mov z4.d, #0xffffffff
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
+; CHECK-NEXT: umin z1.d, p0/m, z1.d, z4.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z4.d
+; CHECK-NEXT: umin z3.d, p0/m, z3.d, z4.d
+; CHECK-NEXT: umin z2.d, p0/m, z2.d, z4.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: uzp1 z1.s, z2.s, z3.s
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
ret <vscale x 8 x i32> %x
@@ -248,22 +158,12 @@ define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281337537757184 // =0xffe000000000
-; CHECK-NEXT: movk x8, #16623, lsl #48
-; CHECK-NEXT: movprfx z2, z1
-; CHECK-NEXT: fmaxnm z2.d, p0/m, z2.d, #0.0
-; CHECK-NEXT: movprfx z3, z0
-; CHECK-NEXT: fmaxnm z3.d, p0/m, z3.d, #0.0
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fminnm z2.d, p0/m, z2.d, z4.d
-; CHECK-NEXT: fminnm z3.d, p0/m, z3.d, z4.d
-; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
-; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z2.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z3.s, z2.s
+; CHECK-NEXT: mov z2.d, #65535 // =0xffff
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double> %f)
ret <vscale x 4 x i16> %x
@@ -273,36 +173,18 @@ define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281337537757184 // =0xffe000000000
-; CHECK-NEXT: movk x8, #16623, lsl #48
-; CHECK-NEXT: movprfx z5, z3
-; CHECK-NEXT: fmaxnm z5.d, p0/m, z5.d, #0.0
-; CHECK-NEXT: movprfx z6, z2
-; CHECK-NEXT: fmaxnm z6.d, p0/m, z6.d, #0.0
-; CHECK-NEXT: movprfx z7, z1
-; CHECK-NEXT: fmaxnm z7.d, p0/m, z7.d, #0.0
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: fmaxnm z24.d, p0/m, z24.d, #0.0
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmuo p1.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: fminnm z5.d, p0/m, z5.d, z4.d
-; CHECK-NEXT: fminnm z6.d, p0/m, z6.d, z4.d
-; CHECK-NEXT: fminnm z7.d, p0/m, z7.d, z4.d
-; CHECK-NEXT: fminnm z4.d, p0/m, z4.d, z24.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fcvtzu z5.d, p0/m, z5.d
-; CHECK-NEXT: fcvtzu z6.d, p0/m, z6.d
-; CHECK-NEXT: fcvtzu z7.d, p0/m, z7.d
-; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z5.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z4.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z6.s, z5.s
-; CHECK-NEXT: uzp1 z1.s, z4.s, z7.s
-; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
+; CHECK-NEXT: mov z4.d, #65535 // =0xffff
+; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z3.d, p0/m, z3.d, z4.d
+; CHECK-NEXT: umin z2.d, p0/m, z2.d, z4.d
+; CHECK-NEXT: umin z1.d, p0/m, z1.d, z4.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z4.d
+; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double> %f)
ret <vscale x 8 x i16> %x
@@ -312,14 +194,7 @@ define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #4895412794951729151 // =0x43efffffffffffff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, #0.0
-; CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.d
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double> %f)
ret <vscale x 2 x i64> %x
@@ -329,20 +204,8 @@ define <vscale x 4 x i64> @test_signed_v4f64_v4i64(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #4895412794951729151 // =0x43efffffffffffff
-; CHECK-NEXT: movi v2.2d, #0000000000000000
-; CHECK-NEXT: movi v3.2d, #0000000000000000
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, #0.0
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, #0.0
-; CHECK-NEXT: fcvtzu z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z4.d
-; CHECK-NEXT: fcvtzu z3.d, p2/m, z1.d
-; CHECK-NEXT: fcmgt p0.d, p0/z, z1.d, z4.d
-; CHECK-NEXT: mov z2.d, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z3.d, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z2.d
-; CHECK-NEXT: mov z1.d, z3.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double> %f)
ret <vscale x 4 x i64> %x
@@ -363,14 +226,10 @@ define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.h
-; CHECK-NEXT: mov z0.d, #0xffffffff
-; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: mov z1.d, #0xffffffff
+; CHECK-NEXT: fcvt z0.d, p0/m, z0.h
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
ret <vscale x 2 x i32> %x
@@ -380,14 +239,7 @@ define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.h
-; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
ret <vscale x 4 x i32> %x
@@ -396,21 +248,13 @@ define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z2.s, z0.h
-; CHECK-NEXT: uunpkhi z3.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
+; CHECK-NEXT: uunpklo z1.s, z0.h
+; CHECK-NEXT: uunpkhi z2.s, z0.h
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z4.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, #0.0
-; CHECK-NEXT: fcmge p2.h, p0/z, z3.h, #0.0
-; CHECK-NEXT: fcvtzu z0.s, p1/m, z2.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z4.h
-; CHECK-NEXT: fcvtzu z1.s, p2/m, z3.h
-; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z4.h
-; CHECK-NEXT: mov z0.s, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzu z1.s, p0/m, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
ret <vscale x 8 x i32> %x
@@ -420,14 +264,10 @@ define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.h
-; CHECK-NEXT: mov z0.s, #65535 // =0xffff
-; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: mov z1.s, #65535 // =0xffff
+; CHECK-NEXT: fcvt z0.s, p0/m, z0.h
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f16.nxv4i16(<vscale x 4 x half> %f)
ret <vscale x 4 x i16> %x
@@ -437,14 +277,7 @@ define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.h, p1/m, z0.h
-; CHECK-NEXT: mov z1.h, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
ret <vscale x 8 x i16> %x
@@ -454,14 +287,7 @@ define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.h
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
ret <vscale x 2 x i64> %x
@@ -470,21 +296,13 @@ define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: uunpkhi z3.d, z0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
+; CHECK-NEXT: uunpklo z1.d, z0.s
+; CHECK-NEXT: uunpkhi z2.d, z0.s
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z4.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, #0.0
-; CHECK-NEXT: fcmge p2.h, p0/z, z3.h, #0.0
-; CHECK-NEXT: fcvtzu z0.d, p1/m, z2.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z4.h
-; CHECK-NEXT: fcvtzu z1.d, p2/m, z3.h
-; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z4.h
-; CHECK-NEXT: mov z0.d, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
ret <vscale x 4 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/sve-llrint.ll b/llvm/test/CodeGen/AArch64/sve-llrint.ll
index 436b09e93fa9e..8ecf378d5623d 100644
--- a/llvm/test/CodeGen/AArch64/sve-llrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-llrint.ll
@@ -5,18 +5,8 @@ define <vscale x 1 x i64> @llrint_v1i64_v1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: llrint_v1i64_v1f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x i64> %a
@@ -27,18 +17,8 @@ define <vscale x 2 x i64> @llrint_v1i64_v2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: llrint_v1i64_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x i64> %a
@@ -50,27 +30,14 @@ define <vscale x 4 x i64> @llrint_v4i64_v4f16(<vscale x 4 x half> %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
; CHECK-NEXT: frintx z1.h, p0/m, z1.h
-; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z2.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmuo p3.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z1.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z2.h
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z0.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: frintx z2.h, p0/m, z0.h
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x i64> %a
@@ -80,62 +47,25 @@ declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f16(<vscale x 4 x half>)
define <vscale x 8 x i64> @llrint_v8i64_v8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: llrint_v8i64_v8f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: uunpklo z1.s, z0.h
; CHECK-NEXT: uunpkhi z0.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z4.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.d, #0x7fffffffffffffff
; CHECK-NEXT: uunpklo z2.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
; CHECK-NEXT: uunpklo z3.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: frintx z2.h, p0/m, z2.h
; CHECK-NEXT: frintx z1.h, p0/m, z1.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
; CHECK-NEXT: frintx z3.h, p0/m, z3.h
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: frintx z24.h, p0/m, z0.h
-; CHECK-NEXT: mov z0.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z4.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z1.h, z4.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z3.h, z4.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z1.h, z0.h
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z2.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z24.h, z4.h
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z6.d, p2/m, z1.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z2.h, z0.h
-; CHECK-NEXT: fcvtzs z7.d, p3/m, z3.h
-; CHECK-NEXT: fcmgt p5.h, p0/z, z3.h, z0.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z24.h, z0.h
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z24.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z2.h, z2.h
-; CHECK-NEXT: sel z0.d, p2, z25.d, z5.d
-; CHECK-NEXT: fcmuo p1.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: sel z1.d, p4, z25.d, z6.d
-; CHECK-NEXT: sel z2.d, p5, z25.d, z7.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z3.h, z3.h
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.h, p0/z, z24.h, z24.h
-; CHECK-NEXT: sel z3.d, p6, z25.d, z4.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z4, z0
+; CHECK-NEXT: frintx z4.h, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z0, z2
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z2, z3
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z3.h
+; CHECK-NEXT: movprfx z3, z4
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z4.h
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x i64> %a
@@ -145,110 +75,46 @@ declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f16(<vscale x 8 x half>)
define <vscale x 16 x i64> @llrint_v16i64_v16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: llrint_v16i64_v16f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: uunpkhi z3.s, z0.h
; CHECK-NEXT: uunpklo z2.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: uunpklo z7.s, z1.h
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z0.h, #-1025 // =0xfffffffffffffbff
+; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z3.s, z1.h
; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z29.h, w8
-; CHECK-NEXT: uunpkhi z25.d, z3.s
+; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: uunpklo z4.d, z2.s
-; CHECK-NEXT: uunpkhi z6.d, z2.s
-; CHECK-NEXT: uunpklo z24.d, z3.s
-; CHECK-NEXT: uunpklo z26.d, z7.s
-; CHECK-NEXT: uunpkhi z7.d, z7.s
-; CHECK-NEXT: uunpklo z30.d, z1.s
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
+; CHECK-NEXT: uunpkhi z2.d, z2.s
+; CHECK-NEXT: uunpklo z5.d, z0.s
+; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z6.d, z3.s
+; CHECK-NEXT: uunpkhi z3.d, z3.s
+; CHECK-NEXT: uunpklo z7.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: movprfx z27, z4
-; CHECK-NEXT: frintx z27.h, p0/m, z4.h
-; CHECK-NEXT: movprfx z28, z6
-; CHECK-NEXT: frintx z28.h, p0/m, z6.h
-; CHECK-NEXT: frintx z25.h, p0/m, z25.h
-; CHECK-NEXT: frintx z24.h, p0/m, z24.h
-; CHECK-NEXT: frintx z26.h, p0/m, z26.h
+; CHECK-NEXT: frintx z4.h, p0/m, z4.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
+; CHECK-NEXT: movprfx z24, z0
+; CHECK-NEXT: frintx z24.h, p0/m, z0.h
+; CHECK-NEXT: frintx z6.h, p0/m, z6.h
+; CHECK-NEXT: movprfx z25, z3
+; CHECK-NEXT: frintx z25.h, p0/m, z3.h
; CHECK-NEXT: frintx z7.h, p0/m, z7.h
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: frintx z30.h, p0/m, z30.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z25.h, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z27.h, z0.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z28.h, z0.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z24.h, z0.h
-; CHECK-NEXT: fcvtzs z5.d, p4/m, z25.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z26.h, z0.h
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z27.h
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z28.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z7.h, z0.h
-; CHECK-NEXT: fcvtzs z4.d, p3/m, z24.h
-; CHECK-NEXT: fcmgt p3.h, p0/z, z27.h, z29.h
-; CHECK-NEXT: fcvtzs z6.d, p5/m, z26.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z27.h, z27.h
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z31.d, p4/m, z7.h
-; CHECK-NEXT: fcmgt p5.h, p0/z, z28.h, z29.h
-; CHECK-NEXT: fcmuo p2.h, p0/z, z28.h, z28.h
-; CHECK-NEXT: movprfx z28, z1
-; CHECK-NEXT: frintx z28.h, p0/m, z1.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z30.h, z0.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z24.h, z29.h
-; CHECK-NEXT: fcmuo p7.h, p0/z, z24.h, z24.h
-; CHECK-NEXT: mov z24.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p8.h, p0/z, z25.h, z29.h
-; CHECK-NEXT: fcvtzs z27.d, p4/m, z30.h
-; CHECK-NEXT: fcmuo p10.h, p0/z, z25.h, z25.h
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: sel z1.d, p5, z24.d, z3.d
-; CHECK-NEXT: fcmge p4.h, p0/z, z28.h, z0.h
-; CHECK-NEXT: sel z0.d, p3, z24.d, z2.d
-; CHECK-NEXT: sel z2.d, p6, z24.d, z4.d
-; CHECK-NEXT: sel z3.d, p8, z24.d, z5.d
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p9.h, p0/z, z26.h, z29.h
-; CHECK-NEXT: mov z2.d, p7/m, #0 // =0x0
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcvtzs z25.d, p4/m, z28.h
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p5.h, p0/z, z7.h, z29.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z30.h, z29.h
-; CHECK-NEXT: sel z4.d, p9, z24.d, z6.d
-; CHECK-NEXT: fcmgt p4.h, p0/z, z28.h, z29.h
-; CHECK-NEXT: fcmuo p8.h, p0/z, z7.h, z7.h
-; CHECK-NEXT: sel z5.d, p5, z24.d, z31.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p9.h, p0/z, z30.h, z30.h
-; CHECK-NEXT: sel z6.d, p6, z24.d, z27.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: sel z7.d, p4, z24.d, z25.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p3.h, p0/z, z26.h, z26.h
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.h, p0/z, z28.h, z28.h
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z26, z1
+; CHECK-NEXT: frintx z26.h, p0/m, z1.h
+; CHECK-NEXT: movprfx z0, z4
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z4.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z2, z5
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z5.h
+; CHECK-NEXT: movprfx z3, z24
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z24.h
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z6.h
+; CHECK-NEXT: movprfx z5, z25
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z25.h
+; CHECK-NEXT: movprfx z6, z7
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z7.h
+; CHECK-NEXT: movprfx z7, z26
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z26.h
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x i64> %a
@@ -258,252 +124,79 @@ declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f16(<vscale x 16 x half>)
define <vscale x 32 x i64> @llrint_v32i64_v32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: llrint_v32i64_v32f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x90, 0x01, 0x1e, 0x22 // sp + 16 + 144 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: uunpklo z4.s, z0.h
-; CHECK-NEXT: uunpkhi z0.s, z0.h
-; CHECK-NEXT: mov w9, #31743 // =0x7bff
-; CHECK-NEXT: uunpklo z5.s, z1.h
+; CHECK-NEXT: uunpkhi z4.s, z3.h
+; CHECK-NEXT: uunpklo z3.s, z3.h
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z28.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: uunpkhi z29.s, z1.h
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: uunpklo z13.s, z2.h
-; CHECK-NEXT: mov z9.d, #0x8000000000000000
-; CHECK-NEXT: uunpkhi z14.s, z2.h
-; CHECK-NEXT: uunpkhi z17.s, z3.h
-; CHECK-NEXT: uunpklo z6.d, z4.s
-; CHECK-NEXT: uunpkhi z4.d, z4.s
-; CHECK-NEXT: uunpklo z27.d, z0.s
-; CHECK-NEXT: uunpklo z31.d, z5.s
-; CHECK-NEXT: uunpkhi z8.d, z5.s
-; CHECK-NEXT: uunpkhi z30.d, z0.s
-; CHECK-NEXT: uunpkhi z11.d, z29.s
-; CHECK-NEXT: uunpklo z10.d, z29.s
-; CHECK-NEXT: uunpklo z15.s, z3.h
-; CHECK-NEXT: uunpklo z16.d, z14.s
-; CHECK-NEXT: uunpkhi z14.d, z14.s
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z5, z27
-; CHECK-NEXT: frintx z5.h, p0/m, z27.h
-; CHECK-NEXT: movprfx z1, z6
-; CHECK-NEXT: frintx z1.h, p0/m, z6.h
+; CHECK-NEXT: uunpkhi z7.s, z2.h
+; CHECK-NEXT: uunpklo z2.s, z2.h
+; CHECK-NEXT: uunpkhi z24.s, z0.h
+; CHECK-NEXT: uunpkhi z25.s, z1.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpkhi z5.d, z4.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpkhi z6.d, z3.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: uunpkhi z26.d, z7.s
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: uunpkhi z27.d, z2.s
+; CHECK-NEXT: uunpkhi z28.d, z24.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: uunpkhi z29.d, z25.s
+; CHECK-NEXT: uunpklo z25.d, z25.s
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
; CHECK-NEXT: frintx z4.h, p0/m, z4.h
-; CHECK-NEXT: movprfx z12, z31
-; CHECK-NEXT: frintx z12.h, p0/m, z31.h
-; CHECK-NEXT: movprfx z27, z8
-; CHECK-NEXT: frintx z27.h, p0/m, z8.h
-; CHECK-NEXT: movprfx z6, z30
-; CHECK-NEXT: frintx z6.h, p0/m, z30.h
-; CHECK-NEXT: movprfx z31, z10
-; CHECK-NEXT: frintx z31.h, p0/m, z10.h
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
-; CHECK-NEXT: frintx z11.h, p0/m, z11.h
-; CHECK-NEXT: movprfx z3, z16
-; CHECK-NEXT: frintx z3.h, p0/m, z16.h
-; CHECK-NEXT: mov z30.h, w9
-; CHECK-NEXT: uunpklo z10.d, z13.s
-; CHECK-NEXT: uunpkhi z13.d, z13.s
-; CHECK-NEXT: uunpkhi z20.d, z15.s
-; CHECK-NEXT: uunpklo z16.d, z17.s
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: mov z18.d, #0x8000000000000000
-; CHECK-NEXT: uunpklo z15.d, z15.s
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: frintx z10.h, p0/m, z10.h
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z29.d, #0x7fffffffffffffff
-; CHECK-NEXT: movprfx z19, z13
-; CHECK-NEXT: frintx z19.h, p0/m, z13.h
-; CHECK-NEXT: movprfx z13, z14
-; CHECK-NEXT: frintx z13.h, p0/m, z14.h
-; CHECK-NEXT: frintx z20.h, p0/m, z20.h
-; CHECK-NEXT: frintx z16.h, p0/m, z16.h
-; CHECK-NEXT: mov z22.d, #0x8000000000000000
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: frintx z15.h, p0/m, z15.h
-; CHECK-NEXT: mov z14.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p4.h, p0/z, z4.h, z28.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z12.h, z28.h
-; CHECK-NEXT: fcmgt p9.h, p0/z, z12.h, z30.h
-; CHECK-NEXT: fcmuo p8.h, p0/z, z12.h, z12.h
-; CHECK-NEXT: fcvtzs z7.d, p4/m, z4.h
-; CHECK-NEXT: fcvtzs z8.d, p2/m, z12.h
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p4.h, p0/z, z27.h, z28.h
-; CHECK-NEXT: fcmuo p10.h, p0/z, z11.h, z11.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z5.h, z28.h
-; CHECK-NEXT: mov z8.d, p9/m, z29.d
-; CHECK-NEXT: fcvtzs z9.d, p4/m, z27.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z11.h, z28.h
-; CHECK-NEXT: fcvtzs z24.d, p3/m, z5.h
-; CHECK-NEXT: mov z8.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcmge p1.h, p0/z, z6.h, z28.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z1.h, z28.h
-; CHECK-NEXT: str z8, [x8, #4, mul vl]
-; CHECK-NEXT: fcvtzs z12.d, p4/m, z11.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z11.h, z30.h
-; CHECK-NEXT: uunpkhi z11.d, z17.s
-; CHECK-NEXT: mov z17.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z25.d, p1/m, z6.h
-; CHECK-NEXT: fcvtzs z0.d, p5/m, z1.h
-; CHECK-NEXT: fcmge p6.h, p0/z, z10.h, z28.h
-; CHECK-NEXT: frintx z11.h, p0/m, z11.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z31.h, z28.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z13.h, z28.h
-; CHECK-NEXT: fcvtzs z18.d, p6/m, z10.h
-; CHECK-NEXT: fcmgt p11.h, p0/z, z10.h, z30.h
-; CHECK-NEXT: fcvtzs z2.d, p3/m, z31.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z11.h, z28.h
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z13.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z20.h, z28.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z16.h, z28.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z10.h, z10.h
-; CHECK-NEXT: sel z10.d, p4, z29.d, z12.d
-; CHECK-NEXT: sel z12.d, p11, z29.d, z18.d
-; CHECK-NEXT: fcvtzs z26.d, p5/m, z11.h
-; CHECK-NEXT: fcvtzs z22.d, p2/m, z20.h
-; CHECK-NEXT: fcvtzs z23.d, p3/m, z16.h
-; CHECK-NEXT: mov z10.d, p10/m, #0 // =0x0
-; CHECK-NEXT: mov z12.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.h, p0/z, z11.h, z30.h
-; CHECK-NEXT: fcmge p6.h, p0/z, z19.h, z28.h
-; CHECK-NEXT: str z10, [x8, #7, mul vl]
-; CHECK-NEXT: fcmge p7.h, p0/z, z3.h, z28.h
-; CHECK-NEXT: str z12, [x8, #8, mul vl]
-; CHECK-NEXT: fcmge p2.h, p0/z, z15.h, z28.h
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, p4/m, z29.d
-; CHECK-NEXT: fcmgt p5.h, p0/z, z16.h, z30.h
-; CHECK-NEXT: fcvtzs z14.d, p6/m, z19.h
-; CHECK-NEXT: fcvtzs z17.d, p7/m, z3.h
-; CHECK-NEXT: fcmgt p3.h, p0/z, z20.h, z30.h
-; CHECK-NEXT: fcvtzs z28.d, p2/m, z15.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z11.h, z11.h
-; CHECK-NEXT: sel z11.d, p5, z29.d, z23.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z16.h, z16.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z19.h, z30.h
-; CHECK-NEXT: sel z16.d, p3, z29.d, z22.d
-; CHECK-NEXT: mov z26.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.h, p0/z, z15.h, z30.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z13.h, z30.h
-; CHECK-NEXT: mov z11.d, p2/m, #0 // =0x0
-; CHECK-NEXT: str z26, [x8, #15, mul vl]
-; CHECK-NEXT: sel z26.d, p4, z29.d, z14.d
-; CHECK-NEXT: fcmuo p6.h, p0/z, z20.h, z20.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z3.h, z30.h
-; CHECK-NEXT: str z11, [x8, #14, mul vl]
-; CHECK-NEXT: mov z28.d, p3/m, z29.d
-; CHECK-NEXT: fcmuo p4.h, p0/z, z13.h, z13.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z3.h, z3.h
-; CHECK-NEXT: sel z3.d, p1, z29.d, z21.d
-; CHECK-NEXT: mov z16.d, p6/m, #0 // =0x0
-; CHECK-NEXT: sel z11.d, p2, z29.d, z17.d
-; CHECK-NEXT: fcmgt p12.h, p0/z, z27.h, z30.h
-; CHECK-NEXT: mov z3.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z16, [x8, #13, mul vl]
-; CHECK-NEXT: fcmuo p6.h, p0/z, z15.h, z15.h
-; CHECK-NEXT: mov z11.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.h, p0/z, z4.h, z30.h
-; CHECK-NEXT: str z3, [x8, #11, mul vl]
-; CHECK-NEXT: fcmuo p5.h, p0/z, z19.h, z19.h
-; CHECK-NEXT: mov z9.d, p12/m, z29.d
-; CHECK-NEXT: str z11, [x8, #10, mul vl]
-; CHECK-NEXT: fcmgt p2.h, p0/z, z5.h, z30.h
-; CHECK-NEXT: mov z28.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.h, p0/z, z6.h, z30.h
-; CHECK-NEXT: sel z3.d, p1, z29.d, z7.d
-; CHECK-NEXT: mov z26.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.h, p0/z, z27.h, z27.h
-; CHECK-NEXT: str z28, [x8, #12, mul vl]
-; CHECK-NEXT: fcmgt p6.h, p0/z, z31.h, z30.h
-; CHECK-NEXT: sel z7.d, p2, z29.d, z24.d
-; CHECK-NEXT: str z26, [x8, #9, mul vl]
-; CHECK-NEXT: sel z24.d, p4, z29.d, z25.d
-; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z30.h
-; CHECK-NEXT: fcmuo p5.h, p0/z, z31.h, z31.h
-; CHECK-NEXT: mov z9.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p6/m, z29.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z6.h, z6.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z5.h, z5.h
-; CHECK-NEXT: str z9, [x8, #5, mul vl]
-; CHECK-NEXT: mov z0.d, p1/m, z29.d
-; CHECK-NEXT: mov z2.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p4.h, p0/z, z4.h, z4.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: mov z24.d, p2/m, #0 // =0x0
-; CHECK-NEXT: str z2, [x8, #6, mul vl]
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z24, [x8, #3, mul vl]
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z7, [x8, #2, mul vl]
-; CHECK-NEXT: str z3, [x8, #1, mul vl]
+; CHECK-NEXT: frintx z6.h, p0/m, z6.h
+; CHECK-NEXT: frintx z3.h, p0/m, z3.h
+; CHECK-NEXT: frintx z26.h, p0/m, z26.h
+; CHECK-NEXT: frintx z7.h, p0/m, z7.h
+; CHECK-NEXT: frintx z27.h, p0/m, z27.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
+; CHECK-NEXT: frintx z28.h, p0/m, z28.h
+; CHECK-NEXT: frintx z29.h, p0/m, z29.h
+; CHECK-NEXT: frintx z25.h, p0/m, z25.h
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.h
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.h
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.h
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.h
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.h
+; CHECK-NEXT: str z5, [x8, #15, mul vl]
+; CHECK-NEXT: uunpkhi z5.d, z1.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: str z4, [x8, #14, mul vl]
+; CHECK-NEXT: uunpkhi z4.d, z0.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: str z3, [x8, #12, mul vl]
+; CHECK-NEXT: uunpklo z3.d, z24.s
+; CHECK-NEXT: str z6, [x8, #13, mul vl]
+; CHECK-NEXT: str z26, [x8, #11, mul vl]
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
+; CHECK-NEXT: frintx z1.h, p0/m, z1.h
+; CHECK-NEXT: str z7, [x8, #10, mul vl]
+; CHECK-NEXT: frintx z4.h, p0/m, z4.h
+; CHECK-NEXT: frintx z0.h, p0/m, z0.h
+; CHECK-NEXT: str z27, [x8, #9, mul vl]
+; CHECK-NEXT: frintx z3.h, p0/m, z3.h
+; CHECK-NEXT: str z2, [x8, #8, mul vl]
+; CHECK-NEXT: str z29, [x8, #7, mul vl]
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: str z25, [x8, #6, mul vl]
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: str z5, [x8, #5, mul vl]
+; CHECK-NEXT: str z1, [x8, #4, mul vl]
+; CHECK-NEXT: str z3, [x8, #2, mul vl]
+; CHECK-NEXT: str z4, [x8, #1, mul vl]
; CHECK-NEXT: str z0, [x8]
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x i64> %a
@@ -514,19 +207,8 @@ define <vscale x 1 x i64> @llrint_v1i64_v1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: llrint_v1i64_v1f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x i64> %a
@@ -537,19 +219,8 @@ define <vscale x 2 x i64> @llrint_v2i64_v2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: llrint_v2i64_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x i64> %a
@@ -561,28 +232,14 @@ define <vscale x 4 x i64> @llrint_v4i64_v4f32(<vscale x 4 x float> %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
; CHECK-NEXT: frintx z1.s, p0/m, z1.s
-; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmuo p3.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z1.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z0.s
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: frintx z2.s, p0/m, z0.s
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.s
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x i64> %a
@@ -592,61 +249,25 @@ declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f32(<vscale x 4 x float>)
define <vscale x 8 x i64> @llrint_v8i64_v8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: llrint_v8i64_v8f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uunpklo z3.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.s, w8
+; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: frintx z2.s, p0/m, z2.s
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z6, z0
-; CHECK-NEXT: frintx z6.s, p0/m, z0.s
+; CHECK-NEXT: movprfx z4, z0
+; CHECK-NEXT: frintx z4.s, p0/m, z0.s
; CHECK-NEXT: frintx z3.s, p0/m, z3.s
-; CHECK-NEXT: frintx z1.s, p0/m, z1.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z2.s, z4.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z4.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z3.s, z4.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z2.s, z25.s
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z2.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z4.s
-; CHECK-NEXT: mov z4.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcvtzs z7.d, p2/m, z6.s
-; CHECK-NEXT: fcvtzs z24.d, p3/m, z3.s
-; CHECK-NEXT: fcmgt p3.s, p0/z, z6.s, z25.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z3.s, z25.s
-; CHECK-NEXT: fcvtzs z26.d, p1/m, z1.s
-; CHECK-NEXT: sel z0.d, p4, z4.d, z5.d
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z25.s
-; CHECK-NEXT: fcmuo p4.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: fcmuo p6.s, p0/z, z3.s, z3.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z2.s, z2.s
-; CHECK-NEXT: sel z2.d, p5, z4.d, z24.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z1.d, p3, z4.d, z7.d
-; CHECK-NEXT: sel z3.d, p1, z4.d, z26.d
-; CHECK-NEXT: mov z2.d, p6/m, #0 // =0x0
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z1.d, p4/m, #0 // =0x0
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z5, z1
+; CHECK-NEXT: frintx z5.s, p0/m, z1.s
+; CHECK-NEXT: movprfx z0, z2
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.s
+; CHECK-NEXT: movprfx z1, z4
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z2, z3
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z3.s
+; CHECK-NEXT: movprfx z3, z5
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z5.s
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x i64> %a
@@ -656,114 +277,43 @@ declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f32(<vscale x 8 x float>)
define <vscale x 16 x i64> @llrint_v16i64_v16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: llrint_v16i64_v16f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-3
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
; CHECK-NEXT: uunpklo z4.d, z0.s
-; CHECK-NEXT: uunpkhi z5.d, z0.s
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: uunpkhi z7.d, z1.s
-; CHECK-NEXT: uunpklo z24.d, z2.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: uunpklo z6.d, z1.s
+; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z5.d, z1.s
+; CHECK-NEXT: uunpkhi z1.d, z1.s
+; CHECK-NEXT: uunpklo z6.d, z2.s
; CHECK-NEXT: uunpkhi z2.d, z2.s
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z25, z4
-; CHECK-NEXT: frintx z25.s, p0/m, z4.s
+; CHECK-NEXT: uunpklo z7.d, z3.s
+; CHECK-NEXT: uunpkhi z3.d, z3.s
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: frintx z4.s, p0/m, z4.s
+; CHECK-NEXT: movprfx z24, z0
+; CHECK-NEXT: frintx z24.s, p0/m, z0.s
; CHECK-NEXT: frintx z5.s, p0/m, z5.s
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: frintx z7.s, p0/m, z7.s
-; CHECK-NEXT: frintx z24.s, p0/m, z24.s
-; CHECK-NEXT: movprfx z30, z2
-; CHECK-NEXT: frintx z30.s, p0/m, z2.s
+; CHECK-NEXT: movprfx z25, z1
+; CHECK-NEXT: frintx z25.s, p0/m, z1.s
; CHECK-NEXT: frintx z6.s, p0/m, z6.s
-; CHECK-NEXT: uunpklo z2.d, z3.s
-; CHECK-NEXT: mov z29.s, w8
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
-; CHECK-NEXT: mov z9.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p5.s, p0/z, z25.s, z4.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z5.s, z4.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z7.s, z4.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z24.s, z4.s
-; CHECK-NEXT: fcvtzs z0.d, p5/m, z25.s
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z5.s
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z7.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z4.s
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z24.s
-; CHECK-NEXT: fcmgt p3.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z30.s, z4.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: movprfx z25, z2
-; CHECK-NEXT: frintx z25.s, p0/m, z2.s
-; CHECK-NEXT: uunpkhi z2.d, z3.s
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z6.s
-; CHECK-NEXT: mov z0.d, p3/m, z9.d
-; CHECK-NEXT: fcmgt p5.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: fcvtzs z31.d, p4/m, z30.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: movprfx z5, z2
-; CHECK-NEXT: frintx z5.s, p0/m, z2.s
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmge p4.s, p0/z, z25.s, z4.s
-; CHECK-NEXT: fcmgt p6.s, p0/z, z6.s, z29.s
-; CHECK-NEXT: mov z1.d, p5/m, z9.d
-; CHECK-NEXT: fcmgt p8.s, p0/z, z7.s, z29.s
-; CHECK-NEXT: fcmuo p10.s, p0/z, z7.s, z7.s
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z8.d, p4/m, z25.s
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: sel z2.d, p6, z9.d, z26.d
-; CHECK-NEXT: sel z3.d, p8, z9.d, z27.d
-; CHECK-NEXT: fcmge p4.s, p0/z, z5.s, z4.s
-; CHECK-NEXT: fcmgt p9.s, p0/z, z24.s, z29.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z30.s, z29.s
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmgt p6.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcvtzs z7.d, p4/m, z5.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: sel z4.d, p9, z9.d, z28.d
-; CHECK-NEXT: fcmuo p7.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: sel z6.d, p6, z9.d, z8.d
-; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p8.s, p0/z, z30.s, z30.s
-; CHECK-NEXT: fcmuo p9.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: mov z7.d, p4/m, z9.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z2.d, p7/m, #0 // =0x0
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p3.s, p0/z, z24.s, z24.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: sel z5.d, p5, z9.d, z31.d
-; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #3
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z26, z2
+; CHECK-NEXT: frintx z26.s, p0/m, z2.s
+; CHECK-NEXT: frintx z7.s, p0/m, z7.s
+; CHECK-NEXT: movprfx z27, z3
+; CHECK-NEXT: frintx z27.s, p0/m, z3.s
+; CHECK-NEXT: movprfx z0, z4
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z1, z24
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z24.s
+; CHECK-NEXT: movprfx z2, z5
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z5.s
+; CHECK-NEXT: movprfx z3, z25
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z25.s
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z6.s
+; CHECK-NEXT: movprfx z5, z26
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z26.s
+; CHECK-NEXT: movprfx z6, z7
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z7.s
+; CHECK-NEXT: movprfx z7, z27
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z27.s
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x i64> %a
@@ -773,251 +323,71 @@ declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f32(<vscale x 16 x float>
define <vscale x 32 x i64> @llrint_v32i64_v32f32(<vscale x 32 x float> %x) {
; CHECK-LABEL: llrint_v32i64_v32f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x98, 0x01, 0x1e, 0x22 // sp + 16 + 152 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: uunpklo z24.d, z0.s
-; CHECK-NEXT: uunpklo z26.d, z1.s
-; CHECK-NEXT: mov w9, #-553648128 // =0xdf000000
-; CHECK-NEXT: uunpklo z28.d, z2.s
-; CHECK-NEXT: uunpkhi z30.d, z2.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: uunpkhi z25.d, z0.s
-; CHECK-NEXT: uunpkhi z13.d, z3.s
-; CHECK-NEXT: uunpklo z14.d, z4.s
-; CHECK-NEXT: uunpkhi z27.d, z1.s
-; CHECK-NEXT: uunpklo z9.d, z3.s
-; CHECK-NEXT: mov z29.s, w9
-; CHECK-NEXT: movprfx z0, z24
-; CHECK-NEXT: frintx z0.s, p0/m, z24.s
-; CHECK-NEXT: movprfx z24, z26
-; CHECK-NEXT: frintx z24.s, p0/m, z26.s
-; CHECK-NEXT: mov w9, #1593835519 // =0x5effffff
-; CHECK-NEXT: movprfx z10, z28
-; CHECK-NEXT: frintx z10.s, p0/m, z28.s
-; CHECK-NEXT: frintx z30.s, p0/m, z30.s
-; CHECK-NEXT: uunpklo z17.d, z5.s
-; CHECK-NEXT: movprfx z1, z25
-; CHECK-NEXT: frintx z1.s, p0/m, z25.s
-; CHECK-NEXT: movprfx z15, z13
-; CHECK-NEXT: frintx z15.s, p0/m, z13.s
-; CHECK-NEXT: movprfx z13, z14
-; CHECK-NEXT: frintx z13.s, p0/m, z14.s
-; CHECK-NEXT: uunpkhi z14.d, z4.s
-; CHECK-NEXT: uunpkhi z18.d, z5.s
-; CHECK-NEXT: uunpkhi z19.d, z6.s
-; CHECK-NEXT: movprfx z25, z27
-; CHECK-NEXT: frintx z25.s, p0/m, z27.s
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: mov z11.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p3.s, p0/z, z24.s, z29.s
-; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p5.s, p0/z, z10.s, z29.s
-; CHECK-NEXT: frintx z9.s, p0/m, z9.s
-; CHECK-NEXT: uunpklo z20.d, z7.s
-; CHECK-NEXT: movprfx z5, z14
-; CHECK-NEXT: frintx z5.s, p0/m, z14.s
-; CHECK-NEXT: movprfx z14, z17
-; CHECK-NEXT: frintx z14.s, p0/m, z17.s
-; CHECK-NEXT: movprfx z17, z18
-; CHECK-NEXT: frintx z17.s, p0/m, z18.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z30.s, z29.s
-; CHECK-NEXT: uunpkhi z7.d, z7.s
-; CHECK-NEXT: mov z31.s, w9
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: frintx z19.s, p0/m, z19.s
+; CHECK-NEXT: uunpkhi z24.d, z7.s
+; CHECK-NEXT: uunpkhi z25.d, z6.s
; CHECK-NEXT: uunpklo z6.d, z6.s
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z24.s
-; CHECK-NEXT: fcvtzs z11.d, p5/m, z10.s
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z16.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z22, z7
-; CHECK-NEXT: frintx z22.s, p0/m, z7.s
-; CHECK-NEXT: fcvtzs z12.d, p6/m, z30.s
-; CHECK-NEXT: frintx z20.s, p0/m, z20.s
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: uunpkhi z26.d, z5.s
+; CHECK-NEXT: uunpklo z5.d, z5.s
+; CHECK-NEXT: uunpkhi z27.d, z4.s
+; CHECK-NEXT: uunpkhi z28.d, z1.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpkhi z29.d, z3.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: frintx z24.s, p0/m, z24.s
; CHECK-NEXT: frintx z6.s, p0/m, z6.s
-; CHECK-NEXT: mov z3.d, #0x7fffffffffffffff
-; CHECK-NEXT: mov z18.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z29.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, z29.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcmgt p9.s, p0/z, z10.s, z31.s
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z1.s
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z25.s
-; CHECK-NEXT: mov z11.d, p9/m, z3.d
-; CHECK-NEXT: fcmuo p8.s, p0/z, z10.s, z10.s
-; CHECK-NEXT: mov z10.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p5.s, p0/z, z9.s, z29.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z15.s, z29.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z13.s, z29.s
-; CHECK-NEXT: mov z11.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcvtzs z10.d, p5/m, z9.s
-; CHECK-NEXT: fcvtzs z4.d, p3/m, z15.s
-; CHECK-NEXT: fcvtzs z16.d, p6/m, z13.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z17.s, z29.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z19.s, z29.s
-; CHECK-NEXT: fcmgt p12.s, p0/z, z30.s, z31.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z15.s, z31.s
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z17.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z20.s, z29.s
-; CHECK-NEXT: fcvtzs z23.d, p2/m, z19.s
-; CHECK-NEXT: sel z7.d, p12, z3.d, z12.d
-; CHECK-NEXT: fcmgt p11.s, p0/z, z13.s, z31.s
-; CHECK-NEXT: mov z4.d, p5/m, z3.d
-; CHECK-NEXT: fcmge p4.s, p0/z, z22.s, z29.s
-; CHECK-NEXT: fcvtzs z0.d, p3/m, z20.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: fcmge p7.s, p0/z, z14.s, z29.s
-; CHECK-NEXT: sel z12.d, p11, z3.d, z16.d
-; CHECK-NEXT: fcvtzs z8.d, p4/m, z22.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z13.s, z13.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z29.s
-; CHECK-NEXT: mov z29.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z18.d, p7/m, z14.s
-; CHECK-NEXT: fcmuo p10.s, p0/z, z15.s, z15.s
-; CHECK-NEXT: mov z15.d, #0x8000000000000000
-; CHECK-NEXT: mov z12.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.s, p0/z, z22.s, z31.s
-; CHECK-NEXT: fcvtzs z29.d, p2/m, z6.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z20.s, z31.s
-; CHECK-NEXT: str z12, [x8, #8, mul vl]
-; CHECK-NEXT: fcvtzs z15.d, p6/m, z5.s
-; CHECK-NEXT: mov z4.d, p10/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.s, p0/z, z19.s, z31.s
-; CHECK-NEXT: mov z8.d, p4/m, z3.d
-; CHECK-NEXT: fcmuo p1.s, p0/z, z22.s, z22.s
-; CHECK-NEXT: str z4, [x8, #7, mul vl]
-; CHECK-NEXT: mov z0.d, p5/m, z3.d
-; CHECK-NEXT: fcmuo p2.s, p0/z, z20.s, z20.s
-; CHECK-NEXT: fcmuo p6.s, p0/z, z19.s, z19.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z5.s, z31.s
-; CHECK-NEXT: mov z8.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p5.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: sel z5.d, p3, z3.d, z23.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.s, p0/z, z6.s, z31.s
-; CHECK-NEXT: str z8, [x8, #15, mul vl]
-; CHECK-NEXT: fcmgt p1.s, p0/z, z17.s, z31.s
-; CHECK-NEXT: str z0, [x8, #14, mul vl]
-; CHECK-NEXT: mov z5.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p2.s, p0/z, z14.s, z31.s
-; CHECK-NEXT: sel z0.d, p3, z3.d, z29.d
-; CHECK-NEXT: fcmuo p6.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: str z5, [x8, #13, mul vl]
-; CHECK-NEXT: sel z6.d, p4, z3.d, z15.d
-; CHECK-NEXT: sel z5.d, p1, z3.d, z21.d
-; CHECK-NEXT: fcmuo p4.s, p0/z, z17.s, z17.s
-; CHECK-NEXT: sel z29.d, p2, z3.d, z18.d
-; CHECK-NEXT: mov z6.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.s, p0/z, z14.s, z14.s
-; CHECK-NEXT: mov z0.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z31.s
-; CHECK-NEXT: str z6, [x8, #9, mul vl]
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z0, [x8, #12, mul vl]
-; CHECK-NEXT: mov z29.d, p3/m, #0 // =0x0
-; CHECK-NEXT: str z5, [x8, #11, mul vl]
-; CHECK-NEXT: sel z5.d, p1, z3.d, z26.d
-; CHECK-NEXT: fcmgt p2.s, p0/z, z24.s, z31.s
-; CHECK-NEXT: str z29, [x8, #10, mul vl]
-; CHECK-NEXT: ldr z4, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: str z11, [x8, #4, mul vl]
-; CHECK-NEXT: fcmgt p4.s, p0/z, z25.s, z31.s
-; CHECK-NEXT: fcmuo p3.s, p0/z, z30.s, z30.s
-; CHECK-NEXT: sel z26.d, p2, z3.d, z27.d
-; CHECK-NEXT: fcmgt p6.s, p0/z, z9.s, z31.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z4.s, z31.s
-; CHECK-NEXT: fcmuo p5.s, p0/z, z9.s, z9.s
-; CHECK-NEXT: sel z6.d, p4, z3.d, z28.d
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p2.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: sel z0.d, p6, z3.d, z10.d
-; CHECK-NEXT: fcmuo p3.s, p0/z, z24.s, z24.s
-; CHECK-NEXT: fcmuo p4.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z1.d, p1, z3.d, z2.d
-; CHECK-NEXT: str z7, [x8, #5, mul vl]
-; CHECK-NEXT: fcmuo p0.s, p0/z, z4.s, z4.s
-; CHECK-NEXT: mov z0.d, p5/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z26.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z0, [x8, #6, mul vl]
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z6, [x8, #3, mul vl]
-; CHECK-NEXT: str z26, [x8, #2, mul vl]
-; CHECK-NEXT: str z5, [x8, #1, mul vl]
-; CHECK-NEXT: str z1, [x8]
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: frintx z7.s, p0/m, z7.s
+; CHECK-NEXT: frintx z25.s, p0/m, z25.s
+; CHECK-NEXT: frintx z26.s, p0/m, z26.s
+; CHECK-NEXT: frintx z5.s, p0/m, z5.s
+; CHECK-NEXT: frintx z27.s, p0/m, z27.s
+; CHECK-NEXT: frintx z28.s, p0/m, z28.s
+; CHECK-NEXT: frintx z4.s, p0/m, z4.s
+; CHECK-NEXT: frintx z29.s, p0/m, z29.s
+; CHECK-NEXT: frintx z3.s, p0/m, z3.s
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.s
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-NEXT: frintx z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.s
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.s
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.s
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.s
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.s
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.s
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.s
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.s
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.s
+; CHECK-NEXT: str z24, [x8, #15, mul vl]
+; CHECK-NEXT: uunpkhi z24.d, z2.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: str z6, [x8, #12, mul vl]
+; CHECK-NEXT: uunpkhi z6.d, z0.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: str z7, [x8, #14, mul vl]
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
+; CHECK-NEXT: str z25, [x8, #13, mul vl]
+; CHECK-NEXT: str z26, [x8, #11, mul vl]
+; CHECK-NEXT: frintx z24.s, p0/m, z24.s
+; CHECK-NEXT: frintx z2.s, p0/m, z2.s
+; CHECK-NEXT: str z5, [x8, #10, mul vl]
+; CHECK-NEXT: frintx z6.s, p0/m, z6.s
+; CHECK-NEXT: frintx z0.s, p0/m, z0.s
+; CHECK-NEXT: str z27, [x8, #9, mul vl]
+; CHECK-NEXT: str z4, [x8, #8, mul vl]
+; CHECK-NEXT: str z29, [x8, #7, mul vl]
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.s
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.s
+; CHECK-NEXT: str z3, [x8, #6, mul vl]
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: str z1, [x8, #2, mul vl]
+; CHECK-NEXT: str z24, [x8, #5, mul vl]
+; CHECK-NEXT: str z2, [x8, #4, mul vl]
+; CHECK-NEXT: str z6, [x8, #1, mul vl]
+; CHECK-NEXT: str z0, [x8]
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv32f32(<vscale x 32 x float> %x)
ret <vscale x 32 x i64> %a
@@ -1028,19 +398,8 @@ define <vscale x 1 x i64> @llrint_v1i64_v1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: llrint_v1i64_v1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x i64> %a
@@ -1051,19 +410,8 @@ define <vscale x 2 x i64> @llrint_v2i64_v2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: llrint_v2i64_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x i64> %a
@@ -1074,27 +422,10 @@ define <vscale x 4 x i64> @llrint_v4i64_v4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: llrint_v4i64_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fcmuo p3.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z1.d
-; CHECK-NEXT: fcmgt p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x i64> %a
@@ -1104,56 +435,15 @@ declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double>)
define <vscale x 8 x i64> @llrint_v8i64_v8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: llrint_v8i64_v8f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
-; CHECK-NEXT: mov z24.d, x8
; CHECK-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z5.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z5.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z2.d, z5.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z0.d, z24.d
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z3.d, z5.d
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z6.d, p2/m, z1.d
-; CHECK-NEXT: fcvtzs z7.d, p3/m, z2.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z24.d
-; CHECK-NEXT: sel z0.d, p4, z25.d, z4.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z2.d, z24.d
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z3.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z24.d
-; CHECK-NEXT: fcmuo p5.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: sel z1.d, p3, z25.d, z6.d
-; CHECK-NEXT: fcmuo p6.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: sel z2.d, p4, z25.d, z7.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: sel z3.d, p1, z25.d, z5.d
-; CHECK-NEXT: mov z1.d, p5/m, #0 // =0x0
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z2.d, p6/m, #0 // =0x0
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x i64> %a
@@ -1163,103 +453,23 @@ declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f64(<vscale x 8 x double>)
define <vscale x 16 x i64> @llrint_v16f64(<vscale x 16 x double> %x) {
; CHECK-LABEL: llrint_v16f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-3
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: frintx z24.d, p0/m, z0.d
-; CHECK-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-NEXT: mov z0.d, x8
+; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-NEXT: frintx z3.d, p0/m, z3.d
; CHECK-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-NEXT: mov z30.d, x8
-; CHECK-NEXT: mov z29.d, #0x8000000000000000
; CHECK-NEXT: frintx z5.d, p0/m, z5.d
+; CHECK-NEXT: frintx z6.d, p0/m, z6.d
; CHECK-NEXT: frintx z7.d, p0/m, z7.d
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x7fffffffffffffff
-; CHECK-NEXT: mov z9.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.d, p0/z, z24.d, z0.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z3.d, z0.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z0.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z2.d, z0.d
-; CHECK-NEXT: fcvtzs z25.d, p1/m, z24.d
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z3.d
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z1.d
-; CHECK-NEXT: fcmge p5.d, p0/z, z4.d, z0.d
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z2.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z24.d, z30.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z24.d, z24.d
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p7.d, p0/z, z6.d, z0.d
-; CHECK-NEXT: fcvtzs z29.d, p5/m, z4.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z5.d, z0.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z1.d, z30.d
-; CHECK-NEXT: fcvtzs z24.d, p7/m, z6.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z2.d, z30.d
-; CHECK-NEXT: fcmge p7.d, p0/z, z7.d, z0.d
-; CHECK-NEXT: fcvtzs z31.d, p3/m, z5.d
-; CHECK-NEXT: sel z0.d, p4, z8.d, z25.d
-; CHECK-NEXT: fcmgt p8.d, p0/z, z3.d, z30.d
-; CHECK-NEXT: fcmgt p9.d, p0/z, z4.d, z30.d
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcvtzs z9.d, p7/m, z7.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z1.d, p5, z8.d, z26.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: sel z2.d, p6, z8.d, z27.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z5.d, z30.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z6.d, z30.d
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p7.d, p0/z, z7.d, z30.d
-; CHECK-NEXT: fcmuo p10.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: sel z3.d, p8, z8.d, z28.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z4.d, z4.d
-; CHECK-NEXT: sel z4.d, p9, z8.d, z29.d
-; CHECK-NEXT: fcmuo p8.d, p0/z, z5.d, z5.d
-; CHECK-NEXT: sel z5.d, p5, z8.d, z31.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p9.d, p0/z, z6.d, z6.d
-; CHECK-NEXT: sel z6.d, p6, z8.d, z24.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p4/m, #0 // =0x0
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.d, p0/z, z7.d, z7.d
-; CHECK-NEXT: sel z7.d, p7, z8.d, z9.d
-; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #3
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f64(<vscale x 16 x double> %x)
ret <vscale x 16 x i64> %a
@@ -1269,242 +479,71 @@ declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f64(<vscale x 16 x double
define <vscale x 32 x i64> @llrint_v32f64(<vscale x 32 x double> %x) {
; CHECK-LABEL: llrint_v32f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x90, 0x01, 0x1e, 0x22 // sp + 16 + 144 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: ldr z0, [x0]
-; CHECK-NEXT: ldr z7, [x0, #3, mul vl]
+; CHECK-NEXT: ldr z0, [x0, #15, mul vl]
+; CHECK-NEXT: ldr z1, [x0, #14, mul vl]
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ldr z27, [x0, #4, mul vl]
-; CHECK-NEXT: ldr z4, [x0, #2, mul vl]
-; CHECK-NEXT: mov x9, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z25.d, x9
-; CHECK-NEXT: ldr z2, [x0, #1, mul vl]
-; CHECK-NEXT: ldr z29, [x0, #6, mul vl]
+; CHECK-NEXT: ldr z2, [x0, #13, mul vl]
+; CHECK-NEXT: ldr z3, [x0, #12, mul vl]
+; CHECK-NEXT: ldr z4, [x0, #11, mul vl]
+; CHECK-NEXT: ldr z5, [x0, #10, mul vl]
+; CHECK-NEXT: ldr z6, [x0, #9, mul vl]
+; CHECK-NEXT: ldr z7, [x0, #8, mul vl]
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: frintx z7.d, p0/m, z7.d
-; CHECK-NEXT: ldr z31, [x0, #7, mul vl]
-; CHECK-NEXT: movprfx z14, z27
-; CHECK-NEXT: frintx z14.d, p0/m, z27.d
+; CHECK-NEXT: frintx z1.d, p0/m, z1.d
+; CHECK-NEXT: ldr z24, [x0, #7, mul vl]
+; CHECK-NEXT: ldr z25, [x0, #6, mul vl]
+; CHECK-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-NEXT: frintx z3.d, p0/m, z3.d
+; CHECK-NEXT: ldr z26, [x0, #5, mul vl]
+; CHECK-NEXT: ldr z27, [x0, #4, mul vl]
; CHECK-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-NEXT: ldr z27, [x0, #5, mul vl]
-; CHECK-NEXT: ldr z15, [x0, #8, mul vl]
-; CHECK-NEXT: mov x9, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: movprfx z3, z2
-; CHECK-NEXT: frintx z3.d, p0/m, z2.d
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: mov z30.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z25.d
-; CHECK-NEXT: movprfx z28, z27
-; CHECK-NEXT: frintx z28.d, p0/m, z27.d
+; CHECK-NEXT: ldr z28, [x0, #3, mul vl]
+; CHECK-NEXT: ldr z29, [x0, #2, mul vl]
+; CHECK-NEXT: frintx z5.d, p0/m, z5.d
+; CHECK-NEXT: ldr z30, [x0, #1, mul vl]
+; CHECK-NEXT: ldr z31, [x0]
+; CHECK-NEXT: frintx z6.d, p0/m, z6.d
+; CHECK-NEXT: frintx z7.d, p0/m, z7.d
+; CHECK-NEXT: frintx z24.d, p0/m, z24.d
+; CHECK-NEXT: frintx z25.d, p0/m, z25.d
+; CHECK-NEXT: frintx z26.d, p0/m, z26.d
+; CHECK-NEXT: frintx z27.d, p0/m, z27.d
+; CHECK-NEXT: frintx z28.d, p0/m, z28.d
; CHECK-NEXT: frintx z29.d, p0/m, z29.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z7.d, z25.d
-; CHECK-NEXT: mov z1.d, x9
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p3.d, p0/z, z14.d, z25.d
-; CHECK-NEXT: ldr z11, [x0, #13, mul vl]
-; CHECK-NEXT: ldr z18, [x0, #11, mul vl]
-; CHECK-NEXT: fcmge p5.d, p0/z, z4.d, z25.d
-; CHECK-NEXT: ldr z19, [x0, #9, mul vl]
-; CHECK-NEXT: movprfx z20, z31
-; CHECK-NEXT: frintx z20.d, p0/m, z31.d
-; CHECK-NEXT: frintx z15.d, p0/m, z15.d
-; CHECK-NEXT: ldr z9, [x0, #15, mul vl]
-; CHECK-NEXT: ldr z10, [x0, #14, mul vl]
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcvtzs z24.d, p2/m, z7.d
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z30.d, p3/m, z14.d
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: frintx z18.d, p0/m, z18.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z28.d, z25.d
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: ldr z8, [x0, #12, mul vl]
-; CHECK-NEXT: fcmgt p10.d, p0/z, z14.d, z1.d
-; CHECK-NEXT: ldr z13, [x0, #10, mul vl]
-; CHECK-NEXT: fcvtzs z6.d, p5/m, z4.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z29.d, z25.d
-; CHECK-NEXT: mov z16.d, #0x8000000000000000
-; CHECK-NEXT: mov z17.d, #0x8000000000000000
-; CHECK-NEXT: frintx z10.d, p0/m, z10.d
-; CHECK-NEXT: frintx z9.d, p0/m, z9.d
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z12.d, p1/m, z28.d
-; CHECK-NEXT: frintx z13.d, p0/m, z13.d
-; CHECK-NEXT: mov z22.d, #0x8000000000000000
-; CHECK-NEXT: frintx z8.d, p0/m, z8.d
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcvtzs z31.d, p2/m, z29.d
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: fcmuo p8.d, p0/z, z14.d, z14.d
-; CHECK-NEXT: movprfx z14, z19
-; CHECK-NEXT: frintx z14.d, p0/m, z19.d
-; CHECK-NEXT: movprfx z19, z11
-; CHECK-NEXT: frintx z19.d, p0/m, z11.d
-; CHECK-NEXT: mov z11.d, #0x8000000000000000
-; CHECK-NEXT: mov z30.d, p10/m, z27.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z3.d, z25.d
-; CHECK-NEXT: fcmge p5.d, p0/z, z20.d, z25.d
-; CHECK-NEXT: mov z30.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcmge p6.d, p0/z, z15.d, z25.d
-; CHECK-NEXT: fcvtzs z5.d, p4/m, z3.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z18.d, z25.d
-; CHECK-NEXT: str z30, [x8, #4, mul vl]
-; CHECK-NEXT: fcvtzs z16.d, p5/m, z20.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z19.d, z25.d
-; CHECK-NEXT: fcvtzs z17.d, p6/m, z15.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z20.d, z1.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z10.d, z25.d
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z18.d
-; CHECK-NEXT: fcvtzs z22.d, p2/m, z19.d
-; CHECK-NEXT: fcmgt p11.d, p0/z, z15.d, z1.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z9.d, z25.d
-; CHECK-NEXT: fcmge p6.d, p0/z, z14.d, z25.d
-; CHECK-NEXT: fcvtzs z23.d, p3/m, z10.d
-; CHECK-NEXT: fcmge p7.d, p0/z, z13.d, z25.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z15.d, z15.d
-; CHECK-NEXT: sel z15.d, p5, z27.d, z16.d
-; CHECK-NEXT: sel z16.d, p11, z27.d, z17.d
-; CHECK-NEXT: fcvtzs z26.d, p4/m, z9.d
-; CHECK-NEXT: fcvtzs z11.d, p6/m, z14.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z8.d, z25.d
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z16.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.d, p0/z, z9.d, z1.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z10.d, z1.d
-; CHECK-NEXT: str z16, [x8, #8, mul vl]
-; CHECK-NEXT: fcvtzs z25.d, p2/m, z8.d
-; CHECK-NEXT: fcmgt p3.d, p0/z, z19.d, z1.d
-; CHECK-NEXT: fcmuo p9.d, p0/z, z20.d, z20.d
-; CHECK-NEXT: mov z20.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, p4/m, z27.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z9.d, z9.d
-; CHECK-NEXT: sel z9.d, p5, z27.d, z23.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z10.d, z10.d
-; CHECK-NEXT: sel z10.d, p3, z27.d, z22.d
-; CHECK-NEXT: fcvtzs z20.d, p7/m, z13.d
-; CHECK-NEXT: mov z15.d, p9/m, #0 // =0x0
-; CHECK-NEXT: mov z26.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z9.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.d, p0/z, z14.d, z1.d
-; CHECK-NEXT: str z15, [x8, #7, mul vl]
-; CHECK-NEXT: fcmgt p3.d, p0/z, z8.d, z1.d
-; CHECK-NEXT: str z26, [x8, #15, mul vl]
-; CHECK-NEXT: fcmuo p6.d, p0/z, z19.d, z19.d
-; CHECK-NEXT: str z9, [x8, #14, mul vl]
-; CHECK-NEXT: fcmgt p1.d, p0/z, z18.d, z1.d
-; CHECK-NEXT: fcmgt p2.d, p0/z, z13.d, z1.d
-; CHECK-NEXT: sel z26.d, p4, z27.d, z11.d
-; CHECK-NEXT: mov z25.d, p3/m, z27.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z18.d, z18.d
-; CHECK-NEXT: mov z10.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.d, p0/z, z13.d, z13.d
-; CHECK-NEXT: sel z9.d, p2, z27.d, z20.d
-; CHECK-NEXT: fcmgt p12.d, p0/z, z28.d, z1.d
-; CHECK-NEXT: str z10, [x8, #13, mul vl]
-; CHECK-NEXT: fcmuo p6.d, p0/z, z8.d, z8.d
-; CHECK-NEXT: sel z8.d, p1, z27.d, z21.d
-; CHECK-NEXT: mov z9.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z1.d
-; CHECK-NEXT: fcmuo p5.d, p0/z, z14.d, z14.d
-; CHECK-NEXT: mov z8.d, p4/m, #0 // =0x0
-; CHECK-NEXT: mov z12.d, p12/m, z27.d
-; CHECK-NEXT: str z9, [x8, #10, mul vl]
-; CHECK-NEXT: mov z25.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p2.d, p0/z, z4.d, z1.d
-; CHECK-NEXT: str z8, [x8, #11, mul vl]
-; CHECK-NEXT: mov z5.d, p1/m, z27.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z7.d, z1.d
-; CHECK-NEXT: str z25, [x8, #12, mul vl]
-; CHECK-NEXT: mov z26.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.d, p0/z, z28.d, z28.d
-; CHECK-NEXT: mov z6.d, p2/m, z27.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z29.d, z1.d
-; CHECK-NEXT: str z26, [x8, #9, mul vl]
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z24.d, p4/m, z27.d
-; CHECK-NEXT: mov z12.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p5.d, p0/z, z29.d, z29.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z7.d, z7.d
-; CHECK-NEXT: sel z25.d, p6, z27.d, z31.d
-; CHECK-NEXT: str z12, [x8, #5, mul vl]
-; CHECK-NEXT: fcmuo p3.d, p0/z, z4.d, z4.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: mov z25.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z27.d, z2.d
-; CHECK-NEXT: mov z24.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p3/m, #0 // =0x0
+; CHECK-NEXT: frintx z30.d, p0/m, z30.d
+; CHECK-NEXT: frintx z31.d, p0/m, z31.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.d
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.d
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.d
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.d
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.d
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.d
+; CHECK-NEXT: fcvtzs z30.d, p0/m, z30.d
+; CHECK-NEXT: fcvtzs z31.d, p0/m, z31.d
+; CHECK-NEXT: str z0, [x8, #15, mul vl]
+; CHECK-NEXT: str z1, [x8, #14, mul vl]
+; CHECK-NEXT: str z2, [x8, #13, mul vl]
+; CHECK-NEXT: str z3, [x8, #12, mul vl]
+; CHECK-NEXT: str z4, [x8, #11, mul vl]
+; CHECK-NEXT: str z5, [x8, #10, mul vl]
+; CHECK-NEXT: str z6, [x8, #9, mul vl]
+; CHECK-NEXT: str z7, [x8, #8, mul vl]
+; CHECK-NEXT: str z24, [x8, #7, mul vl]
; CHECK-NEXT: str z25, [x8, #6, mul vl]
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z24, [x8, #3, mul vl]
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z6, [x8, #2, mul vl]
-; CHECK-NEXT: str z5, [x8, #1, mul vl]
-; CHECK-NEXT: str z0, [x8]
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: str z26, [x8, #5, mul vl]
+; CHECK-NEXT: str z27, [x8, #4, mul vl]
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: str z29, [x8, #2, mul vl]
+; CHECK-NEXT: str z30, [x8, #1, mul vl]
+; CHECK-NEXT: str z31, [x8]
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv16f64(<vscale x 32 x double> %x)
ret <vscale x 32 x i64> %a
diff --git a/llvm/test/CodeGen/AArch64/sve-lrint.ll b/llvm/test/CodeGen/AArch64/sve-lrint.ll
index c6a6a693cca02..889d4a1c8f73a 100644
--- a/llvm/test/CodeGen/AArch64/sve-lrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-lrint.ll
@@ -5,18 +5,8 @@ define <vscale x 1 x i64> @lrint_v1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: lrint_v1f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.lrint.nxv1i64.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x i64> %a
@@ -26,18 +16,8 @@ define <vscale x 2 x i64> @lrint_v2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: lrint_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.lrint.nxv2i64.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x i64> %a
@@ -48,27 +28,14 @@ define <vscale x 4 x i64> @lrint_v4f16(<vscale x 4 x half> %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
; CHECK-NEXT: frintx z1.h, p0/m, z1.h
-; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z2.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmuo p3.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z1.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z2.h
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z0.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: frintx z2.h, p0/m, z0.h
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.lrint.nxv4i64.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x i64> %a
@@ -77,62 +44,25 @@ define <vscale x 4 x i64> @lrint_v4f16(<vscale x 4 x half> %x) {
define <vscale x 8 x i64> @lrint_v8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: lrint_v8f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: uunpklo z1.s, z0.h
; CHECK-NEXT: uunpkhi z0.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z4.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.d, #0x7fffffffffffffff
; CHECK-NEXT: uunpklo z2.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
; CHECK-NEXT: uunpklo z3.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: frintx z2.h, p0/m, z2.h
; CHECK-NEXT: frintx z1.h, p0/m, z1.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
; CHECK-NEXT: frintx z3.h, p0/m, z3.h
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: frintx z24.h, p0/m, z0.h
-; CHECK-NEXT: mov z0.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z4.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z1.h, z4.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z3.h, z4.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z1.h, z0.h
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z2.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z24.h, z4.h
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z6.d, p2/m, z1.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z2.h, z0.h
-; CHECK-NEXT: fcvtzs z7.d, p3/m, z3.h
-; CHECK-NEXT: fcmgt p5.h, p0/z, z3.h, z0.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z24.h, z0.h
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z24.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z2.h, z2.h
-; CHECK-NEXT: sel z0.d, p2, z25.d, z5.d
-; CHECK-NEXT: fcmuo p1.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: sel z1.d, p4, z25.d, z6.d
-; CHECK-NEXT: sel z2.d, p5, z25.d, z7.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z3.h, z3.h
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.h, p0/z, z24.h, z24.h
-; CHECK-NEXT: sel z3.d, p6, z25.d, z4.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z4, z0
+; CHECK-NEXT: frintx z4.h, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z0, z2
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z2, z3
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z3.h
+; CHECK-NEXT: movprfx z3, z4
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z4.h
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.lrint.nxv8i64.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x i64> %a
@@ -141,110 +71,46 @@ define <vscale x 8 x i64> @lrint_v8f16(<vscale x 8 x half> %x) {
define <vscale x 16 x i64> @lrint_v16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: lrint_v16f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: uunpkhi z3.s, z0.h
; CHECK-NEXT: uunpklo z2.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: uunpklo z7.s, z1.h
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z0.h, #-1025 // =0xfffffffffffffbff
+; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z3.s, z1.h
; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z29.h, w8
-; CHECK-NEXT: uunpkhi z25.d, z3.s
+; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: uunpklo z4.d, z2.s
-; CHECK-NEXT: uunpkhi z6.d, z2.s
-; CHECK-NEXT: uunpklo z24.d, z3.s
-; CHECK-NEXT: uunpklo z26.d, z7.s
-; CHECK-NEXT: uunpkhi z7.d, z7.s
-; CHECK-NEXT: uunpklo z30.d, z1.s
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
+; CHECK-NEXT: uunpkhi z2.d, z2.s
+; CHECK-NEXT: uunpklo z5.d, z0.s
+; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z6.d, z3.s
+; CHECK-NEXT: uunpkhi z3.d, z3.s
+; CHECK-NEXT: uunpklo z7.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: movprfx z27, z4
-; CHECK-NEXT: frintx z27.h, p0/m, z4.h
-; CHECK-NEXT: movprfx z28, z6
-; CHECK-NEXT: frintx z28.h, p0/m, z6.h
-; CHECK-NEXT: frintx z25.h, p0/m, z25.h
-; CHECK-NEXT: frintx z24.h, p0/m, z24.h
-; CHECK-NEXT: frintx z26.h, p0/m, z26.h
+; CHECK-NEXT: frintx z4.h, p0/m, z4.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
+; CHECK-NEXT: movprfx z24, z0
+; CHECK-NEXT: frintx z24.h, p0/m, z0.h
+; CHECK-NEXT: frintx z6.h, p0/m, z6.h
+; CHECK-NEXT: movprfx z25, z3
+; CHECK-NEXT: frintx z25.h, p0/m, z3.h
; CHECK-NEXT: frintx z7.h, p0/m, z7.h
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: frintx z30.h, p0/m, z30.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z25.h, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z27.h, z0.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z28.h, z0.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z24.h, z0.h
-; CHECK-NEXT: fcvtzs z5.d, p4/m, z25.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z26.h, z0.h
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z27.h
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z28.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z7.h, z0.h
-; CHECK-NEXT: fcvtzs z4.d, p3/m, z24.h
-; CHECK-NEXT: fcmgt p3.h, p0/z, z27.h, z29.h
-; CHECK-NEXT: fcvtzs z6.d, p5/m, z26.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z27.h, z27.h
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z31.d, p4/m, z7.h
-; CHECK-NEXT: fcmgt p5.h, p0/z, z28.h, z29.h
-; CHECK-NEXT: fcmuo p2.h, p0/z, z28.h, z28.h
-; CHECK-NEXT: movprfx z28, z1
-; CHECK-NEXT: frintx z28.h, p0/m, z1.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z30.h, z0.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z24.h, z29.h
-; CHECK-NEXT: fcmuo p7.h, p0/z, z24.h, z24.h
-; CHECK-NEXT: mov z24.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p8.h, p0/z, z25.h, z29.h
-; CHECK-NEXT: fcvtzs z27.d, p4/m, z30.h
-; CHECK-NEXT: fcmuo p10.h, p0/z, z25.h, z25.h
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: sel z1.d, p5, z24.d, z3.d
-; CHECK-NEXT: fcmge p4.h, p0/z, z28.h, z0.h
-; CHECK-NEXT: sel z0.d, p3, z24.d, z2.d
-; CHECK-NEXT: sel z2.d, p6, z24.d, z4.d
-; CHECK-NEXT: sel z3.d, p8, z24.d, z5.d
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p9.h, p0/z, z26.h, z29.h
-; CHECK-NEXT: mov z2.d, p7/m, #0 // =0x0
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcvtzs z25.d, p4/m, z28.h
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p5.h, p0/z, z7.h, z29.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z30.h, z29.h
-; CHECK-NEXT: sel z4.d, p9, z24.d, z6.d
-; CHECK-NEXT: fcmgt p4.h, p0/z, z28.h, z29.h
-; CHECK-NEXT: fcmuo p8.h, p0/z, z7.h, z7.h
-; CHECK-NEXT: sel z5.d, p5, z24.d, z31.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p9.h, p0/z, z30.h, z30.h
-; CHECK-NEXT: sel z6.d, p6, z24.d, z27.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: sel z7.d, p4, z24.d, z25.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p3.h, p0/z, z26.h, z26.h
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.h, p0/z, z28.h, z28.h
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z26, z1
+; CHECK-NEXT: frintx z26.h, p0/m, z1.h
+; CHECK-NEXT: movprfx z0, z4
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z4.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z2, z5
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z5.h
+; CHECK-NEXT: movprfx z3, z24
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z24.h
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z6.h
+; CHECK-NEXT: movprfx z5, z25
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z25.h
+; CHECK-NEXT: movprfx z6, z7
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z7.h
+; CHECK-NEXT: movprfx z7, z26
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z26.h
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.lrint.nxv16i64.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x i64> %a
@@ -253,252 +119,79 @@ define <vscale x 16 x i64> @lrint_v16f16(<vscale x 16 x half> %x) {
define <vscale x 32 x i64> @lrint_v32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: lrint_v32f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x90, 0x01, 0x1e, 0x22 // sp + 16 + 144 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: uunpklo z4.s, z0.h
-; CHECK-NEXT: uunpkhi z0.s, z0.h
-; CHECK-NEXT: mov w9, #31743 // =0x7bff
-; CHECK-NEXT: uunpklo z5.s, z1.h
+; CHECK-NEXT: uunpkhi z4.s, z3.h
+; CHECK-NEXT: uunpklo z3.s, z3.h
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z28.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: uunpkhi z29.s, z1.h
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: uunpklo z13.s, z2.h
-; CHECK-NEXT: mov z9.d, #0x8000000000000000
-; CHECK-NEXT: uunpkhi z14.s, z2.h
-; CHECK-NEXT: uunpkhi z17.s, z3.h
-; CHECK-NEXT: uunpklo z6.d, z4.s
-; CHECK-NEXT: uunpkhi z4.d, z4.s
-; CHECK-NEXT: uunpklo z27.d, z0.s
-; CHECK-NEXT: uunpklo z31.d, z5.s
-; CHECK-NEXT: uunpkhi z8.d, z5.s
-; CHECK-NEXT: uunpkhi z30.d, z0.s
-; CHECK-NEXT: uunpkhi z11.d, z29.s
-; CHECK-NEXT: uunpklo z10.d, z29.s
-; CHECK-NEXT: uunpklo z15.s, z3.h
-; CHECK-NEXT: uunpklo z16.d, z14.s
-; CHECK-NEXT: uunpkhi z14.d, z14.s
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z5, z27
-; CHECK-NEXT: frintx z5.h, p0/m, z27.h
-; CHECK-NEXT: movprfx z1, z6
-; CHECK-NEXT: frintx z1.h, p0/m, z6.h
+; CHECK-NEXT: uunpkhi z7.s, z2.h
+; CHECK-NEXT: uunpklo z2.s, z2.h
+; CHECK-NEXT: uunpkhi z24.s, z0.h
+; CHECK-NEXT: uunpkhi z25.s, z1.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpkhi z5.d, z4.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpkhi z6.d, z3.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: uunpkhi z26.d, z7.s
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: uunpkhi z27.d, z2.s
+; CHECK-NEXT: uunpkhi z28.d, z24.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: uunpkhi z29.d, z25.s
+; CHECK-NEXT: uunpklo z25.d, z25.s
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
; CHECK-NEXT: frintx z4.h, p0/m, z4.h
-; CHECK-NEXT: movprfx z12, z31
-; CHECK-NEXT: frintx z12.h, p0/m, z31.h
-; CHECK-NEXT: movprfx z27, z8
-; CHECK-NEXT: frintx z27.h, p0/m, z8.h
-; CHECK-NEXT: movprfx z6, z30
-; CHECK-NEXT: frintx z6.h, p0/m, z30.h
-; CHECK-NEXT: movprfx z31, z10
-; CHECK-NEXT: frintx z31.h, p0/m, z10.h
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
-; CHECK-NEXT: frintx z11.h, p0/m, z11.h
-; CHECK-NEXT: movprfx z3, z16
-; CHECK-NEXT: frintx z3.h, p0/m, z16.h
-; CHECK-NEXT: mov z30.h, w9
-; CHECK-NEXT: uunpklo z10.d, z13.s
-; CHECK-NEXT: uunpkhi z13.d, z13.s
-; CHECK-NEXT: uunpkhi z20.d, z15.s
-; CHECK-NEXT: uunpklo z16.d, z17.s
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: mov z18.d, #0x8000000000000000
-; CHECK-NEXT: uunpklo z15.d, z15.s
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: frintx z10.h, p0/m, z10.h
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z29.d, #0x7fffffffffffffff
-; CHECK-NEXT: movprfx z19, z13
-; CHECK-NEXT: frintx z19.h, p0/m, z13.h
-; CHECK-NEXT: movprfx z13, z14
-; CHECK-NEXT: frintx z13.h, p0/m, z14.h
-; CHECK-NEXT: frintx z20.h, p0/m, z20.h
-; CHECK-NEXT: frintx z16.h, p0/m, z16.h
-; CHECK-NEXT: mov z22.d, #0x8000000000000000
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: frintx z15.h, p0/m, z15.h
-; CHECK-NEXT: mov z14.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p4.h, p0/z, z4.h, z28.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z12.h, z28.h
-; CHECK-NEXT: fcmgt p9.h, p0/z, z12.h, z30.h
-; CHECK-NEXT: fcmuo p8.h, p0/z, z12.h, z12.h
-; CHECK-NEXT: fcvtzs z7.d, p4/m, z4.h
-; CHECK-NEXT: fcvtzs z8.d, p2/m, z12.h
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p4.h, p0/z, z27.h, z28.h
-; CHECK-NEXT: fcmuo p10.h, p0/z, z11.h, z11.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z5.h, z28.h
-; CHECK-NEXT: mov z8.d, p9/m, z29.d
-; CHECK-NEXT: fcvtzs z9.d, p4/m, z27.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z11.h, z28.h
-; CHECK-NEXT: fcvtzs z24.d, p3/m, z5.h
-; CHECK-NEXT: mov z8.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcmge p1.h, p0/z, z6.h, z28.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z1.h, z28.h
-; CHECK-NEXT: str z8, [x8, #4, mul vl]
-; CHECK-NEXT: fcvtzs z12.d, p4/m, z11.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z11.h, z30.h
-; CHECK-NEXT: uunpkhi z11.d, z17.s
-; CHECK-NEXT: mov z17.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z25.d, p1/m, z6.h
-; CHECK-NEXT: fcvtzs z0.d, p5/m, z1.h
-; CHECK-NEXT: fcmge p6.h, p0/z, z10.h, z28.h
-; CHECK-NEXT: frintx z11.h, p0/m, z11.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z31.h, z28.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z13.h, z28.h
-; CHECK-NEXT: fcvtzs z18.d, p6/m, z10.h
-; CHECK-NEXT: fcmgt p11.h, p0/z, z10.h, z30.h
-; CHECK-NEXT: fcvtzs z2.d, p3/m, z31.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z11.h, z28.h
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z13.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z20.h, z28.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z16.h, z28.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z10.h, z10.h
-; CHECK-NEXT: sel z10.d, p4, z29.d, z12.d
-; CHECK-NEXT: sel z12.d, p11, z29.d, z18.d
-; CHECK-NEXT: fcvtzs z26.d, p5/m, z11.h
-; CHECK-NEXT: fcvtzs z22.d, p2/m, z20.h
-; CHECK-NEXT: fcvtzs z23.d, p3/m, z16.h
-; CHECK-NEXT: mov z10.d, p10/m, #0 // =0x0
-; CHECK-NEXT: mov z12.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.h, p0/z, z11.h, z30.h
-; CHECK-NEXT: fcmge p6.h, p0/z, z19.h, z28.h
-; CHECK-NEXT: str z10, [x8, #7, mul vl]
-; CHECK-NEXT: fcmge p7.h, p0/z, z3.h, z28.h
-; CHECK-NEXT: str z12, [x8, #8, mul vl]
-; CHECK-NEXT: fcmge p2.h, p0/z, z15.h, z28.h
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, p4/m, z29.d
-; CHECK-NEXT: fcmgt p5.h, p0/z, z16.h, z30.h
-; CHECK-NEXT: fcvtzs z14.d, p6/m, z19.h
-; CHECK-NEXT: fcvtzs z17.d, p7/m, z3.h
-; CHECK-NEXT: fcmgt p3.h, p0/z, z20.h, z30.h
-; CHECK-NEXT: fcvtzs z28.d, p2/m, z15.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z11.h, z11.h
-; CHECK-NEXT: sel z11.d, p5, z29.d, z23.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z16.h, z16.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z19.h, z30.h
-; CHECK-NEXT: sel z16.d, p3, z29.d, z22.d
-; CHECK-NEXT: mov z26.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.h, p0/z, z15.h, z30.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z13.h, z30.h
-; CHECK-NEXT: mov z11.d, p2/m, #0 // =0x0
-; CHECK-NEXT: str z26, [x8, #15, mul vl]
-; CHECK-NEXT: sel z26.d, p4, z29.d, z14.d
-; CHECK-NEXT: fcmuo p6.h, p0/z, z20.h, z20.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z3.h, z30.h
-; CHECK-NEXT: str z11, [x8, #14, mul vl]
-; CHECK-NEXT: mov z28.d, p3/m, z29.d
-; CHECK-NEXT: fcmuo p4.h, p0/z, z13.h, z13.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z3.h, z3.h
-; CHECK-NEXT: sel z3.d, p1, z29.d, z21.d
-; CHECK-NEXT: mov z16.d, p6/m, #0 // =0x0
-; CHECK-NEXT: sel z11.d, p2, z29.d, z17.d
-; CHECK-NEXT: fcmgt p12.h, p0/z, z27.h, z30.h
-; CHECK-NEXT: mov z3.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z16, [x8, #13, mul vl]
-; CHECK-NEXT: fcmuo p6.h, p0/z, z15.h, z15.h
-; CHECK-NEXT: mov z11.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.h, p0/z, z4.h, z30.h
-; CHECK-NEXT: str z3, [x8, #11, mul vl]
-; CHECK-NEXT: fcmuo p5.h, p0/z, z19.h, z19.h
-; CHECK-NEXT: mov z9.d, p12/m, z29.d
-; CHECK-NEXT: str z11, [x8, #10, mul vl]
-; CHECK-NEXT: fcmgt p2.h, p0/z, z5.h, z30.h
-; CHECK-NEXT: mov z28.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.h, p0/z, z6.h, z30.h
-; CHECK-NEXT: sel z3.d, p1, z29.d, z7.d
-; CHECK-NEXT: mov z26.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.h, p0/z, z27.h, z27.h
-; CHECK-NEXT: str z28, [x8, #12, mul vl]
-; CHECK-NEXT: fcmgt p6.h, p0/z, z31.h, z30.h
-; CHECK-NEXT: sel z7.d, p2, z29.d, z24.d
-; CHECK-NEXT: str z26, [x8, #9, mul vl]
-; CHECK-NEXT: sel z24.d, p4, z29.d, z25.d
-; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z30.h
-; CHECK-NEXT: fcmuo p5.h, p0/z, z31.h, z31.h
-; CHECK-NEXT: mov z9.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p6/m, z29.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z6.h, z6.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z5.h, z5.h
-; CHECK-NEXT: str z9, [x8, #5, mul vl]
-; CHECK-NEXT: mov z0.d, p1/m, z29.d
-; CHECK-NEXT: mov z2.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p4.h, p0/z, z4.h, z4.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: mov z24.d, p2/m, #0 // =0x0
-; CHECK-NEXT: str z2, [x8, #6, mul vl]
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z24, [x8, #3, mul vl]
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z7, [x8, #2, mul vl]
-; CHECK-NEXT: str z3, [x8, #1, mul vl]
+; CHECK-NEXT: frintx z6.h, p0/m, z6.h
+; CHECK-NEXT: frintx z3.h, p0/m, z3.h
+; CHECK-NEXT: frintx z26.h, p0/m, z26.h
+; CHECK-NEXT: frintx z7.h, p0/m, z7.h
+; CHECK-NEXT: frintx z27.h, p0/m, z27.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
+; CHECK-NEXT: frintx z28.h, p0/m, z28.h
+; CHECK-NEXT: frintx z29.h, p0/m, z29.h
+; CHECK-NEXT: frintx z25.h, p0/m, z25.h
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.h
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.h
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.h
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.h
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.h
+; CHECK-NEXT: str z5, [x8, #15, mul vl]
+; CHECK-NEXT: uunpkhi z5.d, z1.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: str z4, [x8, #14, mul vl]
+; CHECK-NEXT: uunpkhi z4.d, z0.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: str z3, [x8, #12, mul vl]
+; CHECK-NEXT: uunpklo z3.d, z24.s
+; CHECK-NEXT: str z6, [x8, #13, mul vl]
+; CHECK-NEXT: str z26, [x8, #11, mul vl]
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
+; CHECK-NEXT: frintx z1.h, p0/m, z1.h
+; CHECK-NEXT: str z7, [x8, #10, mul vl]
+; CHECK-NEXT: frintx z4.h, p0/m, z4.h
+; CHECK-NEXT: frintx z0.h, p0/m, z0.h
+; CHECK-NEXT: str z27, [x8, #9, mul vl]
+; CHECK-NEXT: frintx z3.h, p0/m, z3.h
+; CHECK-NEXT: str z2, [x8, #8, mul vl]
+; CHECK-NEXT: str z29, [x8, #7, mul vl]
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: str z25, [x8, #6, mul vl]
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: str z5, [x8, #5, mul vl]
+; CHECK-NEXT: str z1, [x8, #4, mul vl]
+; CHECK-NEXT: str z3, [x8, #2, mul vl]
+; CHECK-NEXT: str z4, [x8, #1, mul vl]
; CHECK-NEXT: str z0, [x8]
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.lrint.nxv32i64.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x i64> %a
@@ -508,19 +201,8 @@ define <vscale x 1 x i64> @lrint_v1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: lrint_v1f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.lrint.nxv1i64.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x i64> %a
@@ -530,19 +212,8 @@ define <vscale x 2 x i64> @lrint_v2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: lrint_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.lrint.nxv2i64.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x i64> %a
@@ -553,28 +224,14 @@ define <vscale x 4 x i64> @lrint_v4f32(<vscale x 4 x float> %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
; CHECK-NEXT: frintx z1.s, p0/m, z1.s
-; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmuo p3.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z1.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z0.s
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: frintx z2.s, p0/m, z0.s
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.s
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.lrint.nxv4i64.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x i64> %a
@@ -583,61 +240,25 @@ define <vscale x 4 x i64> @lrint_v4f32(<vscale x 4 x float> %x) {
define <vscale x 8 x i64> @lrint_v8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: lrint_v8f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uunpklo z3.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.s, w8
+; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: frintx z2.s, p0/m, z2.s
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z6, z0
-; CHECK-NEXT: frintx z6.s, p0/m, z0.s
+; CHECK-NEXT: movprfx z4, z0
+; CHECK-NEXT: frintx z4.s, p0/m, z0.s
; CHECK-NEXT: frintx z3.s, p0/m, z3.s
-; CHECK-NEXT: frintx z1.s, p0/m, z1.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z2.s, z4.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z4.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z3.s, z4.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z2.s, z25.s
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z2.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z4.s
-; CHECK-NEXT: mov z4.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcvtzs z7.d, p2/m, z6.s
-; CHECK-NEXT: fcvtzs z24.d, p3/m, z3.s
-; CHECK-NEXT: fcmgt p3.s, p0/z, z6.s, z25.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z3.s, z25.s
-; CHECK-NEXT: fcvtzs z26.d, p1/m, z1.s
-; CHECK-NEXT: sel z0.d, p4, z4.d, z5.d
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z25.s
-; CHECK-NEXT: fcmuo p4.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: fcmuo p6.s, p0/z, z3.s, z3.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z2.s, z2.s
-; CHECK-NEXT: sel z2.d, p5, z4.d, z24.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z1.d, p3, z4.d, z7.d
-; CHECK-NEXT: sel z3.d, p1, z4.d, z26.d
-; CHECK-NEXT: mov z2.d, p6/m, #0 // =0x0
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z1.d, p4/m, #0 // =0x0
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z5, z1
+; CHECK-NEXT: frintx z5.s, p0/m, z1.s
+; CHECK-NEXT: movprfx z0, z2
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.s
+; CHECK-NEXT: movprfx z1, z4
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z2, z3
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z3.s
+; CHECK-NEXT: movprfx z3, z5
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z5.s
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.lrint.nxv8i64.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x i64> %a
@@ -646,114 +267,43 @@ define <vscale x 8 x i64> @lrint_v8f32(<vscale x 8 x float> %x) {
define <vscale x 16 x i64> @lrint_v16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: lrint_v16f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-3
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
; CHECK-NEXT: uunpklo z4.d, z0.s
-; CHECK-NEXT: uunpkhi z5.d, z0.s
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: uunpkhi z7.d, z1.s
-; CHECK-NEXT: uunpklo z24.d, z2.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: uunpklo z6.d, z1.s
+; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z5.d, z1.s
+; CHECK-NEXT: uunpkhi z1.d, z1.s
+; CHECK-NEXT: uunpklo z6.d, z2.s
; CHECK-NEXT: uunpkhi z2.d, z2.s
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z25, z4
-; CHECK-NEXT: frintx z25.s, p0/m, z4.s
+; CHECK-NEXT: uunpklo z7.d, z3.s
+; CHECK-NEXT: uunpkhi z3.d, z3.s
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: frintx z4.s, p0/m, z4.s
+; CHECK-NEXT: movprfx z24, z0
+; CHECK-NEXT: frintx z24.s, p0/m, z0.s
; CHECK-NEXT: frintx z5.s, p0/m, z5.s
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: frintx z7.s, p0/m, z7.s
-; CHECK-NEXT: frintx z24.s, p0/m, z24.s
-; CHECK-NEXT: movprfx z30, z2
-; CHECK-NEXT: frintx z30.s, p0/m, z2.s
+; CHECK-NEXT: movprfx z25, z1
+; CHECK-NEXT: frintx z25.s, p0/m, z1.s
; CHECK-NEXT: frintx z6.s, p0/m, z6.s
-; CHECK-NEXT: uunpklo z2.d, z3.s
-; CHECK-NEXT: mov z29.s, w8
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
-; CHECK-NEXT: mov z9.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p5.s, p0/z, z25.s, z4.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z5.s, z4.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z7.s, z4.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z24.s, z4.s
-; CHECK-NEXT: fcvtzs z0.d, p5/m, z25.s
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z5.s
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z7.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z4.s
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z24.s
-; CHECK-NEXT: fcmgt p3.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z30.s, z4.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: movprfx z25, z2
-; CHECK-NEXT: frintx z25.s, p0/m, z2.s
-; CHECK-NEXT: uunpkhi z2.d, z3.s
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z6.s
-; CHECK-NEXT: mov z0.d, p3/m, z9.d
-; CHECK-NEXT: fcmgt p5.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: fcvtzs z31.d, p4/m, z30.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: movprfx z5, z2
-; CHECK-NEXT: frintx z5.s, p0/m, z2.s
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmge p4.s, p0/z, z25.s, z4.s
-; CHECK-NEXT: fcmgt p6.s, p0/z, z6.s, z29.s
-; CHECK-NEXT: mov z1.d, p5/m, z9.d
-; CHECK-NEXT: fcmgt p8.s, p0/z, z7.s, z29.s
-; CHECK-NEXT: fcmuo p10.s, p0/z, z7.s, z7.s
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z8.d, p4/m, z25.s
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: sel z2.d, p6, z9.d, z26.d
-; CHECK-NEXT: sel z3.d, p8, z9.d, z27.d
-; CHECK-NEXT: fcmge p4.s, p0/z, z5.s, z4.s
-; CHECK-NEXT: fcmgt p9.s, p0/z, z24.s, z29.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z30.s, z29.s
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmgt p6.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcvtzs z7.d, p4/m, z5.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: sel z4.d, p9, z9.d, z28.d
-; CHECK-NEXT: fcmuo p7.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: sel z6.d, p6, z9.d, z8.d
-; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p8.s, p0/z, z30.s, z30.s
-; CHECK-NEXT: fcmuo p9.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: mov z7.d, p4/m, z9.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z2.d, p7/m, #0 // =0x0
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p3.s, p0/z, z24.s, z24.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: sel z5.d, p5, z9.d, z31.d
-; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #3
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z26, z2
+; CHECK-NEXT: frintx z26.s, p0/m, z2.s
+; CHECK-NEXT: frintx z7.s, p0/m, z7.s
+; CHECK-NEXT: movprfx z27, z3
+; CHECK-NEXT: frintx z27.s, p0/m, z3.s
+; CHECK-NEXT: movprfx z0, z4
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z1, z24
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z24.s
+; CHECK-NEXT: movprfx z2, z5
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z5.s
+; CHECK-NEXT: movprfx z3, z25
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z25.s
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z6.s
+; CHECK-NEXT: movprfx z5, z26
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z26.s
+; CHECK-NEXT: movprfx z6, z7
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z7.s
+; CHECK-NEXT: movprfx z7, z27
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z27.s
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.lrint.nxv16i64.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x i64> %a
@@ -762,251 +312,71 @@ define <vscale x 16 x i64> @lrint_v16f32(<vscale x 16 x float> %x) {
define <vscale x 32 x i64> @lrint_v32f32(<vscale x 32 x float> %x) {
; CHECK-LABEL: lrint_v32f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x98, 0x01, 0x1e, 0x22 // sp + 16 + 152 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: uunpklo z24.d, z0.s
-; CHECK-NEXT: uunpklo z26.d, z1.s
-; CHECK-NEXT: mov w9, #-553648128 // =0xdf000000
-; CHECK-NEXT: uunpklo z28.d, z2.s
-; CHECK-NEXT: uunpkhi z30.d, z2.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: uunpkhi z25.d, z0.s
-; CHECK-NEXT: uunpkhi z13.d, z3.s
-; CHECK-NEXT: uunpklo z14.d, z4.s
-; CHECK-NEXT: uunpkhi z27.d, z1.s
-; CHECK-NEXT: uunpklo z9.d, z3.s
-; CHECK-NEXT: mov z29.s, w9
-; CHECK-NEXT: movprfx z0, z24
-; CHECK-NEXT: frintx z0.s, p0/m, z24.s
-; CHECK-NEXT: movprfx z24, z26
-; CHECK-NEXT: frintx z24.s, p0/m, z26.s
-; CHECK-NEXT: mov w9, #1593835519 // =0x5effffff
-; CHECK-NEXT: movprfx z10, z28
-; CHECK-NEXT: frintx z10.s, p0/m, z28.s
-; CHECK-NEXT: frintx z30.s, p0/m, z30.s
-; CHECK-NEXT: uunpklo z17.d, z5.s
-; CHECK-NEXT: movprfx z1, z25
-; CHECK-NEXT: frintx z1.s, p0/m, z25.s
-; CHECK-NEXT: movprfx z15, z13
-; CHECK-NEXT: frintx z15.s, p0/m, z13.s
-; CHECK-NEXT: movprfx z13, z14
-; CHECK-NEXT: frintx z13.s, p0/m, z14.s
-; CHECK-NEXT: uunpkhi z14.d, z4.s
-; CHECK-NEXT: uunpkhi z18.d, z5.s
-; CHECK-NEXT: uunpkhi z19.d, z6.s
-; CHECK-NEXT: movprfx z25, z27
-; CHECK-NEXT: frintx z25.s, p0/m, z27.s
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: mov z11.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p3.s, p0/z, z24.s, z29.s
-; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p5.s, p0/z, z10.s, z29.s
-; CHECK-NEXT: frintx z9.s, p0/m, z9.s
-; CHECK-NEXT: uunpklo z20.d, z7.s
-; CHECK-NEXT: movprfx z5, z14
-; CHECK-NEXT: frintx z5.s, p0/m, z14.s
-; CHECK-NEXT: movprfx z14, z17
-; CHECK-NEXT: frintx z14.s, p0/m, z17.s
-; CHECK-NEXT: movprfx z17, z18
-; CHECK-NEXT: frintx z17.s, p0/m, z18.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z30.s, z29.s
-; CHECK-NEXT: uunpkhi z7.d, z7.s
-; CHECK-NEXT: mov z31.s, w9
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: frintx z19.s, p0/m, z19.s
+; CHECK-NEXT: uunpkhi z24.d, z7.s
+; CHECK-NEXT: uunpkhi z25.d, z6.s
; CHECK-NEXT: uunpklo z6.d, z6.s
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z24.s
-; CHECK-NEXT: fcvtzs z11.d, p5/m, z10.s
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z16.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z22, z7
-; CHECK-NEXT: frintx z22.s, p0/m, z7.s
-; CHECK-NEXT: fcvtzs z12.d, p6/m, z30.s
-; CHECK-NEXT: frintx z20.s, p0/m, z20.s
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: uunpkhi z26.d, z5.s
+; CHECK-NEXT: uunpklo z5.d, z5.s
+; CHECK-NEXT: uunpkhi z27.d, z4.s
+; CHECK-NEXT: uunpkhi z28.d, z1.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpkhi z29.d, z3.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: frintx z24.s, p0/m, z24.s
; CHECK-NEXT: frintx z6.s, p0/m, z6.s
-; CHECK-NEXT: mov z3.d, #0x7fffffffffffffff
-; CHECK-NEXT: mov z18.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z29.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, z29.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcmgt p9.s, p0/z, z10.s, z31.s
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z1.s
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z25.s
-; CHECK-NEXT: mov z11.d, p9/m, z3.d
-; CHECK-NEXT: fcmuo p8.s, p0/z, z10.s, z10.s
-; CHECK-NEXT: mov z10.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p5.s, p0/z, z9.s, z29.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z15.s, z29.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z13.s, z29.s
-; CHECK-NEXT: mov z11.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcvtzs z10.d, p5/m, z9.s
-; CHECK-NEXT: fcvtzs z4.d, p3/m, z15.s
-; CHECK-NEXT: fcvtzs z16.d, p6/m, z13.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z17.s, z29.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z19.s, z29.s
-; CHECK-NEXT: fcmgt p12.s, p0/z, z30.s, z31.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z15.s, z31.s
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z17.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z20.s, z29.s
-; CHECK-NEXT: fcvtzs z23.d, p2/m, z19.s
-; CHECK-NEXT: sel z7.d, p12, z3.d, z12.d
-; CHECK-NEXT: fcmgt p11.s, p0/z, z13.s, z31.s
-; CHECK-NEXT: mov z4.d, p5/m, z3.d
-; CHECK-NEXT: fcmge p4.s, p0/z, z22.s, z29.s
-; CHECK-NEXT: fcvtzs z0.d, p3/m, z20.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: fcmge p7.s, p0/z, z14.s, z29.s
-; CHECK-NEXT: sel z12.d, p11, z3.d, z16.d
-; CHECK-NEXT: fcvtzs z8.d, p4/m, z22.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z13.s, z13.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z29.s
-; CHECK-NEXT: mov z29.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z18.d, p7/m, z14.s
-; CHECK-NEXT: fcmuo p10.s, p0/z, z15.s, z15.s
-; CHECK-NEXT: mov z15.d, #0x8000000000000000
-; CHECK-NEXT: mov z12.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.s, p0/z, z22.s, z31.s
-; CHECK-NEXT: fcvtzs z29.d, p2/m, z6.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z20.s, z31.s
-; CHECK-NEXT: str z12, [x8, #8, mul vl]
-; CHECK-NEXT: fcvtzs z15.d, p6/m, z5.s
-; CHECK-NEXT: mov z4.d, p10/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.s, p0/z, z19.s, z31.s
-; CHECK-NEXT: mov z8.d, p4/m, z3.d
-; CHECK-NEXT: fcmuo p1.s, p0/z, z22.s, z22.s
-; CHECK-NEXT: str z4, [x8, #7, mul vl]
-; CHECK-NEXT: mov z0.d, p5/m, z3.d
-; CHECK-NEXT: fcmuo p2.s, p0/z, z20.s, z20.s
-; CHECK-NEXT: fcmuo p6.s, p0/z, z19.s, z19.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z5.s, z31.s
-; CHECK-NEXT: mov z8.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p5.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: sel z5.d, p3, z3.d, z23.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.s, p0/z, z6.s, z31.s
-; CHECK-NEXT: str z8, [x8, #15, mul vl]
-; CHECK-NEXT: fcmgt p1.s, p0/z, z17.s, z31.s
-; CHECK-NEXT: str z0, [x8, #14, mul vl]
-; CHECK-NEXT: mov z5.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p2.s, p0/z, z14.s, z31.s
-; CHECK-NEXT: sel z0.d, p3, z3.d, z29.d
-; CHECK-NEXT: fcmuo p6.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: str z5, [x8, #13, mul vl]
-; CHECK-NEXT: sel z6.d, p4, z3.d, z15.d
-; CHECK-NEXT: sel z5.d, p1, z3.d, z21.d
-; CHECK-NEXT: fcmuo p4.s, p0/z, z17.s, z17.s
-; CHECK-NEXT: sel z29.d, p2, z3.d, z18.d
-; CHECK-NEXT: mov z6.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.s, p0/z, z14.s, z14.s
-; CHECK-NEXT: mov z0.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z31.s
-; CHECK-NEXT: str z6, [x8, #9, mul vl]
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z0, [x8, #12, mul vl]
-; CHECK-NEXT: mov z29.d, p3/m, #0 // =0x0
-; CHECK-NEXT: str z5, [x8, #11, mul vl]
-; CHECK-NEXT: sel z5.d, p1, z3.d, z26.d
-; CHECK-NEXT: fcmgt p2.s, p0/z, z24.s, z31.s
-; CHECK-NEXT: str z29, [x8, #10, mul vl]
-; CHECK-NEXT: ldr z4, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: str z11, [x8, #4, mul vl]
-; CHECK-NEXT: fcmgt p4.s, p0/z, z25.s, z31.s
-; CHECK-NEXT: fcmuo p3.s, p0/z, z30.s, z30.s
-; CHECK-NEXT: sel z26.d, p2, z3.d, z27.d
-; CHECK-NEXT: fcmgt p6.s, p0/z, z9.s, z31.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z4.s, z31.s
-; CHECK-NEXT: fcmuo p5.s, p0/z, z9.s, z9.s
-; CHECK-NEXT: sel z6.d, p4, z3.d, z28.d
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p2.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: sel z0.d, p6, z3.d, z10.d
-; CHECK-NEXT: fcmuo p3.s, p0/z, z24.s, z24.s
-; CHECK-NEXT: fcmuo p4.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z1.d, p1, z3.d, z2.d
-; CHECK-NEXT: str z7, [x8, #5, mul vl]
-; CHECK-NEXT: fcmuo p0.s, p0/z, z4.s, z4.s
-; CHECK-NEXT: mov z0.d, p5/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z26.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z0, [x8, #6, mul vl]
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z6, [x8, #3, mul vl]
-; CHECK-NEXT: str z26, [x8, #2, mul vl]
-; CHECK-NEXT: str z5, [x8, #1, mul vl]
-; CHECK-NEXT: str z1, [x8]
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: frintx z7.s, p0/m, z7.s
+; CHECK-NEXT: frintx z25.s, p0/m, z25.s
+; CHECK-NEXT: frintx z26.s, p0/m, z26.s
+; CHECK-NEXT: frintx z5.s, p0/m, z5.s
+; CHECK-NEXT: frintx z27.s, p0/m, z27.s
+; CHECK-NEXT: frintx z28.s, p0/m, z28.s
+; CHECK-NEXT: frintx z4.s, p0/m, z4.s
+; CHECK-NEXT: frintx z29.s, p0/m, z29.s
+; CHECK-NEXT: frintx z3.s, p0/m, z3.s
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.s
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-NEXT: frintx z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.s
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.s
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.s
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.s
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.s
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.s
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.s
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.s
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.s
+; CHECK-NEXT: str z24, [x8, #15, mul vl]
+; CHECK-NEXT: uunpkhi z24.d, z2.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: str z6, [x8, #12, mul vl]
+; CHECK-NEXT: uunpkhi z6.d, z0.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: str z7, [x8, #14, mul vl]
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
+; CHECK-NEXT: str z25, [x8, #13, mul vl]
+; CHECK-NEXT: str z26, [x8, #11, mul vl]
+; CHECK-NEXT: frintx z24.s, p0/m, z24.s
+; CHECK-NEXT: frintx z2.s, p0/m, z2.s
+; CHECK-NEXT: str z5, [x8, #10, mul vl]
+; CHECK-NEXT: frintx z6.s, p0/m, z6.s
+; CHECK-NEXT: frintx z0.s, p0/m, z0.s
+; CHECK-NEXT: str z27, [x8, #9, mul vl]
+; CHECK-NEXT: str z4, [x8, #8, mul vl]
+; CHECK-NEXT: str z29, [x8, #7, mul vl]
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.s
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.s
+; CHECK-NEXT: str z3, [x8, #6, mul vl]
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: str z1, [x8, #2, mul vl]
+; CHECK-NEXT: str z24, [x8, #5, mul vl]
+; CHECK-NEXT: str z2, [x8, #4, mul vl]
+; CHECK-NEXT: str z6, [x8, #1, mul vl]
+; CHECK-NEXT: str z0, [x8]
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.lrint.nxv32i64.nxv32f32(<vscale x 32 x float> %x)
ret <vscale x 32 x i64> %a
@@ -1016,19 +386,8 @@ define <vscale x 1 x i64> @lrint_v1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: lrint_v1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.lrint.nxv1i64.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x i64> %a
@@ -1038,19 +397,8 @@ define <vscale x 2 x i64> @lrint_v2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: lrint_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.lrint.nxv2i64.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x i64> %a
@@ -1060,27 +408,10 @@ define <vscale x 4 x i64> @lrint_v4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: lrint_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fcmuo p3.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z1.d
-; CHECK-NEXT: fcmgt p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.lrint.nxv4i64.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x i64> %a
@@ -1089,56 +420,15 @@ define <vscale x 4 x i64> @lrint_v4f64(<vscale x 4 x double> %x) {
define <vscale x 8 x i64> @lrint_v8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: lrint_v8f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
-; CHECK-NEXT: mov z24.d, x8
; CHECK-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z5.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z5.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z2.d, z5.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z0.d, z24.d
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z3.d, z5.d
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z6.d, p2/m, z1.d
-; CHECK-NEXT: fcvtzs z7.d, p3/m, z2.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z24.d
-; CHECK-NEXT: sel z0.d, p4, z25.d, z4.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z2.d, z24.d
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z3.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z24.d
-; CHECK-NEXT: fcmuo p5.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: sel z1.d, p3, z25.d, z6.d
-; CHECK-NEXT: fcmuo p6.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: sel z2.d, p4, z25.d, z7.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: sel z3.d, p1, z25.d, z5.d
-; CHECK-NEXT: mov z1.d, p5/m, #0 // =0x0
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z2.d, p6/m, #0 // =0x0
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.lrint.nxv8i64.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x i64> %a
@@ -1147,103 +437,23 @@ define <vscale x 8 x i64> @lrint_v8f64(<vscale x 8 x double> %x) {
define <vscale x 16 x i64> @lrint_v16f64(<vscale x 16 x double> %x) {
; CHECK-LABEL: lrint_v16f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-3
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: frintx z24.d, p0/m, z0.d
-; CHECK-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-NEXT: mov z0.d, x8
+; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-NEXT: frintx z3.d, p0/m, z3.d
; CHECK-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-NEXT: mov z30.d, x8
-; CHECK-NEXT: mov z29.d, #0x8000000000000000
; CHECK-NEXT: frintx z5.d, p0/m, z5.d
+; CHECK-NEXT: frintx z6.d, p0/m, z6.d
; CHECK-NEXT: frintx z7.d, p0/m, z7.d
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x7fffffffffffffff
-; CHECK-NEXT: mov z9.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.d, p0/z, z24.d, z0.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z3.d, z0.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z0.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z2.d, z0.d
-; CHECK-NEXT: fcvtzs z25.d, p1/m, z24.d
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z3.d
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z1.d
-; CHECK-NEXT: fcmge p5.d, p0/z, z4.d, z0.d
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z2.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z24.d, z30.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z24.d, z24.d
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p7.d, p0/z, z6.d, z0.d
-; CHECK-NEXT: fcvtzs z29.d, p5/m, z4.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z5.d, z0.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z1.d, z30.d
-; CHECK-NEXT: fcvtzs z24.d, p7/m, z6.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z2.d, z30.d
-; CHECK-NEXT: fcmge p7.d, p0/z, z7.d, z0.d
-; CHECK-NEXT: fcvtzs z31.d, p3/m, z5.d
-; CHECK-NEXT: sel z0.d, p4, z8.d, z25.d
-; CHECK-NEXT: fcmgt p8.d, p0/z, z3.d, z30.d
-; CHECK-NEXT: fcmgt p9.d, p0/z, z4.d, z30.d
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcvtzs z9.d, p7/m, z7.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z1.d, p5, z8.d, z26.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: sel z2.d, p6, z8.d, z27.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z5.d, z30.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z6.d, z30.d
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p7.d, p0/z, z7.d, z30.d
-; CHECK-NEXT: fcmuo p10.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: sel z3.d, p8, z8.d, z28.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z4.d, z4.d
-; CHECK-NEXT: sel z4.d, p9, z8.d, z29.d
-; CHECK-NEXT: fcmuo p8.d, p0/z, z5.d, z5.d
-; CHECK-NEXT: sel z5.d, p5, z8.d, z31.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p9.d, p0/z, z6.d, z6.d
-; CHECK-NEXT: sel z6.d, p6, z8.d, z24.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p4/m, #0 // =0x0
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.d, p0/z, z7.d, z7.d
-; CHECK-NEXT: sel z7.d, p7, z8.d, z9.d
-; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #3
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.lrint.nxv16i64.nxv16f64(<vscale x 16 x double> %x)
ret <vscale x 16 x i64> %a
@@ -1252,242 +462,71 @@ define <vscale x 16 x i64> @lrint_v16f64(<vscale x 16 x double> %x) {
define <vscale x 32 x i64> @lrint_v32f64(<vscale x 32 x double> %x) {
; CHECK-LABEL: lrint_v32f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x90, 0x01, 0x1e, 0x22 // sp + 16 + 144 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: ldr z0, [x0]
-; CHECK-NEXT: ldr z7, [x0, #3, mul vl]
+; CHECK-NEXT: ldr z0, [x0, #15, mul vl]
+; CHECK-NEXT: ldr z1, [x0, #14, mul vl]
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ldr z27, [x0, #4, mul vl]
-; CHECK-NEXT: ldr z4, [x0, #2, mul vl]
-; CHECK-NEXT: mov x9, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z25.d, x9
-; CHECK-NEXT: ldr z2, [x0, #1, mul vl]
-; CHECK-NEXT: ldr z29, [x0, #6, mul vl]
+; CHECK-NEXT: ldr z2, [x0, #13, mul vl]
+; CHECK-NEXT: ldr z3, [x0, #12, mul vl]
+; CHECK-NEXT: ldr z4, [x0, #11, mul vl]
+; CHECK-NEXT: ldr z5, [x0, #10, mul vl]
+; CHECK-NEXT: ldr z6, [x0, #9, mul vl]
+; CHECK-NEXT: ldr z7, [x0, #8, mul vl]
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: frintx z7.d, p0/m, z7.d
-; CHECK-NEXT: ldr z31, [x0, #7, mul vl]
-; CHECK-NEXT: movprfx z14, z27
-; CHECK-NEXT: frintx z14.d, p0/m, z27.d
+; CHECK-NEXT: frintx z1.d, p0/m, z1.d
+; CHECK-NEXT: ldr z24, [x0, #7, mul vl]
+; CHECK-NEXT: ldr z25, [x0, #6, mul vl]
+; CHECK-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-NEXT: frintx z3.d, p0/m, z3.d
+; CHECK-NEXT: ldr z26, [x0, #5, mul vl]
+; CHECK-NEXT: ldr z27, [x0, #4, mul vl]
; CHECK-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-NEXT: ldr z27, [x0, #5, mul vl]
-; CHECK-NEXT: ldr z15, [x0, #8, mul vl]
-; CHECK-NEXT: mov x9, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: movprfx z3, z2
-; CHECK-NEXT: frintx z3.d, p0/m, z2.d
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: mov z30.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z25.d
-; CHECK-NEXT: movprfx z28, z27
-; CHECK-NEXT: frintx z28.d, p0/m, z27.d
+; CHECK-NEXT: ldr z28, [x0, #3, mul vl]
+; CHECK-NEXT: ldr z29, [x0, #2, mul vl]
+; CHECK-NEXT: frintx z5.d, p0/m, z5.d
+; CHECK-NEXT: ldr z30, [x0, #1, mul vl]
+; CHECK-NEXT: ldr z31, [x0]
+; CHECK-NEXT: frintx z6.d, p0/m, z6.d
+; CHECK-NEXT: frintx z7.d, p0/m, z7.d
+; CHECK-NEXT: frintx z24.d, p0/m, z24.d
+; CHECK-NEXT: frintx z25.d, p0/m, z25.d
+; CHECK-NEXT: frintx z26.d, p0/m, z26.d
+; CHECK-NEXT: frintx z27.d, p0/m, z27.d
+; CHECK-NEXT: frintx z28.d, p0/m, z28.d
; CHECK-NEXT: frintx z29.d, p0/m, z29.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z7.d, z25.d
-; CHECK-NEXT: mov z1.d, x9
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p3.d, p0/z, z14.d, z25.d
-; CHECK-NEXT: ldr z11, [x0, #13, mul vl]
-; CHECK-NEXT: ldr z18, [x0, #11, mul vl]
-; CHECK-NEXT: fcmge p5.d, p0/z, z4.d, z25.d
-; CHECK-NEXT: ldr z19, [x0, #9, mul vl]
-; CHECK-NEXT: movprfx z20, z31
-; CHECK-NEXT: frintx z20.d, p0/m, z31.d
-; CHECK-NEXT: frintx z15.d, p0/m, z15.d
-; CHECK-NEXT: ldr z9, [x0, #15, mul vl]
-; CHECK-NEXT: ldr z10, [x0, #14, mul vl]
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcvtzs z24.d, p2/m, z7.d
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z30.d, p3/m, z14.d
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: frintx z18.d, p0/m, z18.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z28.d, z25.d
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: ldr z8, [x0, #12, mul vl]
-; CHECK-NEXT: fcmgt p10.d, p0/z, z14.d, z1.d
-; CHECK-NEXT: ldr z13, [x0, #10, mul vl]
-; CHECK-NEXT: fcvtzs z6.d, p5/m, z4.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z29.d, z25.d
-; CHECK-NEXT: mov z16.d, #0x8000000000000000
-; CHECK-NEXT: mov z17.d, #0x8000000000000000
-; CHECK-NEXT: frintx z10.d, p0/m, z10.d
-; CHECK-NEXT: frintx z9.d, p0/m, z9.d
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z12.d, p1/m, z28.d
-; CHECK-NEXT: frintx z13.d, p0/m, z13.d
-; CHECK-NEXT: mov z22.d, #0x8000000000000000
-; CHECK-NEXT: frintx z8.d, p0/m, z8.d
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcvtzs z31.d, p2/m, z29.d
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: fcmuo p8.d, p0/z, z14.d, z14.d
-; CHECK-NEXT: movprfx z14, z19
-; CHECK-NEXT: frintx z14.d, p0/m, z19.d
-; CHECK-NEXT: movprfx z19, z11
-; CHECK-NEXT: frintx z19.d, p0/m, z11.d
-; CHECK-NEXT: mov z11.d, #0x8000000000000000
-; CHECK-NEXT: mov z30.d, p10/m, z27.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z3.d, z25.d
-; CHECK-NEXT: fcmge p5.d, p0/z, z20.d, z25.d
-; CHECK-NEXT: mov z30.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcmge p6.d, p0/z, z15.d, z25.d
-; CHECK-NEXT: fcvtzs z5.d, p4/m, z3.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z18.d, z25.d
-; CHECK-NEXT: str z30, [x8, #4, mul vl]
-; CHECK-NEXT: fcvtzs z16.d, p5/m, z20.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z19.d, z25.d
-; CHECK-NEXT: fcvtzs z17.d, p6/m, z15.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z20.d, z1.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z10.d, z25.d
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z18.d
-; CHECK-NEXT: fcvtzs z22.d, p2/m, z19.d
-; CHECK-NEXT: fcmgt p11.d, p0/z, z15.d, z1.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z9.d, z25.d
-; CHECK-NEXT: fcmge p6.d, p0/z, z14.d, z25.d
-; CHECK-NEXT: fcvtzs z23.d, p3/m, z10.d
-; CHECK-NEXT: fcmge p7.d, p0/z, z13.d, z25.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z15.d, z15.d
-; CHECK-NEXT: sel z15.d, p5, z27.d, z16.d
-; CHECK-NEXT: sel z16.d, p11, z27.d, z17.d
-; CHECK-NEXT: fcvtzs z26.d, p4/m, z9.d
-; CHECK-NEXT: fcvtzs z11.d, p6/m, z14.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z8.d, z25.d
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z16.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.d, p0/z, z9.d, z1.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z10.d, z1.d
-; CHECK-NEXT: str z16, [x8, #8, mul vl]
-; CHECK-NEXT: fcvtzs z25.d, p2/m, z8.d
-; CHECK-NEXT: fcmgt p3.d, p0/z, z19.d, z1.d
-; CHECK-NEXT: fcmuo p9.d, p0/z, z20.d, z20.d
-; CHECK-NEXT: mov z20.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, p4/m, z27.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z9.d, z9.d
-; CHECK-NEXT: sel z9.d, p5, z27.d, z23.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z10.d, z10.d
-; CHECK-NEXT: sel z10.d, p3, z27.d, z22.d
-; CHECK-NEXT: fcvtzs z20.d, p7/m, z13.d
-; CHECK-NEXT: mov z15.d, p9/m, #0 // =0x0
-; CHECK-NEXT: mov z26.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z9.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.d, p0/z, z14.d, z1.d
-; CHECK-NEXT: str z15, [x8, #7, mul vl]
-; CHECK-NEXT: fcmgt p3.d, p0/z, z8.d, z1.d
-; CHECK-NEXT: str z26, [x8, #15, mul vl]
-; CHECK-NEXT: fcmuo p6.d, p0/z, z19.d, z19.d
-; CHECK-NEXT: str z9, [x8, #14, mul vl]
-; CHECK-NEXT: fcmgt p1.d, p0/z, z18.d, z1.d
-; CHECK-NEXT: fcmgt p2.d, p0/z, z13.d, z1.d
-; CHECK-NEXT: sel z26.d, p4, z27.d, z11.d
-; CHECK-NEXT: mov z25.d, p3/m, z27.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z18.d, z18.d
-; CHECK-NEXT: mov z10.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.d, p0/z, z13.d, z13.d
-; CHECK-NEXT: sel z9.d, p2, z27.d, z20.d
-; CHECK-NEXT: fcmgt p12.d, p0/z, z28.d, z1.d
-; CHECK-NEXT: str z10, [x8, #13, mul vl]
-; CHECK-NEXT: fcmuo p6.d, p0/z, z8.d, z8.d
-; CHECK-NEXT: sel z8.d, p1, z27.d, z21.d
-; CHECK-NEXT: mov z9.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z1.d
-; CHECK-NEXT: fcmuo p5.d, p0/z, z14.d, z14.d
-; CHECK-NEXT: mov z8.d, p4/m, #0 // =0x0
-; CHECK-NEXT: mov z12.d, p12/m, z27.d
-; CHECK-NEXT: str z9, [x8, #10, mul vl]
-; CHECK-NEXT: mov z25.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p2.d, p0/z, z4.d, z1.d
-; CHECK-NEXT: str z8, [x8, #11, mul vl]
-; CHECK-NEXT: mov z5.d, p1/m, z27.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z7.d, z1.d
-; CHECK-NEXT: str z25, [x8, #12, mul vl]
-; CHECK-NEXT: mov z26.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.d, p0/z, z28.d, z28.d
-; CHECK-NEXT: mov z6.d, p2/m, z27.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z29.d, z1.d
-; CHECK-NEXT: str z26, [x8, #9, mul vl]
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z24.d, p4/m, z27.d
-; CHECK-NEXT: mov z12.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p5.d, p0/z, z29.d, z29.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z7.d, z7.d
-; CHECK-NEXT: sel z25.d, p6, z27.d, z31.d
-; CHECK-NEXT: str z12, [x8, #5, mul vl]
-; CHECK-NEXT: fcmuo p3.d, p0/z, z4.d, z4.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: mov z25.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z27.d, z2.d
-; CHECK-NEXT: mov z24.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p3/m, #0 // =0x0
+; CHECK-NEXT: frintx z30.d, p0/m, z30.d
+; CHECK-NEXT: frintx z31.d, p0/m, z31.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.d
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.d
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.d
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.d
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.d
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.d
+; CHECK-NEXT: fcvtzs z30.d, p0/m, z30.d
+; CHECK-NEXT: fcvtzs z31.d, p0/m, z31.d
+; CHECK-NEXT: str z0, [x8, #15, mul vl]
+; CHECK-NEXT: str z1, [x8, #14, mul vl]
+; CHECK-NEXT: str z2, [x8, #13, mul vl]
+; CHECK-NEXT: str z3, [x8, #12, mul vl]
+; CHECK-NEXT: str z4, [x8, #11, mul vl]
+; CHECK-NEXT: str z5, [x8, #10, mul vl]
+; CHECK-NEXT: str z6, [x8, #9, mul vl]
+; CHECK-NEXT: str z7, [x8, #8, mul vl]
+; CHECK-NEXT: str z24, [x8, #7, mul vl]
; CHECK-NEXT: str z25, [x8, #6, mul vl]
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z24, [x8, #3, mul vl]
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z6, [x8, #2, mul vl]
-; CHECK-NEXT: str z5, [x8, #1, mul vl]
-; CHECK-NEXT: str z0, [x8]
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: str z26, [x8, #5, mul vl]
+; CHECK-NEXT: str z27, [x8, #4, mul vl]
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: str z29, [x8, #2, mul vl]
+; CHECK-NEXT: str z30, [x8, #1, mul vl]
+; CHECK-NEXT: str z31, [x8]
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.lrint.nxv32i64.nxv16f64(<vscale x 32 x double> %x)
ret <vscale x 32 x i64> %a
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