[llvm-branch-commits] [lld] [llvm] [RFC][AMDGPU][lld] Add object linking support (PR #206787)

[Matt Arsenault via llvm-branch-commits]

================
@@ -0,0 +1,95 @@
+//===- AMDGPUIsaInfo.h - AMDGPU ISA info for cross-component use -*- C++
+//-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Public subset of AMDGPU ISA information needed by the linker (and
+// potentially other cross-component consumers) for subtarget queries and
+// register encoding.
+//
+// These are re-declarations of functions whose implementations live in the
+// AMDGPU target (AMDGPUBaseInfo.cpp). They are duplicated here so that
+// consumers outside the AMDGPU target tree can call them without including
+// target-private headers.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_AMDGPUISAINFO_H
+#define LLVM_SUPPORT_AMDGPUISAINFO_H
+
+#include "llvm/Support/Compiler.h"
+#include <cstdint>
+#include <optional>
+
+namespace llvm {
+
+class MCSubtargetInfo;
+
+namespace AMDGPU {
+
+/// \returns true if the subtarget has GFX90A instructions (unified VGPR/AGPR).
+LLVM_ABI bool isGFX90A(const MCSubtargetInfo &STI);
----------------
arsenm wrote:

TargetParser. All of these properties should be computable from the triple subarch. All ABI needs to be known from the freestanding IR module 

https://github.com/llvm/llvm-project/pull/206787