[llvm-branch-commits] [llvm] [AMDGPU] Add wave reduce intrinsics for double types - 2 (PR #170812)

[Matt Arsenault via llvm-branch-commits]

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@@ -5755,28 +5761,71 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
         break;
       }
       case AMDGPU::V_ADD_F32_e64:
+      case AMDGPU::V_ADD_F64_e64:
+      case AMDGPU::V_ADD_F64_e64_gfx12:
       case AMDGPU::V_SUB_F32_e64: {
-        Register ActiveLanesVreg =
-            MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
-        Register DstVreg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+        bool is32BitOpc = is32bitWaveReduceOperation(Opc);
+        const TargetRegisterClass *VregRC =
+            is32BitOpc ? &AMDGPU::VGPR_32RegClass : TRI->getVGPR64Class();
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arsenm wrote:

No, all the instructions return a VGPR use TII->getRegClass(TII->get(Opcode), 0)

https://github.com/llvm/llvm-project/pull/170812