[llvm-branch-commits] [llvm] [InlineSpiller][AMDGPU] Implement subreg reload during RA spill (PR #175002)

[Quentin Colombet via llvm-branch-commits]

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@@ -1248,18 +1249,62 @@ void InlineSpiller::spillAroundUses(Register Reg) {
 
     // Create a new virtual register for spill/fill.
     // FIXME: Infer regclass from instruction alone.
-    Register NewVReg = Edit->createFrom(Reg);
+
+    unsigned SubReg = 0;
+    LaneBitmask CoveringLanes = LaneBitmask::getNone();
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qcolombet wrote:

Ah right, I forgot we were doing that for every use!
I was afraid we may be leaving some live sublanes on the floor and that they could be read in a following use, but that's indeed not how we do things here.
Thanks for reminding me.

Let me take a closer look

https://github.com/llvm/llvm-project/pull/175002