[llvm-branch-commits] [clang] e4a114e - [RISCV]Remove experimental from Zalasr (#177120)
Cullen Rhodes via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Jan 22 23:47:48 PST 2026
Author: Liao Chunyu
Date: 2026-01-23T07:47:39Z
New Revision: e4a114e889cca86a0fc0cfbaf82360b5a7d66567
URL: https://github.com/llvm/llvm-project/commit/e4a114e889cca86a0fc0cfbaf82360b5a7d66567
DIFF: https://github.com/llvm/llvm-project/commit/e4a114e889cca86a0fc0cfbaf82360b5a7d66567.diff
LOG: [RISCV]Remove experimental from Zalasr (#177120)
Zalasr 1.0 was ratified in October 2025.
Documentation:https://docs.riscv.org/reference/isa/extensions/zalasr/_attachments/riscv-zalasr.pdf
(cherry picked from commit a43b55edf42b4e70e3b26e493e5997a2f5682fea)
Added:
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store.ll
llvm/test/CodeGen/RISCV/atomic-load-store.ll
llvm/test/CodeGen/RISCV/atomic-load-zext.ll
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/features-info.ll
llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32zalasr-invalid.s
llvm/test/MC/RISCV/rv64zalasr-invalid.s
llvm/test/MC/RISCV/rv64zalasr-valid.s
llvm/test/MC/RISCV/rvzalasr-valid.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 86459cac2739c..33f3342c66d42 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -39,6 +39,7 @@
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
// CHECK-NEXT: zabha 1.0 'Zabha' (Byte and Halfword Atomic Memory Operations)
// CHECK-NEXT: zacas 1.0 'Zacas' (Atomic Compare-And-Swap Instructions)
+// CHECK-NEXT: zalasr 1.0 'Zalasr' (Load-Acquire and Store-Release Instructions)
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
// CHECK-NEXT: zama16b 1.0 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)
// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set)
@@ -241,7 +242,6 @@
// CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate)
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
-// CHECK-NEXT: zalasr 0.9 'Zalasr' (Load-Acquire and Store-Release Instructions)
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
// CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 37fe7a0a0e644..f3b532d0b9bff 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -371,24 +371,30 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
// RV32-ZFHMIN: "-target-feature" "+zfhmin"
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izibi -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
-// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izalasr'
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izibi'
// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izibi -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
-// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izalasr'
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izibi'
// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr0p7 -menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izibi0p7 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
-// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izalasr0p7'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zalasr' (this compiler supports 0.9)
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izibi0p7'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zibi' (this compiler supports 0.1)
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p9 -menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izibi0p1 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
-// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zalasr"
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zibi"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZALASR %s
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZALASR %s
+// RV32-ZALASR: "-target-feature" "+zalasr"
// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso1p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZTSO %s
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 2563d83179795..6b21c9b51c188 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -80,6 +80,7 @@
// CHECK-NOT: __riscv_zaamo {{.*$}}
// CHECK-NOT: __riscv_zabha {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
+// CHECK-NOT: __riscv_zalasr {{.*$}}
// CHECK-NOT: __riscv_zalrsc {{.*$}}
// CHECK-NOT: __riscv_zama16b {{.*$}}
// CHECK-NOT: __riscv_zawrs {{.*$}}
@@ -177,7 +178,6 @@
// Experimental extensions
-// CHECK-NOT: __riscv_zalasr {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zvbc32e {{.*$}}
@@ -594,6 +594,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
// CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zalasr1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zalasr1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
+// CHECK-ZALASR-EXT: __riscv_zalasr 1000000{{$}}
+
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
@@ -1546,14 +1554,6 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 1000000{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zalasr0p9 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zalasr0p9 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
-// CHECK-ZALASR-EXT: __riscv_zalasr 9000{{$}}
-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index f1c79f166be1d..711fb56873551 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -172,6 +172,7 @@ on support follow.
``Zaamo`` Assembly Support
``Zabha`` Supported
``Zacas`` Supported (`See note <#riscv-zacas-note>`__)
+ ``Zalasr`` Supported
``Zalrsc`` Assembly Support
``Zama16b`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Zawrs`` Assembly Support
@@ -336,9 +337,6 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-p``
LLVM implements the `018 draft specification <https://www.jhauser.us/RISCV/ext-P/>`__.
-``experimental-zalasr``
- LLVM implements the `0.9 draft specification <https://github.com/riscv/riscv-zalasr/releases/tag/v0.9>`__.
-
``experimental-zibi``
LLVM implements the `0.1 release specification <https://github.com/riscv/zibi/releases/tag/v0.1.0>`__.
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 49e58fd225924..494371901e64d 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -270,7 +270,7 @@ def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
- : RISCVExperimentalExtension<0, 9, "Load-Acquire and Store-Release Instructions">;
+ : RISCVExtension<1, 0, "Load-Acquire and Store-Release Instructions">;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
index 4914357c3a2f6..643a7a44977d9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
@@ -23,14 +23,14 @@
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s
-; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d,+a,+experimental-zalasr -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d,+a,+zalasr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-WMO %s
-; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d,+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d,+a,+zalasr,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-TSO %s
-; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+experimental-zalasr -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+zalasr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-WMO %s
-; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+zalasr,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-TSO %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store.ll
index 5d3fed48bf82b..5a39ece02613b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store.ll
@@ -23,14 +23,14 @@
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+a,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s
-; RUN: llc -mtriple=riscv32 -global-isel -mattr=+a,+experimental-zalasr -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+a,+zalasr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-WMO %s
-; RUN: llc -mtriple=riscv32 -global-isel -mattr=+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+a,+zalasr,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-TSO %s
-; RUN: llc -mtriple=riscv64 -global-isel -mattr=+a,+experimental-zalasr -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+a,+zalasr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-WMO %s
-; RUN: llc -mtriple=riscv64 -global-isel -mattr=+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+a,+zalasr,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-TSO %s
define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
index c6234dedcef36..d17d994d4dd3c 100644
--- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
@@ -27,14 +27,14 @@
; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s
-; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zalasr -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+a,+zalasr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-WMO %s
-; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+a,+zalasr,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-TSO %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zalasr -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+a,+zalasr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-WMO %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+a,+zalasr,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-TSO %s
define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/atomic-load-zext.ll b/llvm/test/CodeGen/RISCV/atomic-load-zext.ll
index 68d6b127ac6f1..37da1a21bc266 100644
--- a/llvm/test/CodeGen/RISCV/atomic-load-zext.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-load-zext.ll
@@ -23,14 +23,14 @@
; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s
-; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zalasr -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+a,+zalasr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-WMO %s
-; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+a,+zalasr,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-TSO %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zalasr -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+a,+zalasr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-WMO %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+a,+zalasr,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-TSO %s
define zeroext i1 @atomic_load_i1_unordered(ptr %a) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index e24230926e270..dee2075db611e 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -133,7 +133,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfofp8min %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFOFP8MIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s
+; RUN: llc -mtriple=riscv32 -mattr=+zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s
; RUN: llc -mtriple=riscv32 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV32ZAMA16B %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
; RUN: llc -mtriple=riscv32 -mattr=+zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s
@@ -154,7 +154,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+a,no-trailing-seq-cst-fence --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s
; RUN: llc -mtriple=riscv64 -mattr=+a --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,experimental-zalasr --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64ZALASRA,A7 %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+zalasr --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64ZALASRA,A7 %s
; RUN: llc -mtriple=riscv64 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV64B %s
; RUN: llc -mtriple=riscv64 -mattr=+zba,+zbb,+zbs %s -o - | FileCheck --check-prefixes=CHECK,RV64COMBINEINTOB %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
@@ -284,7 +284,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfofp8min %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFOFP8MIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s
+; RUN: llc -mtriple=riscv64 -mattr=+zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
; RUN: llc -mtriple=riscv64 -mattr=+zabha %s -o - | FileCheck --check-prefix=RV64ZABHA %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV64ZVBC32E %s
@@ -449,7 +449,7 @@
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0"
; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0"
-; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p9"
+; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr1p0"
; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0"
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp1p0_zicsr2p0"
; RV32ZABHA: .attribute 5, "rv32i2p1_zaamo1p0_zabha1p0"
@@ -598,8 +598,8 @@
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0"
; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0"
-; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p9"
-; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr0p9_zalrsc1p0"
+; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr1p0"
+; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr1p0_zalrsc1p0"
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp1p0_zicsr2p0"
; RV64ZABHA: .attribute 5, "rv64i2p1_zaamo1p0_zabha1p0"
; RV64ZVBC32E: .attribute 5, "rv64i2p1_zicsr2p0_zvbc32e0p7_zve32x1p0_zvl32b1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 2ae36d3a41a25..e327fe73d8a47 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -34,7 +34,6 @@
; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips).
; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).
; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs).
-; CHECK-NEXT: experimental-zalasr - 'Zalasr' (Load-Acquire and Store-Release Instructions).
; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate).
; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad).
; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack).
@@ -254,6 +253,7 @@
; CHECK-NEXT: zaamo - 'Zaamo' (Atomic Memory Operations).
; CHECK-NEXT: zabha - 'Zabha' (Byte and Halfword Atomic Memory Operations).
; CHECK-NEXT: zacas - 'Zacas' (Atomic Compare-And-Swap Instructions).
+; CHECK-NEXT: zalasr - 'Zalasr' (Load-Acquire and Store-Release Instructions).
; CHECK-NEXT: zalrsc - 'Zalrsc' (Load-Reserved/Store-Conditional).
; CHECK-NEXT: zama16b - 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs).
; CHECK-NEXT: zawrs - 'Zawrs' (Wait on Reservation Set).
diff --git a/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll b/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
index 78653ba3b78ef..2b4d8c5b4bb94 100644
--- a/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
+++ b/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=riscv32 -mattr=+a,+experimental-zalasr | FileCheck %s
+; RUN: llc < %s -mtriple=riscv32 -mattr=+a,+zalasr | FileCheck %s
; Make sure we don't fold -1920 into the lw instruction because we still
; need it for the sw.rl.
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 98c2a09d9d7fa..62ac423fb3779 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -423,8 +423,8 @@
.attribute arch, "rv32ia_zacas1p0"
# CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0"
-.attribute arch, "rv32izalasr0p9"
-# CHECK: attribute 5, "rv32i2p1_zalasr0p9"
+.attribute arch, "rv32izalasr1p0"
+# CHECK: attribute 5, "rv32i2p1_zalasr1p0"
.attribute arch, "rv32i_xcvalu"
# CHECK: attribute 5, "rv32i2p1_xcvalu1p0"
diff --git a/llvm/test/MC/RISCV/rv32zalasr-invalid.s b/llvm/test/MC/RISCV/rv32zalasr-invalid.s
index 3731c85cbc077..86cce98998514 100644
--- a/llvm/test/MC/RISCV/rv32zalasr-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zalasr-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s
# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
ld.aq a1, (t0)
diff --git a/llvm/test/MC/RISCV/rv64zalasr-invalid.s b/llvm/test/MC/RISCV/rv64zalasr-invalid.s
index 032c0c00882cb..d289e731dc285 100644
--- a/llvm/test/MC/RISCV/rv64zalasr-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zalasr-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s
# CHECK: error: unrecognized instruction mnemonic
lw. a1, (t0)
diff --git a/llvm/test/MC/RISCV/rv64zalasr-valid.s b/llvm/test/MC/RISCV/rv64zalasr-valid.s
index 13d2b21fe6f3d..6613cf3a1c8ee 100644
--- a/llvm/test/MC/RISCV/rv64zalasr-valid.s
+++ b/llvm/test/MC/RISCV/rv64zalasr-valid.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalasr -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zalasr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalasr < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zalasr < %s \
+# RUN: | llvm-objdump --mattr=+zalasr -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv64 \
diff --git a/llvm/test/MC/RISCV/rvzalasr-valid.s b/llvm/test/MC/RISCV/rvzalasr-valid.s
index 11487ee7597a8..90ec86c19ad5e 100644
--- a/llvm/test/MC/RISCV/rvzalasr-valid.s
+++ b/llvm/test/MC/RISCV/rvzalasr-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zalasr -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zalasr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zalasr < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zalasr < %s \
+# RUN: | llvm-objdump --mattr=+zalasr -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalasr -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zalasr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalasr < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zalasr < %s \
+# RUN: | llvm-objdump --mattr=+zalasr -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 \
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 4286f30e496d7..4439df755d79d 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -536,52 +536,51 @@ TEST(ParseArchString, RejectsDuplicateExtensionNames) {
TEST(ParseArchString,
RejectsExperimentalExtensionsIfNotEnableExperimentalExtension) {
EXPECT_EQ(
- toString(RISCVISAInfo::parseArchString("rv64izalasr", false).takeError()),
+ toString(RISCVISAInfo::parseArchString("rv64izibi", false).takeError()),
"requires '-menable-experimental-extensions' for experimental extension "
- "'zalasr'");
+ "'zibi'");
}
TEST(ParseArchString,
AcceptsExperimentalExtensionsIfEnableExperimentalExtension) {
- // Note: If zalasr becomes none-experimental, this test will need
+ // Note: If zibi becomes none-experimental, this test will need
// updating (and unfortunately, it will still pass). The failure of
// RejectsExperimentalExtensionsIfNotEnableExperimentalExtension will
// hopefully serve as a reminder to update.
- auto MaybeISAInfo = RISCVISAInfo::parseArchString("rv64izalasr", true, false);
+ auto MaybeISAInfo = RISCVISAInfo::parseArchString("rv64izibi", true, false);
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
const auto &Exts = (*MaybeISAInfo)->getExtensions();
EXPECT_EQ(Exts.size(), 2UL);
- EXPECT_EQ(Exts.count("zalasr"), 1U);
- auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izalasr0p9", true);
+ EXPECT_EQ(Exts.count("zibi"), 1U);
+ auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izibi0p1", true);
ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded());
const auto &Exts2 = (*MaybeISAInfo2)->getExtensions();
EXPECT_EQ(Exts2.size(), 2UL);
- EXPECT_EQ(Exts2.count("zalasr"), 1U);
+ EXPECT_EQ(Exts2.count("zibi"), 1U);
}
TEST(ParseArchString,
RequiresExplicitVersionNumberForExperimentalExtensionByDefault) {
EXPECT_EQ(
- toString(RISCVISAInfo::parseArchString("rv64izalasr", true).takeError()),
- "experimental extension requires explicit version number `zalasr`");
+ toString(RISCVISAInfo::parseArchString("rv64izibi", true).takeError()),
+ "experimental extension requires explicit version number `zibi`");
}
TEST(ParseArchString,
AcceptsUnrecognizedVersionIfNotExperimentalExtensionVersionCheck) {
auto MaybeISAInfo =
- RISCVISAInfo::parseArchString("rv64izalasr9p9", true, false);
+ RISCVISAInfo::parseArchString("rv64izibi9p9", true, false);
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
const auto &Exts = (*MaybeISAInfo)->getExtensions();
EXPECT_EQ(Exts.size(), 2UL);
- EXPECT_TRUE(Exts.at("zalasr") == (RISCVISAUtils::ExtensionVersion{9, 9}));
+ EXPECT_TRUE(Exts.at("zibi") == (RISCVISAUtils::ExtensionVersion{9, 9}));
}
TEST(ParseArchString, RejectsUnrecognizedVersionForExperimentalExtension) {
EXPECT_EQ(
- toString(
- RISCVISAInfo::parseArchString("rv64izalasr9p9", true).takeError()),
- "unsupported version number 9.9 for experimental extension 'zalasr' "
- "(this compiler supports 0.9)");
+ toString(RISCVISAInfo::parseArchString("rv64izibi9p9", true).takeError()),
+ "unsupported version number 9.9 for experimental extension 'zibi' "
+ "(this compiler supports 0.1)");
}
TEST(ParseArchString, RejectsExtensionVersionForG) {
@@ -832,13 +831,13 @@ TEST(ToFeatures, IIsDroppedAndExperimentalExtensionsArePrefixed) {
RISCVISAInfo::parseArchString("rv64im_zalasr", true, false);
ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded());
EXPECT_THAT((*MaybeISAInfo1)->toFeatures(),
- ElementsAre("+i", "+m", "+zmmul", "+experimental-zalasr"));
+ ElementsAre("+i", "+m", "+zmmul", "+zalasr"));
auto MaybeISAInfo2 = RISCVISAInfo::parseArchString(
"rv32e_zalasr_xventanacondops", true, false);
ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded());
EXPECT_THAT((*MaybeISAInfo2)->toFeatures(),
- ElementsAre("+e", "+experimental-zalasr", "+xventanacondops"));
+ ElementsAre("+e", "+zalasr", "+xventanacondops"));
}
TEST(ToFeatures, UnsupportedExtensionsAreDropped) {
@@ -1192,6 +1191,7 @@ R"(All available -march extensions for RISC-V
zaamo 1.0
zabha 1.0
zacas 1.0
+ zalasr 1.0
zalrsc 1.0
zama16b 1.0
zawrs 1.0
@@ -1394,7 +1394,6 @@ Experimental extensions
zibi 0.1
zicfilp 1.0 This is a long dummy description
zicfiss 1.0
- zalasr 0.9
zvbc32e 0.7
zvfbfa 0.1
zvfofp8min 0.2
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