[llvm-branch-commits] [RISC-V][MC] Introduce initial support RVY (CHERI) (PR #176871)

[Alexander Richardson via llvm-branch-commits]

================
@@ -727,6 +763,9 @@ static constexpr DecoderListEntry DecoderList32[]{
     {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
     {DecoderTableXAIF32, XAIFGroup, "AI Foundry extensions"},
     // Standard Extensions
+    {DecoderTableRVYOnly32,
+     {RISCV::FeatureStdExtY},
+     "RVY-only standard 32-bit instructions"},
----------------
arichardson wrote:

Seems like I spoke too soon. Tablegen no longer complains, but we are now unable to disassemble the instruction. Will try to debug this a bit more today.

https://github.com/llvm/llvm-project/pull/176871