[llvm-branch-commits] [RISC-V][MC] Introduce initial support RVY (CHERI) (PR #176871)

[Alexander Richardson via llvm-branch-commits]

https://github.com/arichardson created https://github.com/llvm/llvm-project/pull/176871

This adds MC-level support for most of the base Y extension instructions,
restricted to the execution-mode-independent subset. The Y extension
(CHERI for RISC-V) also introduces an execution mode that determines
whether certain register operands use the full extended register or only
the address subset (the current XLEN registers). The instructions that
depend on execution mode (loads/stores/jumps + AUIPC) will be added in
the following commits in this stack of changes.

Co-authored-by: Jessica Clarke <jrtc27 at jrtc27.com>
Co-authored-by: Alexander Richardson <alexrichardson at google.com>
Co-authored-by: Petr Vesely <petr.vesely at codasip.com>