[llvm-branch-commits] [llvm] [CodeGen][NPM] Add "PhysicalRegisterUsageAnalysis" once (PR #173489)

[Vikram Hegde via llvm-branch-commits]

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/173489

>From 97b47142cd69e9a23cff0116ab8e8cf32a062352 Mon Sep 17 00:00:00 2001
From: vikhegde <vikram.hegde at amd.com>
Date: Wed, 24 Dec 2025 12:03:33 +0530
Subject: [PATCH] [CodeGen][NPM] Add "PhysicalRegisterUsageAnalysis" once

---
 llvm/include/llvm/Passes/CodeGenPassBuilder.h |  5 +----
 llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll  | 15 ++++++---------
 2 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 005b695741903..c4a4787c34a25 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -965,7 +965,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses(
   if (TM.Options.EnableIPRA) {
     flushFPMsToMPM(PMW);
     addModulePass(RequireAnalysisPass<PhysicalRegisterUsageAnalysis, Module>(),
-                  PMW);
+                  PMW, /*Force=*/true);
     addMachineFunctionPass(RegUsageInfoPropagationPass(), PMW);
   }
   // Run pre-ra passes.
@@ -1036,9 +1036,6 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses(
   if (TM.Options.EnableIPRA) {
     // Collect register usage information and produce a register mask of
     // clobbered registers, to be used to optimize call sites.
-    flushFPMsToMPM(PMW);
-    addModulePass(RequireAnalysisPass<PhysicalRegisterUsageAnalysis, Module>(),
-                  PMW);
     addMachineFunctionPass(RegUsageInfoCollectorPass(), PMW);
     // If -print-regusage is specified, print the collected register usage info.
     if (Opt.PrintRegUsage) {
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
index 9f8607d1bcd0c..ae64d33cc0b43 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
@@ -75,9 +75,8 @@
 ; GCN-O0-NEXT:post-RA-hazard-rec
 ; GCN-O0-NEXT:amdgpu-wait-sgpr-hazards
 ; GCN-O0-NEXT:amdgpu-lower-vgpr-encoding
-; GCN-O0-NEXT:branch-relaxation)))
-; GCN-O0-NEXT:require<reg-usage>
-; GCN-O0-NEXT:cgscc(function(machine-function(reg-usage-collector
+; GCN-O0-NEXT:branch-relaxation
+; GCN-O0-NEXT:reg-usage-collector
 ; GCN-O0-NEXT:remove-loads-into-fake-uses
 ; GCN-O0-NEXT:live-debug-values
 ; GCN-O0-NEXT:machine-sanmd
@@ -247,9 +246,8 @@
 ; GCN-O2-NEXT:amdgpu-wait-sgpr-hazards
 ; GCN-O2-NEXT:amdgpu-lower-vgpr-encoding
 ; GCN-O2-NEXT:amdgpu-insert-delay-alu
-; GCN-O2-NEXT:branch-relaxation)))
-; GCN-O2-NEXT:require<reg-usage>
-; GCN-O2-NEXT:cgscc(function(machine-function(reg-usage-collector
+; GCN-O2-NEXT:branch-relaxation
+; GCN-O2-NEXT:reg-usage-collector
 ; GCN-O2-NEXT:remove-loads-into-fake-uses
 ; GCN-O2-NEXT:live-debug-values
 ; GCN-O2-NEXT:machine-sanmd
@@ -419,9 +417,8 @@
 ; GCN-O3-NEXT:amdgpu-wait-sgpr-hazards
 ; GCN-O3-NEXT:amdgpu-lower-vgpr-encoding
 ; GCN-O3-NEXT:amdgpu-insert-delay-alu
-; GCN-O3-NEXT:branch-relaxation)))
-; GCN-O3-NEXT:require<reg-usage>
-; GCN-O3-NEXT:cgscc(function(machine-function(reg-usage-collector
+; GCN-O3-NEXT:branch-relaxation
+; GCN-O3-NEXT:reg-usage-collector
 ; GCN-O3-NEXT:remove-loads-into-fake-uses
 ; GCN-O3-NEXT:live-debug-values
 ; GCN-O3-NEXT:machine-sanmd