[llvm-branch-commits] [llvm] [AMDGPU] Enable ISD::{FSIN, FCOS} custom lowering to work on v2f16 (PR #176382)

[Matt Arsenault via llvm-branch-commits]

================
@@ -10098,10 +10129,10 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   case Intrinsic::amdgcn_fdiv_fast:
     return lowerFDIV_FAST(Op, DAG);
   case Intrinsic::amdgcn_sin:
-    return DAG.getNode(AMDGPUISD::SIN_HW, DL, VT, Op.getOperand(1));
+    return BuildScalarizedUnaryOp(Op, AMDGPUISD::SIN_HW, 1, DAG);
----------------
arsenm wrote:

This should never been emitted as vector 

https://github.com/llvm/llvm-project/pull/176382