[llvm-branch-commits] [llvm] [AMDGPU] Enable ISD::{FSIN, FCOS} custom lowering to work on v2f16 (PR #176382)

[Matt Arsenault via llvm-branch-commits]

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@@ -9876,6 +9878,35 @@ SDValue SITargetLowering::lowerWorkitemID(SelectionDAG &DAG, SDValue Op,
                      DAG.getValueType(SmallVT));
 }
 
+/// Helper function for LowerINTRINSIC_WO_CHAIN.  Replace a \p Op of
+/// scalar type with a new node \p NewISD node with one argument which
+/// is the operand at index \p OperandIndex of Op.  Scalarizes for
+/// vector types.
+///
+// FIXME The manual scalarization seems to be necessary because the
+// Expand fallback is not supported for ISD::INTRINSIC_WO_CHAIN and
+// hence the lowering function should not fail for v2f16; see comment
+// in SelectionDAGLegalize::ExpandNode.
+static SDValue BuildScalarizedUnaryOp(SDValue Op, unsigned NewISD,
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arsenm wrote:

This is DAG.UnrollVectorOp

https://github.com/llvm/llvm-project/pull/176382