[llvm-branch-commits] [llvm] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)
Pengcheng Wang via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sun Jan 11 19:57:19 PST 2026
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/172615
>From b85f43932660cd181d7358a8ed0f4877640210f6 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Thu, 18 Dec 2025 15:24:52 +0800
Subject: [PATCH] Address comments
Created using spr 1.3.6-beta.1
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 39 ++++++++++++++-----
.../Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp | 21 ++--------
.../Target/RISCV/RISCVVSETVLIInfoAnalysis.h | 26 +++----------
3 files changed, 37 insertions(+), 49 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index e5c3dc66cb18b..8ba00c815fa0e 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -68,13 +68,33 @@ static unsigned getVLOpNum(const MachineInstr &MI) {
return RISCVII::getVLOpNum(MI.getDesc());
}
+struct BlockData {
+ // The VSETVLIInfo that represents the VL/VTYPE settings on exit from this
+ // block. Calculated in Phase 2.
+ VSETVLIInfo Exit;
+
+ // The VSETVLIInfo that represents the VL/VTYPE settings from all predecessor
+ // blocks. Calculated in Phase 2, and used by Phase 3.
+ VSETVLIInfo Pred;
+
+ // Keeps track of whether the block is already in the queue.
+ bool InQueue = false;
+
+ BlockData() = default;
+};
+
+enum TKTMMode {
+ VSETTK = 0,
+ VSETTM = 1,
+};
+
class RISCVInsertVSETVLI : public MachineFunctionPass {
const RISCVSubtarget *ST;
const TargetInstrInfo *TII;
MachineRegisterInfo *MRI;
// Possibly null!
LiveIntervals *LIS;
- RISCVVSETVLIInfoAnalysis *VIA;
+ RISCVVSETVLIInfoAnalysis VIA;
std::vector<BlockData> BlockInfo;
std::queue<const MachineBasicBlock *> WorkList;
@@ -179,7 +199,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg()) {
if (const MachineInstr *DefMI = Info.getAVLDefMI(LIS);
DefMI && RISCVInstrInfo::isVectorConfigInstr(*DefMI)) {
- VSETVLIInfo DefInfo = VIA->getInfoForVSETVLI(*DefMI);
+ VSETVLIInfo DefInfo = VIA.getInfoForVSETVLI(*DefMI);
if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
auto MI =
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0X0))
@@ -311,7 +331,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
DemandedFields Demanded = getDemanded(MI, ST);
- const VSETVLIInfo NewInfo = VIA->computeInfoForInstr(MI);
+ const VSETVLIInfo NewInfo = VIA.computeInfoForInstr(MI);
assert(NewInfo.isValid() && !NewInfo.isUnknown());
if (Info.isValid() && !needVSETVLI(Demanded, NewInfo, Info))
return;
@@ -362,7 +382,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
const MachineInstr &MI) const {
if (RISCVInstrInfo::isVectorConfigInstr(MI)) {
- Info = VIA->getInfoForVSETVLI(MI);
+ Info = VIA.getInfoForVSETVLI(MI);
return;
}
@@ -493,7 +513,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
// We found a VSET(I)VLI make sure it matches the output of the
// predecessor block.
- VSETVLIInfo DefInfo = VIA->getInfoForVSETVLI(*DefMI);
+ VSETVLIInfo DefInfo = VIA.getInfoForVSETVLI(*DefMI);
if (DefInfo != PBBExit)
return true;
@@ -736,8 +756,8 @@ bool RISCVInsertVSETVLI::canMutatePriorConfig(
if (Used.VLZeroness) {
if (RISCVInstrInfo::isVLPreservingConfig(PrevMI))
return false;
- if (!VIA->getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(
- VIA->getInfoForVSETVLI(MI), LIS))
+ if (!VIA.getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(
+ VIA.getInfoForVSETVLI(MI), LIS))
return false;
}
@@ -925,7 +945,7 @@ bool RISCVInsertVSETVLI::insertVSETMTK(MachineBasicBlock &MBB,
!RISCVII::hasSEWOp(TSFlags) || !RISCVII::hasTWidenOp(TSFlags))
continue;
- VSETVLIInfo CurrInfo = VIA->computeInfoForInstr(MI);
+ VSETVLIInfo CurrInfo = VIA.computeInfoForInstr(MI);
if (Mode == VSETTK && !RISCVII::hasTKOp(TSFlags))
continue;
@@ -986,8 +1006,7 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo();
auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
- RISCVVSETVLIInfoAnalysis SETVLIInfoAnalysis(ST, LIS);
- VIA = &SETVLIInfoAnalysis;
+ VIA = RISCVVSETVLIInfoAnalysis(ST, LIS);
assert(BlockInfo.empty() && "Expect empty block infos");
BlockInfo.resize(MF.getNumBlockIDs());
diff --git a/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp b/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
index 4d586c0455d96..3fa9baea6de14 100644
--- a/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
@@ -1,4 +1,4 @@
-//===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---------------===//
+//===- RISCVVSETVLIInfoAnalysis.cpp - VSETVLI Info Analysis ---------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,21 +6,8 @@
//
//===----------------------------------------------------------------------===//
//
-// This file implements a function pass that inserts VSETVLI instructions where
-// needed and expands the vl outputs of VLEFF/VLSEGFF to PseudoReadVL
-// instructions.
-//
-// This pass consists of 3 phases:
-//
-// Phase 1 collects how each basic block affects VL/VTYPE.
-//
-// Phase 2 uses the information from phase 1 to do a data flow analysis to
-// propagate the VL/VTYPE changes through the function. This gives us the
-// VL/VTYPE at the start of each basic block.
-//
-// Phase 3 inserts VSETVLI instructions in each basic block. Information from
-// phase 2 is used to prevent inserting a VSETVLI before the first vector
-// instruction in the block if possible.
+// This file implements an analysis of the vtype/vl information that is needed
+// by RISCVInsertVSETVLI pass and others.
//
//===----------------------------------------------------------------------===//
@@ -28,8 +15,6 @@
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/LiveIntervals.h"
-#define DEBUG_TYPE "riscv-vsetvli-info"
-
namespace llvm {
namespace RISCV {
diff --git a/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h b/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h
index 84700375d2f07..ec8b8c3fc9812 100644
--- a/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h
+++ b/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h
@@ -1,4 +1,4 @@
-//===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---------------===//
+//===- RISCVVSETVLIInfoAnalysis.h - VSETVLI Info Analysis -----------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,6 +6,9 @@
//
//===----------------------------------------------------------------------===//
//
+// This file implements an analysis of the vtype/vl information that is needed
+// by RISCVInsertVSETVLI pass and others.
+//
//===----------------------------------------------------------------------===//
#include "RISCV.h"
@@ -565,32 +568,13 @@ inline raw_ostream &operator<<(raw_ostream &OS, const VSETVLIInfo &V) {
}
#endif
-struct BlockData {
- // The VSETVLIInfo that represents the VL/VTYPE settings on exit from this
- // block. Calculated in Phase 2.
- VSETVLIInfo Exit;
-
- // The VSETVLIInfo that represents the VL/VTYPE settings from all predecessor
- // blocks. Calculated in Phase 2, and used by Phase 3.
- VSETVLIInfo Pred;
-
- // Keeps track of whether the block is already in the queue.
- bool InQueue = false;
-
- BlockData() = default;
-};
-
-enum TKTMMode {
- VSETTK = 0,
- VSETTM = 1,
-};
-
class RISCVVSETVLIInfoAnalysis {
const RISCVSubtarget *ST;
// Possibly null!
LiveIntervals *LIS;
public:
+ RISCVVSETVLIInfoAnalysis() = default;
RISCVVSETVLIInfoAnalysis(const RISCVSubtarget *ST, LiveIntervals *LIS)
: ST(ST), LIS(LIS) {}
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