[llvm-branch-commits] [llvm] [RISCV] Schedule RVV instructions with compatible vtype/vl first (PR #95924)

[Min-Yih Hsu via llvm-branch-commits]

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@@ -13,6 +13,54 @@ using namespace llvm;
 
 #define DEBUG_TYPE "riscv-prera-sched-strategy"
 
+RISCV::VSETVLIInfo
+RISCVPreRAMachineSchedStrategy::getVSETVLIInfo(const MachineInstr *MI) const {
+  unsigned TSFlags = MI->getDesc().TSFlags;
+  if (!RISCVII::hasSEWOp(TSFlags))
+    return RISCV::VSETVLIInfo();
+  return VIA.computeInfoForInstr(*MI);
+}
+
+bool RISCVPreRAMachineSchedStrategy::tryVSETVLIInfo(RISCV::VSETVLIInfo TryInfo,
+                                                    RISCV::VSETVLIInfo CandInfo,
+                                                    SchedCandidate &TryCand,
+                                                    SchedCandidate &Cand,
+                                                    CandReason Reason) const {
+  // Do not compare the vsetvli info changes between top and bottom
+  // boundary.
+  if (Cand.AtTop != TryCand.AtTop)
+    return false;
+
+  auto IsCompatible = [&](RISCV::VSETVLIInfo FirstInfo,
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mshockwave wrote:

`const RISCV::VSETVLIInfo &`? unlike `tryVSETVLIInfo` 's arguments I don't think there is any move-elimination we can do here

https://github.com/llvm/llvm-project/pull/95924