[llvm-branch-commits] [llvm] [AMDGPU] Canonicalize NAN values for float reduction intrinsics (PR #175131)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 362d25e3b..34e693569 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5864,8 +5864,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
           .addReg(SrcReg)
           .addReg(FF1Reg);
       if (isFPOp) {
-        bool IsMinMaxOpc = Opc == AMDGPU::V_MIN_F32_e64 || Opc == AMDGPU::V_MAX_F32_e64;
-        bool NeedsNANCanonicalization = IsMinMaxOpc && (IsIEEEMode || IsGFX12Plus);
+        bool IsMinMaxOpc =
+            Opc == AMDGPU::V_MIN_F32_e64 || Opc == AMDGPU::V_MAX_F32_e64;
+        bool NeedsNANCanonicalization =
+            IsMinMaxOpc && (IsIEEEMode || IsGFX12Plus);
         Register LaneValVreg =
             MRI.createVirtualRegister(MRI.getRegClass(SrcReg));
         Register DstVreg = MRI.createVirtualRegister(MRI.getRegClass(SrcReg));

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https://github.com/llvm/llvm-project/pull/175131