[llvm-branch-commits] [llvm] [InlineSpiller][AMDGPU] Implement subreg reload during RA spill (PR #175002)

[Christudasan Devadasan via llvm-branch-commits]

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@@ -1220,6 +1220,11 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
     return true;
   }
 
+  /// To enable subreg reload of register tuples during RA. This would
+  /// eventually improve the register allocation for the functions that involve
+  /// subreg uses instead of the entire tuple.
+  virtual bool shouldEnableSubRegReload(unsigned SubReg) const { return false; }
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cdevadas wrote:

Yep, that's something even I prefer. But the targets need to reimplement their `loadRegFromStackSlot` to insert subreg reload. Without that, we can't just trim the Register Class and create a new virtual register based on the new RC. Having a separate switch would allow us to control that.

https://github.com/llvm/llvm-project/pull/175002