[llvm-branch-commits] [llvm] [AArch64] Let LoadStoreOptimizer handle renamable implicit-defs. (PR #174186)

[Gaëtan Bossu via llvm-branch-commits]

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@@ -78,3 +78,32 @@ body:             |
     $q1 = ORRv16i8 $q5, killed $q5
     RET_ReallyLR
 ...
+# Test that when the implicit-def is renamable, the loads/stores can still be
+# bundled together.
+---
+name:            impdef_renamable
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: '', type: default, offset: -8, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -8, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+  - { id: 1, name: '', type: default, offset: -16, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -16, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: impdef_renamable
+    ; CHECK: early-clobber $sp, renamable $w8, $w9 = frame-setup LDPWpre $sp, -4 :: (load (s32) from %stack.1 + 4), (load (s32) from %stack.1, align 8)
+    ; CHECK-NEXT: STPWi killed renamable $w8, killed $w9, $sp, 2 :: (store (s32) into %stack.0 + 4), (store (s32) into %stack.0, align 8)
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gbossu wrote:

Curious: Is that rewriting of the `MemoryOperand`s correct? I might not remember correctly, but I thought that when an instruction has multiple MOs, and one of them tells `NoAlias` when compared to the `MO` of another instructions, then the instructions are assumed not to alias, even though not all `MachineOperands` were actually checked.

I hope my recollection is wrong, but if it is not, we should instead rewrite the two MOs into a single `(store (s64) into %stack.0, align 8)`.

https://github.com/llvm/llvm-project/pull/174186