[llvm-branch-commits] [llvm] [RISCV] Schedule RVV instructions with compatible type first (PR #95924)

[Pengcheng Wang via llvm-branch-commits]

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@@ -13,19 +13,35 @@
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINESCHEDULER_H
 #define LLVM_LIB_TARGET_RISCV_RISCVMACHINESCHEDULER_H
 
+#include "RISCVSubtarget.h"
+#include "RISCVVSETVLIInfoAnalysis.h"
 #include "llvm/CodeGen/MachineScheduler.h"
 
 namespace llvm {
 
 /// A GenericScheduler implementation for RISCV pre RA scheduling.
 class RISCVPreRAMachineSchedStrategy : public GenericScheduler {
+private:
+  RISCV::RISCVVSETVLIInfoAnalysis VIA;
+  RISCV::VSETVLIInfo TopVType;
+  RISCV::VSETVLIInfo BottomVType;
+
+  RISCV::VSETVLIInfo getVSETVLIInfo(const MachineInstr *MI) const;
+  bool tryVType(RISCV::VSETVLIInfo TryVType, RISCV::VSETVLIInfo CandVtype,
+                SchedCandidate &TryCand, SchedCandidate &Cand,
+                CandReason Reason) const;
+
 public:
   RISCVPreRAMachineSchedStrategy(const MachineSchedContext *C)
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wangpc-pp wrote:

Constructor parameter may not be feasible as `createSchedLive` doesn't accept extra parameters.  I can make it a tune option in processor definitions.

https://github.com/llvm/llvm-project/pull/95924