[llvm-branch-commits] [llvm] [AArch64] Add new pass after VirtRegRewriter to add implicit-defs (PR #174188)

[via llvm-branch-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp llvm/lib/Target/AArch64/AArch64.h llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp llvm/lib/Target/AArch64/AArch64Subtarget.cpp llvm/lib/Target/AArch64/AArch64Subtarget.h llvm/lib/Target/AArch64/AArch64TargetMachine.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp b/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
index 695155abc..98ad74791 100644
--- a/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
@@ -109,8 +109,8 @@ struct AArch64SRLTDefineSuperRegs : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   void collectWidestSuperReg(Register R, const BitVector &RequiredBaseRegUnits,
-                 const BitVector &QHiRegUnits,
-                 SmallSet<Register, 8> &SuperRegs);
+                             const BitVector &QHiRegUnits,
+                             SmallSet<Register, 8> &SuperRegs);
 
   StringRef getPassName() const override { return PASS_NAME; }
 
@@ -132,8 +132,7 @@ private:
 
 } // end anonymous namespace
 
-INITIALIZE_PASS(AArch64SRLTDefineSuperRegs, DEBUG_TYPE, PASS_NAME, false,
-                false)
+INITIALIZE_PASS(AArch64SRLTDefineSuperRegs, DEBUG_TYPE, PASS_NAME, false, false)
 
 SmallVector<MCRegister> SupportedAliasRegs = {
     AArch64::X0,  AArch64::X1,  AArch64::X2,  AArch64::X3,  AArch64::X4,
@@ -184,7 +183,8 @@ void AArch64SRLTDefineSuperRegs::collectWidestSuperReg(
       if (QHiRegUnits.test((unsigned)U) &&
           !Subtarget->isSVEorStreamingSVEAvailable())
         return false;
-      // We consider reg A as a suitable super-reg of B when any of the reg units:
+      // We consider reg A as a suitable super-reg of B when any of the reg
+      // units:
       // * is shared (Q0 and B0, both have B0 as sub-register)
       // * is artificial (Q0 = B0 + (B0_HI + H0_HI + S0_HI))
       // This avoids considering e.g. Q0_Q1 as a super reg of D0 or D1.

``````````

</details>


https://github.com/llvm/llvm-project/pull/174188