[llvm-branch-commits] [ARM] Fix more typos (NFC) (PR #183087)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/ARM/A15SDOptimizer.cpp llvm/lib/Target/ARM/ARMAsmPrinter.cpp llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/lib/Target/ARM/ARMCallLowering.cpp llvm/lib/Target/ARM/ARMConstantIslandPass.cpp llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/lib/Target/ARM/ARMFrameLowering.cpp llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/lib/Target/ARM/ARMParallelDSP.cpp llvm/lib/Target/ARM/ARMSLSHardening.cpp llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp llvm/lib/Target/ARM/ARMSubtarget.cpp llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp llvm/lib/Target/ARM/MLxExpansionPass.cpp llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp llvm/lib/Target/ARM/MVETailPredication.cpp llvm/lib/Target/ARM/Thumb1FrameLowering.cpp llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 276736333..aa88d0580 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -2532,7 +2532,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
       case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
       case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
       case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
-      default: llvm_unreachable("unexpected conditional move");
+      default:
+        llvm_unreachable("unexpected conditional move");
       }
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
               MI.getOperand(1).getReg())
diff --git a/llvm/lib/Target/ARM/MLxExpansionPass.cpp b/llvm/lib/Target/ARM/MLxExpansionPass.cpp
index 6b41a63aa..8336122fd 100644
--- a/llvm/lib/Target/ARM/MLxExpansionPass.cpp
+++ b/llvm/lib/Target/ARM/MLxExpansionPass.cpp
@@ -28,8 +28,8 @@ using namespace llvm;
 
 #define DEBUG_TYPE "mlx-expansion"
 
-static cl::opt<bool>
-ForceExpand("expand-all-fp-mlx", cl::init(false), cl::Hidden);
+static cl::opt<bool> ForceExpand("expand-all-fp-mlx", cl::init(false),
+                                 cl::Hidden);
 static cl::opt<unsigned>
 ExpandLimit("expand-limit", cl::init(~0U), cl::Hidden);
 
diff --git a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
index 0b97cd594..d6d1d2534 100644
--- a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
+++ b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
@@ -70,5 +70,5 @@ const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) {
 namespace ARMBankedReg {
 #define GET_BankedRegsList_IMPL
 #include "ARMGenSystemRegister.inc"
-} // end namespace ARMSysReg
+} // namespace ARMBankedReg
 } // end namespace llvm

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https://github.com/llvm/llvm-project/pull/183087