[llvm-branch-commits] [llvm] release/22.x: [RISCV] Remove VMConstraint from VAESKF1_VI/VAESKF2_VI. (#181887) (PR #182309)

[via llvm-branch-commits]

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/182309

Backport 6eae175

Requested by: @topperc

>From 402b468b2af72c164743aa2d802433ecdc164276 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 17 Feb 2026 20:03:39 -0800
Subject: [PATCH] [RISCV] Remove VMConstraint from VAESKF1_VI/VAESKF2_VI.
 (#181887)

These instructions don't have a VM operand. If these instructions use a
V0 destination, the VMConstraint code calls getReg() on the the last
operand which is an immediate. This triggers an assertion. Not sure
what happens on a release build. It probably treats the immediate as a
value in the RISCV register info enum.

(cherry picked from commit 6eae1759f2c08fcd36b3673c6603297ba3f8d7d3)
---
 llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 10 ++++++----
 llvm/test/MC/RISCV/rvv/zvkned.s            | 12 ++++++++++++
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 5a5a9edebd925..e4c76d7810c4b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -176,10 +176,12 @@ let Predicates = [HasStdExtZvkned] in {
   defm VAESDM     : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
   defm VAESEF     : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
   defm VAESEM     : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
-  def  VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
-                    SchedUnaryMC<"WriteVAESKF1V", "ReadVAESKF1V">;
-  def  VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,
-                    SchedBinaryMC<"WriteVAESKF2V", "ReadVAESKF2V", "ReadVAESKF2V">;
+  let RVVConstraint = NoConstraint in {
+    def  VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
+                      SchedUnaryMC<"WriteVAESKF1V", "ReadVAESKF1V">;
+    def  VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,
+                      SchedBinaryMC<"WriteVAESKF2V", "ReadVAESKF2V", "ReadVAESKF2V">;
+  }
   let RVVConstraint = VS2Constraint in
   def  VAESZ_VS   : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">,
                     SchedBinaryMC<"WriteVAESZV", "ReadVAESZV", "ReadVAESZV">;
diff --git a/llvm/test/MC/RISCV/rvv/zvkned.s b/llvm/test/MC/RISCV/rvv/zvkned.s
index bee3d74ee88dc..6bd2b14bc428b 100644
--- a/llvm/test/MC/RISCV/rvv/zvkned.s
+++ b/llvm/test/MC/RISCV/rvv/zvkned.s
@@ -68,6 +68,12 @@ vaeskf1.vi v10, v9, 31
 # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
 # CHECK-UNKNOWN: 8a9fa577 <unknown>
 
+vaeskf1.vi v0, v9, 1
+# CHECK-INST: vaeskf1.vi v0, v9, 1
+# CHECK-ENCODING: [0x77,0xa0,0x90,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 8a90a077 <unknown>
+
 vaeskf2.vi v10, v9, 2
 # CHECK-INST: vaeskf2.vi v10, v9, 2
 # CHECK-ENCODING: [0x77,0x25,0x91,0xaa]
@@ -80,6 +86,12 @@ vaeskf2.vi v10, v9, 31
 # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
 # CHECK-UNKNOWN: aa9fa577 <unknown>
 
+vaeskf2.vi v0, v9, 2
+# CHECK-INST: vaeskf2.vi v0, v9, 2
+# CHECK-ENCODING: [0x77,0x20,0x91,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: aa912077 <unknown>
+
 vaesz.vs v10, v9
 # CHECK-INST: vaesz.vs v10, v9
 # CHECK-ENCODING: [0x77,0xa5,0x93,0xa6]