[llvm-branch-commits] [llvm] 1d9bff7 - MIPS: readsWritesFloatRegister, inc Idx for continue (#179932)

[Cullen Rhodes via llvm-branch-commits]

Author: YunQiang Su
Date: 2026-02-19T08:14:04Z
New Revision: 1d9bff7ac3c40b3e1408d3af39c243c18e252f7b

URL: https://github.com/llvm/llvm-project/commit/1d9bff7ac3c40b3e1408d3af39c243c18e252f7b
DIFF: https://github.com/llvm/llvm-project/commit/1d9bff7ac3c40b3e1408d3af39c243c18e252f7b.diff

LOG: MIPS: readsWritesFloatRegister, inc Idx for continue (#179932)

Otherwise, the input register will also be treat as write.

(cherry picked from commit c7e3bddbfd3451cf5138ec94e00eae45ab9c4b7a)

Added: 
    llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir

Modified: 
    llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index 90f2996e7f93e..36953ecd1f532 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -77,10 +77,11 @@ static std::pair<bool, bool> readsWritesFloatRegister(MachineInstr &MI,
                                                       Register Reg) {
   bool Reads = false;
   bool Writes = false;
-  unsigned Idx = 0;
+  int Idx = -1;
   Register RegF32 = getFloatRegFromFReg(Reg);
   assert(RegF32 != Mips::NoRegister && "Reg is not a Float Register");
   for (llvm::MachineOperand &MO : MI.operands()) {
+    Idx++;
     if (!MO.isReg())
       continue;
     Register MORegF32 = getFloatRegFromFReg(MO.getReg());
@@ -92,7 +93,6 @@ static std::pair<bool, bool> readsWritesFloatRegister(MachineInstr &MI,
       else
         Reads = true;
     }
-    Idx++;
   }
   return std::make_pair(Reads, Writes);
 }

diff  --git a/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir b/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir
new file mode 100644
index 0000000000000..ba98a525c24b5
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir
@@ -0,0 +1,18 @@
+# RUN: llc -mtriple=mipsisa32r6-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s
+
+name:	f
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $d12_64, $d14_64
+
+    renamable $d0_64 = CMP_LT_D renamable $d14_64, renamable $d12_64
+    ; CHECK: cmp.lt.d
+    $v1 = MFC1_D64 $d0_64
+    ; CHECK: mfc1
+    renamable $v0 = COPY renamable $d0_64
+    ; CHECK: mfc1
+    renamable $v0 = SUBu killed renamable $v1, killed renamable $v0
+    RetRA implicit $v0
+...