[llvm-branch-commits] [llvm] [AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (PR #178913)

[Jonathan Thackray via llvm-branch-commits]

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@@ -897,18 +897,27 @@ defm TLBIP : TLBITableBase;
 
 multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,
              bits<3> op2, bit needsreg = 1, bit optionalreg = 0> {
+  defvar HasE1IS = !ne(!find(name, "E1IS"), -1);
+  defvar HasE1OS = !ne(!find(name, "E1OS"), -1);
+  defvar HasE2IS = !ne(!find(name, "E2IS"), -1);
+  defvar HasE2OS = !ne(!find(name, "E2OS"), -1);
+  defvar allowTLBID = !or(!or(HasE1IS, HasE1OS), !or(HasE2IS, HasE2OS));
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jthackray wrote:

So another way might be to add a tiny TLBIPRelax SearchableTable keyed by name? Or detect the `E1IS/E1OS/E2IS/E2OS` suffixes in the C++ code instead? Or perhaps you can see another way?

https://github.com/llvm/llvm-project/pull/178913