[llvm-branch-commits] [llvm] [AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (PR #178913)

[via llvm-branch-commits]

================
@@ -897,18 +897,27 @@ defm TLBIP : TLBITableBase;
 
 multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,
              bits<3> op2, bit needsreg = 1, bit optionalreg = 0> {
+  defvar HasE1IS = !ne(!find(name, "E1IS"), -1);
+  defvar HasE1OS = !ne(!find(name, "E1OS"), -1);
+  defvar HasE2IS = !ne(!find(name, "E2IS"), -1);
+  defvar HasE2OS = !ne(!find(name, "E2OS"), -1);
+  defvar allowTLBID = !or(!or(HasE1IS, HasE1OS), !or(HasE2IS, HasE2OS));
----------------
Lukacma wrote:

I think it is better to pass this as a parameter rather than have this logic here. I also don't think we should put either D128 or TLBID as required feature but rather use that extra parameter to correctly process featurebitset we get. this should simplify logic in BaseInfo.h 

In long run if we keep encountering these kind of instructions we need to thing about how to implement OR functionality here as any of these solutions are quite hacky imo.

https://github.com/llvm/llvm-project/pull/178913