[llvm-branch-commits] [lldb] [lldb][RISCV] update RISCV target features in disassembler (PR #173047)

[David Spickett via llvm-branch-commits]

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@@ -0,0 +1,47 @@
+"""
+Tests that LLDB can correctly set up a disassembler using extensions from the .riscv.attributes section.
+"""
+
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class TestDisassembler(TestBase):
+    expected_zbb_instrs = ["andn", "orn", "xnor", "rol", "ror"]
+
+    @skipIfLLVMTargetMissing("RISCV")
+    def test_without_riscv_attributes(self):
+        """
+        Tests disassembly of a riscv binary without the .riscv.attributes.
+        Without the .riscv.attributes section lldb won't set up a disassembler to
+        handle the bitmanip extension, so it is not expected to see zbb instructions
+        in the output.
+        """
+        self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gc_zbb"})
+
+        target = self.dbg.CreateTarget(self.getBuildArtifact("stripped.out"))
+
+        self.expect("disassemble --name do_zbb_stuff")
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DavidSpickett wrote:

If all you can rely on being consistent is like, the `0x` somewhere, then don't bother.

https://github.com/llvm/llvm-project/pull/173047