[llvm-branch-commits] [llvm] [AMDGPU] Fix instruction size for 64-bit literal constant operands (PR #180387)

[Matt Arsenault via llvm-branch-commits]

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@@ -9791,7 +9791,14 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
               LiteralSize = 8;
             break;
           case AMDGPU::OPERAND_REG_IMM_INT64:
-            if (!Op.isImm() || !AMDGPU::isValid32BitLiteral(Op.getImm(), false))
+            // A 32-bit literal is only valid when the value fits in BOTH signed
+            // and unsigned 32-bit ranges [0, 2^31-1], matching the MC code
+            // emitter's getLit64Encoding logic. This is because of the lack of
+            // abilility to tell signedness of the literal, therefore we need to
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arsenm wrote:

The signedness should come from the operand type. OPERAND_REG_IMM_INT64 should be split into signed and unsigned versions 

https://github.com/llvm/llvm-project/pull/180387