[llvm-branch-commits] [RISCV][CodeGen] Lower abs to Zvabd instructions (PR #180142)

[Pengcheng Wang via llvm-branch-commits]

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/180142

For abs operation, we can synthesize it via vabd.vx with x0 register.