[llvm-branch-commits] [llvm] [AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe (PR #177334)
Jonathan Thackray via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Feb 4 06:06:44 PST 2026
https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/177334
>From de3f8153e17ae55bbaa34a78aeca8c5e964001c5 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Thu, 8 Jan 2026 16:08:36 +0000
Subject: [PATCH 1/2] [AArch64][llvm] Allow FPRCVT insns to run in streaming
mode if safe
For FEAT_FPRCVT instructions, allow them to run in streaming mode if safe
---
.../Target/AArch64/AArch64ISelLowering.cpp | 3 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 +-
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 126 +++++-------------
.../CodeGen/AArch64/arm64-cvtf-simd-itofp.ll | 30 ++---
4 files changed, 49 insertions(+), 114 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0de367e1fb990..da6f6dc6ca45f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -20561,6 +20561,9 @@ tryToReplaceScalarFPConversionWithSVE(SDNode *N, SelectionDAG &DAG,
N->getOpcode() == ISD::FP_TO_UINT_SAT)
return SDValue();
+ if (Subtarget->isStreaming() && Subtarget->hasFPRCVT())
+ return SDValue();
+
if (!Subtarget->isSVEorStreamingSVEAvailable() ||
(!Subtarget->isStreaming() && !Subtarget->isStreamingCompatible()))
return SDValue();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index ba32eac2f0d28..5e0be43ea9408 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5361,7 +5361,7 @@ defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
-let Predicates = [HasNEON, HasFPRCVT] in{
+let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in{
defm FCVTAS : FPToIntegerSIMDScalar<0b11, 0b010, "fcvtas", int_aarch64_neon_fcvtas>;
defm FCVTAU : FPToIntegerSIMDScalar<0b11, 0b011, "fcvtau", int_aarch64_neon_fcvtau>;
defm FCVTMS : FPToIntegerSIMDScalar<0b10, 0b100, "fcvtms", int_aarch64_neon_fcvtms>;
@@ -5404,7 +5404,7 @@ def : Pat<(i64 (any_llround f64:$Rn)),
defm SCVTF : IntegerToFP<0b00, 0b010, "scvtf", any_sint_to_fp>;
defm UCVTF : IntegerToFP<0b00, 0b011, "ucvtf", any_uint_to_fp>;
-let Predicates = [HasNEON, HasFPRCVT] in {
+let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in {
defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf", any_sint_to_fp>;
defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf", any_uint_to_fp>;
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
index 7dd0806758d28..7f05aefda4dc2 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
@@ -36,8 +36,7 @@ define float @test_fptosi_f16_i32_simd(half %a) {
;
; CHECK-SME-LABEL: test_fptosi_f16_i32_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.h
+; CHECK-SME-NEXT: fcvtzs s0, h0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptosi_f16_i32_simd:
@@ -66,8 +65,7 @@ define double @test_fptosi_f16_i64_simd(half %a) {
;
; CHECK-SME-LABEL: test_fptosi_f16_i64_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-SME-NEXT: fcvtzs d0, h0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptosi_f16_i64_simd:
@@ -122,8 +120,7 @@ define double @test_fptosi_f32_i64_simd(float %a) {
;
; CHECK-SME-LABEL: test_fptosi_f32_i64_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtzs d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptosi_f32_i64_simd:
@@ -151,8 +148,7 @@ define double @test_fptosi_f64_i64_simd(double %a) {
;
; CHECK-SME-LABEL: test_fptosi_f64_i64_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtzs d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptosi_f64_i64_simd:
@@ -181,8 +177,7 @@ define float @test_fptosi_f32_i32_simd(float %a) {
;
; CHECK-SME-LABEL: test_fptosi_f32_i32_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtzs s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptosi_f32_i32_simd:
@@ -211,8 +206,7 @@ define float @test_fptoui_f16_i32_simd(half %a) {
;
; CHECK-SME-LABEL: test_fptoui_f16_i32_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.h
+; CHECK-SME-NEXT: fcvtzu s0, h0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptoui_f16_i32_simd:
@@ -241,8 +235,7 @@ define double @test_fptoui_f16_i64_simd(half %a) {
;
; CHECK-SME-LABEL: test_fptoui_f16_i64_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.h
+; CHECK-SME-NEXT: fcvtzu d0, h0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptoui_f16_i64_simd:
@@ -297,8 +290,7 @@ define double @test_fptoui_f32_i64_simd(float %a) {
;
; CHECK-SME-LABEL: test_fptoui_f32_i64_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtzu d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptoui_f32_i64_simd:
@@ -326,8 +318,7 @@ define double @test_fptoui_f64_i64_simd(double %a) {
;
; CHECK-SME-LABEL: test_fptoui_f64_i64_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtzu d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptoui_f64_i64_simd:
@@ -356,8 +347,7 @@ define float @test_fptoui_f32_i32_simd(float %a) {
;
; CHECK-SME-LABEL: test_fptoui_f32_i32_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtzu s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: test_fptoui_f32_i32_simd:
@@ -706,9 +696,7 @@ define double @fcvtas_ds_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtas_ds_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frinta s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtas d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtas_ds_round_simd:
@@ -764,9 +752,7 @@ define float @fcvtas_ss_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtas_ss_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frinta s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtas s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtas_ss_round_simd:
@@ -795,9 +781,7 @@ define double @fcvtas_dd_round_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtas_dd_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frinta d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtas d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtas_dd_round_simd:
@@ -828,9 +812,7 @@ define double @fcvtau_ds_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtau_ds_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frinta s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtau d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtau_ds_round_simd:
@@ -886,9 +868,7 @@ define float @fcvtau_ss_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtau_ss_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frinta s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtas s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtau_ss_round_simd:
@@ -917,9 +897,7 @@ define double @fcvtau_dd_round_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtau_dd_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frinta d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtas d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtau_dd_round_simd:
@@ -1192,9 +1170,7 @@ define double @fcvtms_ds_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtms_ds_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintm s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtms d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtms_ds_round_simd:
@@ -1250,9 +1226,7 @@ define float @fcvtms_ss_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtms_ss_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintm s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtms s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtms_ss_round_simd:
@@ -1281,9 +1255,7 @@ define double @fcvtms_dd_round_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtms_dd_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintm d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtms d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtms_dd_round_simd:
@@ -1315,9 +1287,7 @@ define double @fcvtmu_ds_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtmu_ds_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintm s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtmu d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtmu_ds_round_simd:
@@ -1373,9 +1343,7 @@ define float @fcvtmu_ss_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtmu_ss_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintm s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtms s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtmu_ss_round_simd:
@@ -1404,9 +1372,7 @@ define double @fcvtmu_dd_round_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtmu_dd_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintm d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtms d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtmu_dd_round_simd:
@@ -1437,9 +1403,7 @@ define double @fcvtps_ds_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtps_ds_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintp s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtps d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtps_ds_round_simd:
@@ -1495,9 +1459,7 @@ define float @fcvtps_ss_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtps_ss_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintp s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtps s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtps_ss_round_simd:
@@ -1526,9 +1488,7 @@ define double @fcvtps_dd_round_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtps_dd_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintp d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtps d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtps_dd_round_simd:
@@ -1559,9 +1519,7 @@ define double @fcvtpu_ds_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtpu_ds_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintp s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtpu d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtpu_ds_round_simd:
@@ -1617,9 +1575,7 @@ define float @fcvtpu_ss_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtpu_ss_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintp s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtps s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtpu_ss_round_simd:
@@ -1648,9 +1604,7 @@ define double @fcvtpu_dd_round_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtpu_dd_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintp d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtps d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtpu_dd_round_simd:
@@ -1681,9 +1635,7 @@ define double @fcvtzs_ds_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtzs_ds_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintz s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtzs d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtzs_ds_round_simd:
@@ -1739,9 +1691,7 @@ define float @fcvtzs_ss_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtzs_ss_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintz s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtzs s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtzs_ss_round_simd:
@@ -1770,9 +1720,7 @@ define double @fcvtzs_dd_round_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtzs_dd_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintz d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtzs d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtzs_dd_round_simd:
@@ -1802,9 +1750,7 @@ define double @fcvtzu_ds_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtzu_ds_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintz s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtzu d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtzu_ds_round_simd:
@@ -1860,9 +1806,7 @@ define float @fcvtzu_ss_round_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtzu_ss_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintz s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtzs s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtzu_ss_round_simd:
@@ -1891,9 +1835,7 @@ define double @fcvtzu_dd_round_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtzu_dd_round_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintz d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtzs d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtzu_dd_round_simd:
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
index ab7d880b0d8e6..44594fad93d08 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
@@ -51,8 +51,7 @@ define half @scvtf_bitcast_f32_to_f16(float %f) nounwind {
;
; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f16:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: scvtf z0.h, p0/m, z0.s
+; CHECK-SME-NEXT: scvtf h0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f16:
@@ -75,8 +74,7 @@ define half @ucvtf_bitcast_f32_to_f16(float %f) nounwind {
;
; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f16:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: ucvtf z0.h, p0/m, z0.s
+; CHECK-SME-NEXT: ucvtf h0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f16:
@@ -99,8 +97,7 @@ define float @scvtf_bitcast_f64_to_f32(double %d) nounwind {
;
; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f32:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: scvtf z0.s, p0/m, z0.d
+; CHECK-SME-NEXT: scvtf s0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f32:
@@ -123,8 +120,7 @@ define float @ucvtf_bitcast_f64_to_f32(double %d) nounwind {
;
; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f32:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: ucvtf z0.s, p0/m, z0.d
+; CHECK-SME-NEXT: ucvtf s0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f32:
@@ -147,8 +143,7 @@ define half @scvtf_bitcast_f64_to_f16(double %d) nounwind {
;
; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f16:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: scvtf z0.h, p0/m, z0.d
+; CHECK-SME-NEXT: scvtf h0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f16:
@@ -171,8 +166,7 @@ define half @ucvtf_bitcast_f64_to_f16(double %d) nounwind {
;
; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f16:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: ucvtf z0.h, p0/m, z0.d
+; CHECK-SME-NEXT: ucvtf h0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f16:
@@ -195,8 +189,7 @@ define float @scvtf_bitcast_f32_to_f32(float %f) nounwind {
;
; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f32:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: scvtf z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: scvtf s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f32:
@@ -219,8 +212,7 @@ define float @ucvtf_bitcast_f32_to_f32(float %f) nounwind {
;
; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f32:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: ucvtf z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ucvtf s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f32:
@@ -243,8 +235,7 @@ define double @scvtf_bitcast_f64_to_f64(double %d) nounwind {
;
; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f64:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: scvtf z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: scvtf d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f64:
@@ -267,8 +258,7 @@ define double @ucvtf_bitcast_f64_to_f64(double %d) nounwind {
;
; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f64:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: ucvtf z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ucvtf d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f64:
>From 6214bd66c4aa4a22357c6f9739b081afb324a74c Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Wed, 4 Feb 2026 13:52:59 +0000
Subject: [PATCH 2/2] fixup!
Adjust code
---
.../Target/AArch64/AArch64ISelLowering.cpp | 3 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 +-
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 224 ++++--------------
.../CodeGen/AArch64/arm64-cvtf-simd-itofp.ll | 50 +---
4 files changed, 61 insertions(+), 220 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index da6f6dc6ca45f..db9aa6cff3edc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -20557,6 +20557,9 @@ tryToReplaceScalarFPConversionWithSVE(SDNode *N, SelectionDAG &DAG,
if (DCI.isBeforeLegalizeOps())
return SDValue();
+ if (Subtarget->hasFPRCVT())
+ return SDValue();
+
if (N->getOpcode() == ISD::FP_TO_SINT_SAT ||
N->getOpcode() == ISD::FP_TO_UINT_SAT)
return SDValue();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 5e0be43ea9408..1ff98053abbdc 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5361,7 +5361,7 @@ defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
-let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in{
+let Predicates = [HasFPRCVT] in{
defm FCVTAS : FPToIntegerSIMDScalar<0b11, 0b010, "fcvtas", int_aarch64_neon_fcvtas>;
defm FCVTAU : FPToIntegerSIMDScalar<0b11, 0b011, "fcvtau", int_aarch64_neon_fcvtau>;
defm FCVTMS : FPToIntegerSIMDScalar<0b10, 0b100, "fcvtms", int_aarch64_neon_fcvtms>;
@@ -5404,7 +5404,7 @@ def : Pat<(i64 (any_llround f64:$Rn)),
defm SCVTF : IntegerToFP<0b00, 0b010, "scvtf", any_sint_to_fp>;
defm UCVTF : IntegerToFP<0b00, 0b011, "ucvtf", any_uint_to_fp>;
-let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in {
+let Predicates = [HasFPRCVT] in {
defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf", any_sint_to_fp>;
defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf", any_uint_to_fp>;
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
index 7f05aefda4dc2..7b6cd56dadaaa 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
@@ -41,10 +41,7 @@ define float @test_fptosi_f16_i32_simd(half %a) {
;
; CHECK-SVE-LABEL: test_fptosi_f16_i32_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.h
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs s0, h0
; CHECK-SVE-NEXT: ret
%r = fptosi half %a to i32
%bc = bitcast i32 %r to float
@@ -70,10 +67,7 @@ define double @test_fptosi_f16_i64_simd(half %a) {
;
; CHECK-SVE-LABEL: test_fptosi_f16_i64_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.h
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs d0, h0
; CHECK-SVE-NEXT: ret
%r = fptosi half %a to i64
%bc = bitcast i64 %r to double
@@ -125,10 +119,7 @@ define double @test_fptosi_f32_i64_simd(float %a) {
;
; CHECK-SVE-LABEL: test_fptosi_f32_i64_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs d0, s0
; CHECK-SVE-NEXT: ret
%r = fptosi float %a to i64
%bc = bitcast i64 %r to double
@@ -153,10 +144,7 @@ define double @test_fptosi_f64_i64_simd(double %a) {
;
; CHECK-SVE-LABEL: test_fptosi_f64_i64_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs d0, d0
; CHECK-SVE-NEXT: ret
%r = fptosi double %a to i64
%bc = bitcast i64 %r to double
@@ -182,10 +170,7 @@ define float @test_fptosi_f32_i32_simd(float %a) {
;
; CHECK-SVE-LABEL: test_fptosi_f32_i32_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs s0, s0
; CHECK-SVE-NEXT: ret
%r = fptosi float %a to i32
%bc = bitcast i32 %r to float
@@ -211,10 +196,7 @@ define float @test_fptoui_f16_i32_simd(half %a) {
;
; CHECK-SVE-LABEL: test_fptoui_f16_i32_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0
-; CHECK-SVE-NEXT: fcvtzu z0.s, p0/m, z0.h
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtzu s0, h0
; CHECK-SVE-NEXT: ret
%r = fptoui half %a to i32
%bc = bitcast i32 %r to float
@@ -240,10 +222,7 @@ define double @test_fptoui_f16_i64_simd(half %a) {
;
; CHECK-SVE-LABEL: test_fptoui_f16_i64_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0
-; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.h
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzu d0, h0
; CHECK-SVE-NEXT: ret
%r = fptoui half %a to i64
%bc = bitcast i64 %r to double
@@ -295,10 +274,7 @@ define double @test_fptoui_f32_i64_simd(float %a) {
;
; CHECK-SVE-LABEL: test_fptoui_f32_i64_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzu d0, s0
; CHECK-SVE-NEXT: ret
%r = fptoui float %a to i64
%bc = bitcast i64 %r to double
@@ -323,10 +299,7 @@ define double @test_fptoui_f64_i64_simd(double %a) {
;
; CHECK-SVE-LABEL: test_fptoui_f64_i64_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzu d0, d0
; CHECK-SVE-NEXT: ret
%r = fptoui double %a to i64
%bc = bitcast i64 %r to double
@@ -352,10 +325,7 @@ define float @test_fptoui_f32_i32_simd(float %a) {
;
; CHECK-SVE-LABEL: test_fptoui_f32_i32_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-SVE-NEXT: fcvtzu z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtzu s0, s0
; CHECK-SVE-NEXT: ret
%r = fptoui float %a to i32
%bc = bitcast i32 %r to float
@@ -701,10 +671,7 @@ define double @fcvtas_ds_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtas_ds_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frinta s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtas d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i64
@@ -757,10 +724,7 @@ define float @fcvtas_ss_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtas_ss_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frinta s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtas s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i32
@@ -786,10 +750,7 @@ define double @fcvtas_dd_round_simd(double %a) {
;
; CHECK-SVE-LABEL: fcvtas_dd_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frinta d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtas d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i64
@@ -817,10 +778,7 @@ define double @fcvtau_ds_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtau_ds_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frinta s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtau d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptoui float %r to i64
@@ -873,10 +831,7 @@ define float @fcvtau_ss_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtau_ss_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frinta s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtas s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i32
@@ -902,10 +857,7 @@ define double @fcvtau_dd_round_simd(double %a) {
;
; CHECK-SVE-LABEL: fcvtau_dd_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frinta d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtas d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i64
@@ -927,17 +879,12 @@ define double @fcvtns_ds_roundeven_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtns_ds_roundeven_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintn s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtns d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtns_ds_roundeven_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintn s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtns d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptosi float %r to i64
@@ -985,17 +932,12 @@ define float @fcvtns_ss_roundeven_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtns_ss_roundeven_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintn s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtns s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtns_ss_roundeven_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintn s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtns s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptosi float %r to i32
@@ -1016,17 +958,12 @@ define double @fcvtns_dd_roundeven_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtns_dd_roundeven_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintn d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtns d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtns_dd_roundeven_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintn d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtns d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptosi double %r to i64
@@ -1049,17 +986,12 @@ define double @fcvtnu_ds_roundeven_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtnu_ds_roundeven_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintn s0, s0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtnu d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtnu_ds_roundeven_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintn s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtnu d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptoui float %r to i64
@@ -1107,17 +1039,12 @@ define float @fcvtnu_ss_roundeven_simd(float %a) {
;
; CHECK-SME-LABEL: fcvtnu_ss_roundeven_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintn s0, s0
-; CHECK-SME-NEXT: ptrue p0.s
-; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: fcvtnu s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtnu_ss_roundeven_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintn s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzu z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtnu s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptoui float %r to i32
@@ -1138,17 +1065,12 @@ define double @fcvtnu_dd_roundeven_simd(double %a) {
;
; CHECK-SME-LABEL: fcvtnu_dd_roundeven_simd:
; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: frintn d0, d0
-; CHECK-SME-NEXT: ptrue p0.d
-; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: fcvtnu d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fcvtnu_dd_roundeven_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintn d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtnu d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptoui double %r to i64
@@ -1175,10 +1097,7 @@ define double @fcvtms_ds_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtms_ds_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintm s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtms d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i64
@@ -1231,10 +1150,7 @@ define float @fcvtms_ss_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtms_ss_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintm s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtms s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i32
@@ -1260,10 +1176,7 @@ define double @fcvtms_dd_round_simd(double %a) {
;
; CHECK-SVE-LABEL: fcvtms_dd_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintm d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtms d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i64
@@ -1292,10 +1205,7 @@ define double @fcvtmu_ds_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtmu_ds_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintm s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtmu d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptoui float %r to i64
@@ -1348,10 +1258,7 @@ define float @fcvtmu_ss_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtmu_ss_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintm s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtms s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i32
@@ -1377,10 +1284,7 @@ define double @fcvtmu_dd_round_simd(double %a) {
;
; CHECK-SVE-LABEL: fcvtmu_dd_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintm d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtms d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i64
@@ -1408,10 +1312,7 @@ define double @fcvtps_ds_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtps_ds_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintp s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtps d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i64
@@ -1464,10 +1365,7 @@ define float @fcvtps_ss_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtps_ss_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintp s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtps s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i32
@@ -1493,10 +1391,7 @@ define double @fcvtps_dd_round_simd(double %a) {
;
; CHECK-SVE-LABEL: fcvtps_dd_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintp d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtps d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i64
@@ -1524,10 +1419,7 @@ define double @fcvtpu_ds_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtpu_ds_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintp s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtpu d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptoui float %r to i64
@@ -1580,10 +1472,7 @@ define float @fcvtpu_ss_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtpu_ss_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintp s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtps s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i32
@@ -1609,10 +1498,7 @@ define double @fcvtpu_dd_round_simd(double %a) {
;
; CHECK-SVE-LABEL: fcvtpu_dd_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintp d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtps d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i64
@@ -1640,10 +1526,7 @@ define double @fcvtzs_ds_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtzs_ds_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintz s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i64
@@ -1696,10 +1579,7 @@ define float @fcvtzs_ss_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtzs_ss_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintz s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i32
@@ -1725,10 +1605,7 @@ define double @fcvtzs_dd_round_simd(double %a) {
;
; CHECK-SVE-LABEL: fcvtzs_dd_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintz d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i64
@@ -1755,10 +1632,7 @@ define double @fcvtzu_ds_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtzu_ds_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintz s0, s0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzu d0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptoui float %r to i64
@@ -1811,10 +1685,7 @@ define float @fcvtzu_ss_round_simd(float %a) {
;
; CHECK-SVE-LABEL: fcvtzu_ss_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintz s0, s0
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs s0, s0
; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i32
@@ -1840,10 +1711,7 @@ define double @fcvtzu_dd_round_simd(double %a) {
;
; CHECK-SVE-LABEL: fcvtzu_dd_round_simd:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: frintz d0, d0
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: fcvtzs d0, d0
; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i64
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
index 44594fad93d08..1d2bf1f6b9b7f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
@@ -56,10 +56,7 @@ define half @scvtf_bitcast_f32_to_f16(float %f) nounwind {
;
; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f16:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-SVE-NEXT: scvtf z0.h, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-SVE-NEXT: scvtf h0, s0
; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = sitofp i32 %i to half
@@ -79,10 +76,7 @@ define half @ucvtf_bitcast_f32_to_f16(float %f) nounwind {
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f16:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-SVE-NEXT: ucvtf z0.h, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-SVE-NEXT: ucvtf h0, s0
; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = uitofp i32 %i to half
@@ -102,10 +96,7 @@ define float @scvtf_bitcast_f64_to_f32(double %d) nounwind {
;
; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f32:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-SVE-NEXT: scvtf z0.s, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: scvtf s0, d0
; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = sitofp i64 %i to float
@@ -125,10 +116,7 @@ define float @ucvtf_bitcast_f64_to_f32(double %d) nounwind {
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f32:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-SVE-NEXT: ucvtf z0.s, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ucvtf s0, d0
; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = uitofp i64 %i to float
@@ -148,10 +136,7 @@ define half @scvtf_bitcast_f64_to_f16(double %d) nounwind {
;
; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f16:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-SVE-NEXT: scvtf z0.h, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-SVE-NEXT: scvtf h0, d0
; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = sitofp i64 %i to half
@@ -171,10 +156,7 @@ define half @ucvtf_bitcast_f64_to_f16(double %d) nounwind {
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f16:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-SVE-NEXT: ucvtf z0.h, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-SVE-NEXT: ucvtf h0, d0
; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = uitofp i64 %i to half
@@ -194,10 +176,7 @@ define float @scvtf_bitcast_f32_to_f32(float %f) nounwind {
;
; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f32:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-SVE-NEXT: scvtf z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: scvtf s0, s0
; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = sitofp i32 %i to float
@@ -217,10 +196,7 @@ define float @ucvtf_bitcast_f32_to_f32(float %f) nounwind {
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f32:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-SVE-NEXT: ucvtf z0.s, p0/m, z0.s
-; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ucvtf s0, s0
; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = uitofp i32 %i to float
@@ -240,10 +216,7 @@ define double @scvtf_bitcast_f64_to_f64(double %d) nounwind {
;
; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f64:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-SVE-NEXT: scvtf z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: scvtf d0, d0
; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = sitofp i64 %i to double
@@ -263,10 +236,7 @@ define double @ucvtf_bitcast_f64_to_f64(double %d) nounwind {
;
; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f64:
; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: ptrue p0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-SVE-NEXT: ucvtf z0.d, p0/m, z0.d
-; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ucvtf d0, d0
; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = uitofp i64 %i to double
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