[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize (PR #179441)

[Petar Avramovic via llvm-branch-commits]

https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/179441

Used to fail EXPENSIVE_CHECKS because of type mismatch.

>From 3b6b109375f180e29f818a287de2bdf050cd40ad Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Tue, 3 Feb 2026 12:41:25 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in
 regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
---
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp   | 8 +++++---
 llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir | 8 ++++----
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 445150d9dfe5e..4f4f1cbf2b0d6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1044,9 +1044,11 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
 
     B.setInstrAndDebugLoc(MI);
     if (Ty.getSizeInBits() > 32) {
-      auto Unmerge32 = B.buildUnmerge(SgprRB_S32, Unmerge->getSourceReg());
-      for (unsigned i = 0; i < Unmerge32->getNumDefs(); ++i) {
-        auto [Dst0S32, Dst1S32] = unpackAExt(Unmerge32->getOperand(i).getReg());
+      auto UnmergeV2S16 =
+          B.buildUnmerge({SgprRB, V2S16}, Unmerge->getSourceReg());
+      for (unsigned i = 0; i < UnmergeV2S16->getNumDefs(); ++i) {
+        auto [Dst0S32, Dst1S32] =
+            unpackAExt(UnmergeV2S16->getOperand(i).getReg());
         B.buildTrunc(MI.getOperand(i * 2).getReg(), Dst0S32);
         B.buildTrunc(MI.getOperand(i * 2 + 1).getReg(), Dst1S32);
       }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
index 39eaa44bdd090..94a59eb1a92b2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbanklegalize %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbanklegalize -verify-machineinstrs %s -o - | FileCheck %s
 
 ---
 name: unmerge_sgprS16_from_V2S16
@@ -42,13 +42,13 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
-    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV]](s32)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(<2 x s16>), [[UV1:%[0-9]+]]:sgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV]](<2 x s16>)
     ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST]](s32)
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR]](s32)
-    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV1]](s32)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV1]](<2 x s16>)
     ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
     ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST1]](s32)
     ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR1]](s32)