[llvm-branch-commits] [llvm] [DAG] Change default expansion of strictfp vector operations (PR #179276)
Serge Pavlov via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Feb 2 08:31:03 PST 2026
https://github.com/spavloff created https://github.com/llvm/llvm-project/pull/179276
The previous default implementation unrolled strictfp vector operation, producing its scalar version. This behavior can result in low performance in some cases. A better behavior is to convert strictfp nodes into default-mode operations. This method has already been used to support strictfp nodes on targets with limited support of strictfp operations.
Many targets already implement lowering of strictfp and default-mode nodes identically. Small number of deviations from this rule is fixed in this change. Identical treatment of strictfp and default mode nodes is natural because both represent the same operation in the resulting code, the only difference is additional restrictions that compiler should apply when it handles strictfp nodes.
Unrolling vector operations can also violate user expectations. In strictfp mode, vector operations cannot be created by auto-vectorization because of the side effect of constrained functions, so the vector operations come from source code. A user may use vector operations to improve performance, but unrolling negates that intended performance gain.
>From 8987ab473c7a987d79137e36b0ac475a5039c2af Mon Sep 17 00:00:00 2001
From: Serge Pavlov <sepavloff at gmail.com>
Date: Mon, 2 Feb 2026 14:52:48 +0700
Subject: [PATCH] [DAG] Change default expansion of strictfp vector operations
The previous default implementation unrolled strictfp vector operation,
producing its scalar version. This behavior can result in low
performance in some cases. A better behavior is to convert strictfp
nodes into default-mode operations. This method has already been used to
support strictfp nodes on targets with limited support of strictfp
operations.
Many targets already implement lowering of strictfp and default-mode
nodes identically. Small number of deviations from this rule is fixed in
this change. Identical treatment of strictfp and default mode nodes is
natural because both represent the same operation in the resulting code,
the only difference is additional restrictions that compiler should
apply when it handles strictfp nodes.
Unrolling vector operations can also violate user expectations. In
strictfp mode, vector operations cannot be created by auto-vectorization
because of the side effect of constrained functions, so the vector
operations come from source code. A user may use vector operations to
improve performance, but unrolling negates that intended performance
gain.
---
.../SelectionDAG/LegalizeVectorOps.cpp | 23 +-
.../CodeGen/AArch64/fp-intrinsics-vector.ll | 3 +-
llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll | 124 +---
llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll | 65 +-
llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll | 8 +-
llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll | 8 +-
llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll | 119 +--
llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll | 30 +-
llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll | 430 +++--------
llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll | 142 ++--
llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll | 213 ++----
llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll | 100 +--
llvm/test/CodeGen/PowerPC/fp-strict-round.ll | 88 +--
llvm/test/CodeGen/PowerPC/fp-strict.ll | 191 +----
.../vector-constrained-fp-intrinsics.ll | 177 +----
llvm/test/CodeGen/X86/avx512fp16-frem.ll | 312 ++++----
.../X86/vector-constrained-fp-intrinsics.ll | 690 +++++-------------
17 files changed, 695 insertions(+), 2028 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 8f6eddefa57ac..16f431e0315be 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -257,12 +257,24 @@ SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDNode *Result) {
SDValue
VectorLegalizer::RecursivelyLegalizeResults(SDValue Op,
MutableArrayRef<SDValue> Results) {
- assert(Results.size() == Op->getNumValues() &&
- "Unexpected number of results");
+ // If a strictfp node was lowered to non-strictfp one, the array Results has
+ // one value more than the number of values produced by Op. The additional
+ // value is the chain produced by the original strictfp operation.
+ if (Results.size() != Op->getNumValues()) {
+ assert(Results.size() == (Op->getNumValues() + 1) &&
+ "Unexpected number of results");
+ if (Op.getResNo() >= Op->getNumValues()) {
+ assert(Op.getResNo() + 1 == Results.size());
+ SDValue Chain = Results.back();
+ assert(Chain.getValueType() == MVT::Other);
+ return Chain;
+ }
+ }
// Make sure that the generated code is itself legal.
for (unsigned i = 0, e = Results.size(); i != e; ++i) {
Results[i] = LegalizeOp(Results[i]);
- AddLegalizedOperand(Op.getValue(i), Results[i]);
+ if (i < Op->getNumValues())
+ AddLegalizedOperand(Op.getValue(i), Results[i]);
}
return Results[Op.getResNo()];
@@ -2238,7 +2250,10 @@ void VectorLegalizer::ExpandStrictFPOp(SDNode *Node,
return;
}
- UnrollStrictFPOp(Node, Results);
+ SDValue Chain = Node->getOperand(0);
+ assert(Chain.getValueType() == MVT::Other && "Wrong type of input chain");
+ Results.push_back(SDValue(DAG.mutateStrictFPToFP(Node), 0));
+ Results.push_back(Chain);
}
void VectorLegalizer::ExpandREM(SDNode *Node,
diff --git a/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll b/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
index c3da22757f1d2..50c894623fc17 100644
--- a/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
@@ -760,8 +760,7 @@ define <1 x double> @sitofp_v1f64_v1i64(<1 x i64> %x) #0 {
; CHECK-LABEL: sitofp_v1f64_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: scvtf d0, x8
+; CHECK-NEXT: scvtf d0, d0
; CHECK-NEXT: ret
%val = call <1 x double> @llvm.experimental.constrained.sitofp.v1f64.v1i64(<1 x i64> %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret <1 x double> %val
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
index c68a0e6f43578..7b17e98d9d135 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
@@ -353,24 +353,12 @@ define <3 x half> @v_constained_fadd_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; FIXME: Scalarized
define <4 x half> @v_constained_fadd_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {
-; GFX9-SDAG-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_add_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_add_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_add_f16_e32 v1, v1, v3
-; GFX9-SDAG-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v5, v0, s4
-; GFX9-SDAG-NEXT: v_perm_b32 v1, v4, v1, s4
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v2
-; GFX9-GISEL-NEXT: v_pk_add_f16 v1, v1, v3
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_add_f16 v0, v0, v2
+; GFX9-NEXT: v_pk_add_f16 v1, v1, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
; GFX8-SDAG: ; %bb.0:
@@ -394,86 +382,30 @@ define <4 x half> @v_constained_fadd_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_add_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_add_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX10-SDAG-NEXT: v_add_f16_e32 v1, v1, v3
-; GFX10-SDAG-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX10-SDAG-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-GISEL-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_pk_add_f16 v1, v1, v3
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-TRUE16-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
-; GFX11-SDAG-TRUE16: ; %bb.0:
-; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v1.h, v1.h, v3.h
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.h, v0.h, v2.h
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v1.l, v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-FAKE16-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
-; GFX11-SDAG-FAKE16: ; %bb.0:
-; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_add_f16_e32 v1, v1, v3
-; GFX11-SDAG-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_add_f16_e32 v2, v6, v5
-; GFX11-SDAG-FAKE16-NEXT: v_add_f16_e32 v3, v7, v4
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_pk_add_f16 v1, v1, v3
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_add_f16 v0, v0, v2
+; GFX10-NEXT: v_pk_add_f16 v1, v1, v3
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-SDAG-NEXT: v_add_f16_e32 v1, v1, v3
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v2, v6, v5
-; GFX12-SDAG-NEXT: v_add_f16_e32 v3, v7, v4
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-SDAG-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_add_f16 v0, v0, v2
+; GFX11-NEXT: v_pk_add_f16 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-GISEL-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_add_f16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_pk_add_f16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_add_f16 v0, v0, v2
+; GFX12-NEXT: v_pk_add_f16 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%val = call <4 x half> @llvm.experimental.constrained.fadd.v4f16(<4 x half> %x, <4 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <4 x half> %val
}
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
index f695526737311..28d9d12c78c53 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
@@ -117,19 +117,8 @@ define <4 x half> @v_constained_fma_v4f16_fpexcept_strict(<4 x half> %x, <4 x ha
; GFX9-LABEL: v_constained_fma_v4f16_fpexcept_strict:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX9-NEXT: v_fma_f16 v6, v8, v7, v6
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX9-NEXT: v_fma_f16 v7, v9, v8, v7
-; GFX9-NEXT: v_fma_f16 v1, v1, v3, v5
-; GFX9-NEXT: v_fma_f16 v0, v0, v2, v4
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v7, v0, s4
-; GFX9-NEXT: v_perm_b32 v1, v6, v1, s4
+; GFX9-NEXT: v_pk_fma_f16 v0, v0, v2, v4
+; GFX9-NEXT: v_pk_fma_f16 v1, v1, v3, v5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_constained_fma_v4f16_fpexcept_strict:
@@ -154,46 +143,16 @@ define <4 x half> @v_constained_fma_v4f16_fpexcept_strict(<4 x half> %x, <4 x ha
; GFX10-LABEL: v_constained_fma_v4f16_fpexcept_strict:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v0
-; GFX10-NEXT: v_fmac_f16_e32 v4, v0, v2
-; GFX10-NEXT: v_fmac_f16_e32 v6, v8, v7
-; GFX10-NEXT: v_fmac_f16_e32 v5, v1, v3
-; GFX10-NEXT: v_fmac_f16_e32 v9, v11, v10
-; GFX10-NEXT: v_perm_b32 v1, v6, v5, 0x5040100
-; GFX10-NEXT: v_perm_b32 v0, v9, v4, 0x5040100
+; GFX10-NEXT: v_pk_fma_f16 v0, v0, v2, v4
+; GFX10-NEXT: v_pk_fma_f16 v1, v1, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: v_constained_fma_v4f16_fpexcept_strict:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_fma_f16 v5.h, v1.h, v3.h, v5.h
-; GFX11-TRUE16-NEXT: v_fma_f16 v4.h, v0.h, v2.h, v4.h
-; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v5.l, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-LABEL: v_constained_fma_v4f16_fpexcept_strict:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v0
-; GFX11-FAKE16-NEXT: v_fmac_f16_e32 v4, v0, v2
-; GFX11-FAKE16-NEXT: v_fmac_f16_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: v_fmac_f16_e32 v5, v1, v3
-; GFX11-FAKE16-NEXT: v_fmac_f16_e32 v9, v11, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v6, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v9, v4, 0x5040100
-; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_constained_fma_v4f16_fpexcept_strict:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_fma_f16 v0, v0, v2, v4
+; GFX11-NEXT: v_pk_fma_f16 v1, v1, v3, v5
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%val = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <4 x half> %val
}
@@ -300,9 +259,9 @@ define <2 x half> @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg(<2 x half> %
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX8-NEXT: v_fma_f16 v3, -v5, -v4, v3
+; GFX8-NEXT: v_fma_f16 v3, v5, v4, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_fma_f16 v0, -v0, -v1, v2
+; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll
index 922a4dcbea351..6447ff9409a3e 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll
@@ -136,15 +136,15 @@ define <2 x float> @v_constained_fma_v2f32_fpexcept_strict_fneg_fneg(<2 x float>
; GCN-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_fma_f32 v0, -v0, -v2, v4
-; GCN-NEXT: v_fma_f32 v1, -v1, -v3, v5
+; GCN-NEXT: v_fma_f32 v0, v0, v2, v4
+; GCN-NEXT: v_fma_f32 v1, v1, v3, v5
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_fma_f32 v0, -v0, -v2, v4
-; GFX10-NEXT: v_fma_f32 v1, -v1, -v3, v5
+; GFX10-NEXT: v_fma_f32 v0, v0, v2, v4
+; GFX10-NEXT: v_fma_f32 v1, v1, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg <2 x float> %x
%neg.y = fneg <2 x float> %y
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
index 5cb293ab25806..904471775b3a3 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
@@ -136,15 +136,15 @@ define <2 x double> @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg(<2 x doubl
; GCN-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[4:5], v[8:9]
-; GCN-NEXT: v_fma_f64 v[2:3], -v[2:3], -v[6:7], v[10:11]
+; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[8:9]
+; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[4:5], v[8:9]
-; GFX10-NEXT: v_fma_f64 v[2:3], -v[2:3], -v[6:7], v[10:11]
+; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[8:9]
+; GFX10-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11]
; GFX10-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg <2 x double> %x
%neg.y = fneg <2 x double> %y
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
index bdb2128bf609b..cbd9351a505f2 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
@@ -425,24 +425,12 @@ define <3 x half> @v_constained_fmul_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; FIXME: Scalarized
define <4 x half> @v_constained_fmul_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {
-; GFX9-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
-; GFX9-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v5, v0, s4
-; GFX9-SDAG-NEXT: v_perm_b32 v1, v4, v1, s4
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
-; GFX9-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_mul_f16 v0, v0, v2
+; GFX9-NEXT: v_pk_mul_f16 v1, v1, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
; GFX8-SDAG: ; %bb.0:
@@ -466,86 +454,23 @@ define <4 x half> @v_constained_fmul_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2
-; GFX10-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
-; GFX10-SDAG-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX10-SDAG-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-TRUE16-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
-; GFX11-SDAG-TRUE16: ; %bb.0:
-; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, v1.h, v3.h
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v2.h
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-FAKE16-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
-; GFX11-SDAG-FAKE16: ; %bb.0:
-; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, v1, v3
-; GFX11-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_mul_f16_e32 v2, v6, v5
-; GFX11-SDAG-FAKE16-NEXT: v_mul_f16_e32 v3, v7, v4
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v2, v6, v5
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v3, v7, v4
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-SDAG-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_pk_mul_f16 v0, v0, v2
+; GFX10PLUS-NEXT: v_pk_mul_f16 v1, v1, v3
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_mul_f16 v0, v0, v2
+; GFX12-NEXT: v_pk_mul_f16 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX1-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
; GFX1-GISEL: ; %bb.0:
; GFX1-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll b/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
index 3e889c0a0670a..366cc749ae261 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
@@ -57,26 +57,25 @@ define <2 x half> @v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict(<2 x flo
; GFX8-LABEL: v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict:
@@ -90,9 +89,9 @@ define <2 x half> @v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict(<2 x flo
; GFX11-FAKE16-LABEL: v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%val = call <2 x half> @llvm.experimental.constrained.fptrunc.v2f16.v2f32(<2 x float> %arg, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <2 x half> %val
@@ -374,8 +373,8 @@ define void @v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict_noabi(<2 x flo
; GFX8-LABEL: v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict_noabi:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: flat_store_dword v[2:3], v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
@@ -384,10 +383,9 @@ define void @v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict_noabi(<2 x flo
; GFX9-LABEL: v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict_noabi:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-NEXT: global_store_dword v[2:3], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -395,9 +393,9 @@ define void @v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict_noabi(<2 x flo
; GFX10-LABEL: v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict_noabi:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-NEXT: global_store_dword v[2:3], v0, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -412,9 +410,9 @@ define void @v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict_noabi(<2 x flo
; GFX11-FAKE16-LABEL: v_constrained_fptrunc_v2f32_to_v2f16_fpexcept_strict_noabi:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: global_store_b32 v[2:3], v0, off
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x half> @llvm.experimental.constrained.fptrunc.v2f16.v2f32(<2 x float> %arg, metadata !"round.tonearest", metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
index 0787e0d0551fc..b036c011ed99d 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
@@ -169,20 +169,11 @@ define half @v_constained_fsub_f16_fpexcept_maytrap(half %x, half %y) #0 {
}
define <2 x half> @v_constained_fsub_v2f16_fpexcept_strict(<2 x half> %x, <2 x half> %y) #0 {
-; GFX9-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
; GFX8-SDAG: ; %bb.0:
@@ -201,67 +192,27 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_strict(<2 x half> %x, <2 x h
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX10-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX11-SDAG-TRUE16: ; %bb.0:
-; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v1.h
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX11-SDAG-FAKE16: ; %bb.0:
-; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v2, v3, v2
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v2, v3, v2
-; GFX12-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX10PLUS-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
; GFX10PLUS-SDAG: ; %bb.0:
; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -281,20 +232,11 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_strict(<2 x half> %x, <2 x h
}
define <2 x half> @v_constained_fsub_v2f16_fpexcept_ignore(<2 x half> %x, <2 x half> %y) #0 {
-; GFX9-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
; GFX8-SDAG: ; %bb.0:
@@ -313,67 +255,27 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_ignore(<2 x half> %x, <2 x h
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX10-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX11-SDAG-TRUE16: ; %bb.0:
-; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v1.h
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX11-SDAG-FAKE16: ; %bb.0:
-; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v2, v3, v2
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v2, v3, v2
-; GFX12-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX10PLUS-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
; GFX10PLUS-SDAG: ; %bb.0:
; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -393,20 +295,11 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_ignore(<2 x half> %x, <2 x h
}
define <2 x half> @v_constained_fsub_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x half> %y) #0 {
-; GFX9-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
; GFX8-SDAG: ; %bb.0:
@@ -425,67 +318,27 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX10-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX11-SDAG-TRUE16: ; %bb.0:
-; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v1.h
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX11-SDAG-FAKE16: ; %bb.0:
-; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v2, v3, v2
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v2, v3, v2
-; GFX12-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX10PLUS-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
; GFX10PLUS-SDAG: ; %bb.0:
; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -508,10 +361,7 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX9-SDAG-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v4, v0, s4
+; GFX9-SDAG-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -546,10 +396,8 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX10-SDAG-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX10-SDAG-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
; GFX10-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX10-SDAG-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
@@ -567,20 +415,15 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v2.h
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v2, v5, v4
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
@@ -612,13 +455,8 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX12-SDAG-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
; GFX12-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v2, v5, v4
-; GFX12-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
@@ -671,13 +509,8 @@ define <4 x half> @v_constained_fsub_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX9-SDAG-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v5, v0, s4
-; GFX9-SDAG-NEXT: v_perm_b32 v1, v4, v1, s4
+; GFX9-SDAG-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
+; GFX9-SDAG-NEXT: v_pk_add_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
@@ -716,12 +549,8 @@ define <4 x half> @v_constained_fsub_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX10-SDAG-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX10-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX10-SDAG-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX10-SDAG-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
+; GFX10-SDAG-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10-SDAG-NEXT: v_pk_add_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
@@ -740,25 +569,15 @@ define <4 x half> @v_constained_fsub_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.h, v1.h, v3.h
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v2.h
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
+; GFX11-SDAG-TRUE16-NEXT: v_pk_add_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v2, v6, v5
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e32 v3, v7, v4
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
+; GFX11-SDAG-FAKE16-NEXT: v_pk_add_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
@@ -794,18 +613,8 @@ define <4 x half> @v_constained_fsub_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v2, v6, v5
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v3, v7, v4
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-SDAG-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
+; GFX12-SDAG-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
+; GFX12-SDAG-NEXT: v_pk_add_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
@@ -910,13 +719,8 @@ define amdgpu_ps half @s_constained_fsub_f16_fpexcept_strict(half inreg %x, half
define amdgpu_ps <2 x half> @s_constained_fsub_v2f16_fpexcept_strict(<2 x half> inreg %x, <2 x half> inreg %y) #0 {
; GFX9-SDAG-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_lshr_b32 s0, s3, 16
-; GFX9-SDAG-NEXT: s_lshr_b32 s1, s2, 16
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, s1, v0
-; GFX9-SDAG-NEXT: v_sub_f16_e32 v1, s2, v1
-; GFX9-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-SDAG-NEXT: v_pk_add_f16 v0, s2, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
@@ -957,54 +761,19 @@ define amdgpu_ps <2 x half> @s_constained_fsub_v2f16_fpexcept_strict(<2 x half>
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8-GISEL-NEXT: ; return to shader part epilog
;
-; GFX10-SDAG-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
-; GFX10-SDAG: ; %bb.0:
-; GFX10-SDAG-NEXT: v_sub_f16_e64 v0, s2, s3
-; GFX10-SDAG-NEXT: s_lshr_b32 s0, s3, 16
-; GFX10-SDAG-NEXT: s_lshr_b32 s1, s2, 16
-; GFX10-SDAG-NEXT: v_sub_f16_e64 v1, s1, s0
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-SDAG-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX10-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
-; GFX10-GISEL: ; %bb.0:
-; GFX10-GISEL-NEXT: v_pk_add_f16 v0, s2, s3 neg_lo:[0,1] neg_hi:[0,1]
-; GFX10-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX11-SDAG-TRUE16-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
-; GFX11-SDAG-TRUE16: ; %bb.0:
-; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s0, s3, 16
-; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s1, s2, 16
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e64 v0.l, s2, s3
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e64 v0.h, s1, s0
-; GFX11-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX11-SDAG-FAKE16-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
-; GFX11-SDAG-FAKE16: ; %bb.0:
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e64 v0, s2, s3
-; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s0, s3, 16
-; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s1, s2, 16
-; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e64 v1, s1, s0
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-SDAG-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: ; return to shader part epilog
+; GFX10-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_pk_add_f16 v0, s2, s3 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: v_pk_add_f16 v0, s2, s3 neg_lo:[0,1] neg_hi:[0,1]
-; GFX11-GISEL-NEXT: ; return to shader part epilog
+; GFX11-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_pk_add_f16 v0, s2, s3 neg_lo:[0,1] neg_hi:[0,1]
+; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-SDAG-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_lshr_b32 s0, s3, 16
-; GFX12-SDAG-NEXT: s_lshr_b32 s1, s2, 16
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_3)
-; GFX12-SDAG-NEXT: s_sub_f16 s0, s1, s0
-; GFX12-SDAG-NEXT: s_sub_f16 s1, s2, s3
-; GFX12-SDAG-NEXT: s_pack_ll_b32_b16 s0, s1, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-SDAG-NEXT: v_pk_add_f16 v0, s2, s3 neg_lo:[0,1] neg_hi:[0,1]
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
@@ -1044,6 +813,5 @@ declare <4 x half> @llvm.experimental.constrained.fsub.v4f16(<4 x half>, <4 x ha
attributes #0 = { strictfp }
attributes #1 = { inaccessiblememonly nounwind willreturn }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11: {{.*}}
+; GFX11-GISEL: {{.*}}
; GFX8: {{.*}}
-; GFX9: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
index 98d0a6281054a..605f8834558a5 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
@@ -104,11 +104,11 @@ define <2 x half> @test_ldexp_v2f16_v2i32(ptr addrspace(1) %out, <2 x half> %a,
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff
-; GFX8-SDAG-NEXT: v_med3_i32 v1, v3, s4, v0
-; GFX8-SDAG-NEXT: v_med3_i32 v0, v4, s4, v0
-; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v1, v2, v1
-; GFX8-SDAG-NEXT: v_ldexp_f16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: v_med3_i32 v1, v4, s4, v0
+; GFX8-SDAG-NEXT: v_med3_i32 v0, v3, s4, v0
+; GFX8-SDAG-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_ldexp_v2f16_v2i32:
@@ -116,12 +116,11 @@ define <2 x half> @test_ldexp_v2f16_v2i32(ptr addrspace(1) %out, <2 x half> %a,
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff
-; GFX9-SDAG-NEXT: v_med3_i32 v1, v3, s4, v0
-; GFX9-SDAG-NEXT: v_med3_i32 v0, v4, s4, v0
-; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v1, v2, v1
-; GFX9-SDAG-NEXT: v_ldexp_f16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX9-SDAG-NEXT: v_med3_i32 v1, v4, s4, v0
+; GFX9-SDAG-NEXT: v_med3_i32 v0, v3, s4, v0
+; GFX9-SDAG-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_ldexp_v2f16_v2i32:
@@ -140,14 +139,14 @@ define <2 x half> @test_ldexp_v2f16_v2i32(ptr addrspace(1) %out, <2 x half> %a,
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v3, s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v1, v4, s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v1, v3, v1
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v4, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v3, v3, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v1, v2, v3
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: test_ldexp_v2f16_v2i32:
@@ -211,12 +210,12 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a,
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, 0x7fff
-; GFX8-SDAG-NEXT: v_med3_i32 v0, v4, s4, v1
-; GFX8-SDAG-NEXT: v_med3_i32 v4, v5, s4, v1
-; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX8-SDAG-NEXT: v_ldexp_f16_sdwa v2, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_med3_i32 v0, v5, s4, v1
+; GFX8-SDAG-NEXT: v_med3_i32 v4, v4, s4, v1
+; GFX8-SDAG-NEXT: v_ldexp_f16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v2, v2, v4
; GFX8-SDAG-NEXT: v_med3_i32 v1, v6, s4, v1
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v1, v3, v1
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -225,13 +224,12 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a,
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x7fff
-; GFX9-SDAG-NEXT: v_med3_i32 v0, v4, s4, v1
-; GFX9-SDAG-NEXT: v_med3_i32 v4, v5, s4, v1
-; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX9-SDAG-NEXT: v_ldexp_f16_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-SDAG-NEXT: s_mov_b32 s5, 0x5040100
+; GFX9-SDAG-NEXT: v_med3_i32 v0, v5, s4, v1
+; GFX9-SDAG-NEXT: v_med3_i32 v4, v4, s4, v1
+; GFX9-SDAG-NEXT: v_ldexp_f16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v2, v2, v4
; GFX9-SDAG-NEXT: v_med3_i32 v1, v6, s4, v1
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v2, v0, s5
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v2, v0
; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v1, v3, v1
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -253,16 +251,15 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a,
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v4, s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v1, v5, s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v5, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v4, v4, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v1, v2, v4
; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v2, v6, s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v1, v3, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -335,16 +332,16 @@ define <4 x half> @test_ldexp_v4f16_v4i32(ptr addrspace(1) %out, <4 x half> %a,
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff
-; GFX8-SDAG-NEXT: v_med3_i32 v1, v7, s4, v0
-; GFX8-SDAG-NEXT: v_med3_i32 v6, v6, s4, v0
-; GFX8-SDAG-NEXT: v_med3_i32 v5, v5, s4, v0
-; GFX8-SDAG-NEXT: v_med3_i32 v0, v4, s4, v0
-; GFX8-SDAG-NEXT: v_ldexp_f16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v3, v3, v6
-; GFX8-SDAG-NEXT: v_ldexp_f16_sdwa v5, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v5
-; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX8-SDAG-NEXT: v_med3_i32 v1, v6, s4, v0
+; GFX8-SDAG-NEXT: v_med3_i32 v6, v7, s4, v0
+; GFX8-SDAG-NEXT: v_med3_i32 v4, v4, s4, v0
+; GFX8-SDAG-NEXT: v_med3_i32 v0, v5, s4, v0
+; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v1, v3, v1
+; GFX8-SDAG-NEXT: v_ldexp_f16_sdwa v3, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v4, v2, v4
+; GFX8-SDAG-NEXT: v_ldexp_f16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_ldexp_v4f16_v4i32:
@@ -352,17 +349,16 @@ define <4 x half> @test_ldexp_v4f16_v4i32(ptr addrspace(1) %out, <4 x half> %a,
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff
-; GFX9-SDAG-NEXT: v_med3_i32 v1, v6, s4, v0
-; GFX9-SDAG-NEXT: v_med3_i32 v6, v7, s4, v0
-; GFX9-SDAG-NEXT: v_med3_i32 v4, v4, s4, v0
-; GFX9-SDAG-NEXT: v_med3_i32 v0, v5, s4, v0
-; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v1, v3, v1
-; GFX9-SDAG-NEXT: v_ldexp_f16_sdwa v3, v3, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v4, v2, v4
-; GFX9-SDAG-NEXT: v_ldexp_f16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-SDAG-NEXT: v_perm_b32 v1, v3, v1, s4
+; GFX9-SDAG-NEXT: v_med3_i32 v1, v7, s4, v0
+; GFX9-SDAG-NEXT: v_med3_i32 v6, v6, s4, v0
+; GFX9-SDAG-NEXT: v_med3_i32 v5, v5, s4, v0
+; GFX9-SDAG-NEXT: v_med3_i32 v0, v4, s4, v0
+; GFX9-SDAG-NEXT: v_ldexp_f16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v3, v3, v6
+; GFX9-SDAG-NEXT: v_ldexp_f16_sdwa v5, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v0, v5
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v1, v3, v1
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_ldexp_v4f16_v4i32:
@@ -386,21 +382,21 @@ define <4 x half> @test_ldexp_v4f16_v4i32(ptr addrspace(1) %out, <4 x half> %a,
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v6, s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v1, v7, s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v4, v4, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v7, s0, 0x7fff
; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v5, v5, s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v3, v3, v0
-; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v4
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v4, v4, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v6, v6, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v1, v1, v0
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v2, v6, v5
-; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v1, v7, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, v1, v3, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v7, v5
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v2, v2, v4
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v3, v3, v6
+; GFX11-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v3, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: test_ldexp_v4f16_v4i32:
diff --git a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
index 456f0bd2434fb..56474ede32d47 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
@@ -48,26 +48,26 @@ define float @test_ldexp_f32_i32(ptr addrspace(1) %out, float %a, i32 %b) #0 {
; }
define <2 x float> @test_ldexp_v2f32_v2i32(ptr addrspace(1) %out, <2 x float> %a, <2 x i32> %b) #0 {
-; GFX6-SDAG-LABEL: test_ldexp_v2f32_v2i32:
-; GFX6-SDAG: ; %bb.0:
-; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-SDAG-NEXT: v_ldexp_f32_e32 v1, v3, v5
-; GFX6-SDAG-NEXT: v_ldexp_f32_e32 v0, v2, v4
-; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX6-LABEL: test_ldexp_v2f32_v2i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v4
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v3, v5
+; GFX6-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_ldexp_v2f32_v2i32:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_ldexp_f32 v1, v3, v5
-; GFX8-SDAG-NEXT: v_ldexp_f32 v0, v2, v4
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_ldexp_v2f32_v2i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_ldexp_f32 v0, v2, v4
+; GFX8-NEXT: v_ldexp_f32 v1, v3, v5
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_ldexp_v2f32_v2i32:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_ldexp_f32 v1, v3, v5
-; GFX9-SDAG-NEXT: v_ldexp_f32 v0, v2, v4
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_ldexp_v2f32_v2i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_ldexp_f32 v0, v2, v4
+; GFX9-NEXT: v_ldexp_f32 v1, v3, v5
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_ldexp_v2f32_v2i32:
; GFX11: ; %bb.0:
@@ -75,58 +75,34 @@ define <2 x float> @test_ldexp_v2f32_v2i32(ptr addrspace(1) %out, <2 x float> %a
; GFX11-NEXT: v_ldexp_f32 v0, v2, v4
; GFX11-NEXT: v_ldexp_f32 v1, v3, v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-GISEL-LABEL: test_ldexp_v2f32_v2i32:
-; GFX6-GISEL: ; %bb.0:
-; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-GISEL-NEXT: v_ldexp_f32_e32 v0, v2, v4
-; GFX6-GISEL-NEXT: v_ldexp_f32_e32 v1, v3, v5
-; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_ldexp_v2f32_v2i32:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_ldexp_f32 v0, v2, v4
-; GFX8-GISEL-NEXT: v_ldexp_f32 v1, v3, v5
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_ldexp_v2f32_v2i32:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v2, v4
-; GFX9-GISEL-NEXT: v_ldexp_f32 v1, v3, v5
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x float> @llvm.experimental.constrained.ldexp.v2f32.v2i32(<2 x float> %a, <2 x i32> %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret <2 x float> %result
}
define <3 x float> @test_ldexp_v3f32_v3i32(ptr addrspace(1) %out, <3 x float> %a, <3 x i32> %b) #0 {
-; GFX6-SDAG-LABEL: test_ldexp_v3f32_v3i32:
-; GFX6-SDAG: ; %bb.0:
-; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-SDAG-NEXT: v_ldexp_f32_e32 v4, v4, v7
-; GFX6-SDAG-NEXT: v_ldexp_f32_e32 v1, v3, v6
-; GFX6-SDAG-NEXT: v_ldexp_f32_e32 v0, v2, v5
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v2, v4
-; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX6-LABEL: test_ldexp_v3f32_v3i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v5
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v3, v6
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v4, v7
+; GFX6-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_ldexp_v3f32_v3i32:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_ldexp_f32 v4, v4, v7
-; GFX8-SDAG-NEXT: v_ldexp_f32 v1, v3, v6
-; GFX8-SDAG-NEXT: v_ldexp_f32 v0, v2, v5
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v2, v4
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_ldexp_v3f32_v3i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_ldexp_f32 v0, v2, v5
+; GFX8-NEXT: v_ldexp_f32 v1, v3, v6
+; GFX8-NEXT: v_ldexp_f32 v2, v4, v7
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_ldexp_v3f32_v3i32:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_ldexp_f32 v4, v4, v7
-; GFX9-SDAG-NEXT: v_ldexp_f32 v1, v3, v6
-; GFX9-SDAG-NEXT: v_ldexp_f32 v0, v2, v5
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, v4
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_ldexp_v3f32_v3i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_ldexp_f32 v0, v2, v5
+; GFX9-NEXT: v_ldexp_f32 v1, v3, v6
+; GFX9-NEXT: v_ldexp_f32 v2, v4, v7
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_ldexp_v3f32_v3i32:
; GFX11: ; %bb.0:
@@ -135,67 +111,37 @@ define <3 x float> @test_ldexp_v3f32_v3i32(ptr addrspace(1) %out, <3 x float> %a
; GFX11-NEXT: v_ldexp_f32 v1, v3, v6
; GFX11-NEXT: v_ldexp_f32 v2, v4, v7
; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-GISEL-LABEL: test_ldexp_v3f32_v3i32:
-; GFX6-GISEL: ; %bb.0:
-; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-GISEL-NEXT: v_ldexp_f32_e32 v0, v2, v5
-; GFX6-GISEL-NEXT: v_ldexp_f32_e32 v1, v3, v6
-; GFX6-GISEL-NEXT: v_ldexp_f32_e32 v2, v4, v7
-; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_ldexp_v3f32_v3i32:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_ldexp_f32 v0, v2, v5
-; GFX8-GISEL-NEXT: v_ldexp_f32 v1, v3, v6
-; GFX8-GISEL-NEXT: v_ldexp_f32 v2, v4, v7
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_ldexp_v3f32_v3i32:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v2, v5
-; GFX9-GISEL-NEXT: v_ldexp_f32 v1, v3, v6
-; GFX9-GISEL-NEXT: v_ldexp_f32 v2, v4, v7
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x float> @llvm.experimental.constrained.ldexp.v3f32.v3i32(<3 x float> %a, <3 x i32> %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret <3 x float> %result
}
define <4 x float> @test_ldexp_v4f32_v4i32(ptr addrspace(1) %out, <4 x float> %a, <4 x i32> %b) #0 {
-; GFX6-SDAG-LABEL: test_ldexp_v4f32_v4i32:
-; GFX6-SDAG: ; %bb.0:
-; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-SDAG-NEXT: v_ldexp_f32_e32 v5, v5, v9
-; GFX6-SDAG-NEXT: v_ldexp_f32_e32 v4, v4, v8
-; GFX6-SDAG-NEXT: v_ldexp_f32_e32 v1, v3, v7
-; GFX6-SDAG-NEXT: v_ldexp_f32_e32 v0, v2, v6
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v2, v4
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v3, v5
-; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX6-LABEL: test_ldexp_v4f32_v4i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v6
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v3, v7
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v4, v8
+; GFX6-NEXT: v_ldexp_f32_e32 v3, v5, v9
+; GFX6-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_ldexp_v4f32_v4i32:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_ldexp_f32 v5, v5, v9
-; GFX8-SDAG-NEXT: v_ldexp_f32 v4, v4, v8
-; GFX8-SDAG-NEXT: v_ldexp_f32 v1, v3, v7
-; GFX8-SDAG-NEXT: v_ldexp_f32 v0, v2, v6
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v2, v4
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v3, v5
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_ldexp_v4f32_v4i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_ldexp_f32 v0, v2, v6
+; GFX8-NEXT: v_ldexp_f32 v1, v3, v7
+; GFX8-NEXT: v_ldexp_f32 v2, v4, v8
+; GFX8-NEXT: v_ldexp_f32 v3, v5, v9
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_ldexp_v4f32_v4i32:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_ldexp_f32 v5, v5, v9
-; GFX9-SDAG-NEXT: v_ldexp_f32 v4, v4, v8
-; GFX9-SDAG-NEXT: v_ldexp_f32 v1, v3, v7
-; GFX9-SDAG-NEXT: v_ldexp_f32 v0, v2, v6
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, v4
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, v5
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_ldexp_v4f32_v4i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_ldexp_f32 v0, v2, v6
+; GFX9-NEXT: v_ldexp_f32 v1, v3, v7
+; GFX9-NEXT: v_ldexp_f32 v2, v4, v8
+; GFX9-NEXT: v_ldexp_f32 v3, v5, v9
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_ldexp_v4f32_v4i32:
; GFX11: ; %bb.0:
@@ -205,33 +151,6 @@ define <4 x float> @test_ldexp_v4f32_v4i32(ptr addrspace(1) %out, <4 x float> %a
; GFX11-NEXT: v_ldexp_f32 v2, v4, v8
; GFX11-NEXT: v_ldexp_f32 v3, v5, v9
; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-GISEL-LABEL: test_ldexp_v4f32_v4i32:
-; GFX6-GISEL: ; %bb.0:
-; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-GISEL-NEXT: v_ldexp_f32_e32 v0, v2, v6
-; GFX6-GISEL-NEXT: v_ldexp_f32_e32 v1, v3, v7
-; GFX6-GISEL-NEXT: v_ldexp_f32_e32 v2, v4, v8
-; GFX6-GISEL-NEXT: v_ldexp_f32_e32 v3, v5, v9
-; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_ldexp_v4f32_v4i32:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_ldexp_f32 v0, v2, v6
-; GFX8-GISEL-NEXT: v_ldexp_f32 v1, v3, v7
-; GFX8-GISEL-NEXT: v_ldexp_f32 v2, v4, v8
-; GFX8-GISEL-NEXT: v_ldexp_f32 v3, v5, v9
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_ldexp_v4f32_v4i32:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v2, v6
-; GFX9-GISEL-NEXT: v_ldexp_f32 v1, v3, v7
-; GFX9-GISEL-NEXT: v_ldexp_f32 v2, v4, v8
-; GFX9-GISEL-NEXT: v_ldexp_f32 v3, v5, v9
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x float> @llvm.experimental.constrained.ldexp.v4f32.v4i32(<4 x float> %a, <4 x i32> %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret <4 x float> %result
}
@@ -249,3 +168,9 @@ attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessib
; GCN: {{.*}}
; GFX11-GISEL: {{.*}}
; GFX11-SDAG: {{.*}}
+; GFX6-GISEL: {{.*}}
+; GFX6-SDAG: {{.*}}
+; GFX8-GISEL: {{.*}}
+; GFX8-SDAG: {{.*}}
+; GFX9-GISEL: {{.*}}
+; GFX9-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll b/llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
index d4b94b97acad8..450720bb5df6c 100644
--- a/llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
+++ b/llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
@@ -4,11 +4,7 @@
define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) #0 {
; CHECK-LABEL: add_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.f32 s11, s3, s7
-; CHECK-NEXT: vadd.f32 s10, s2, s6
-; CHECK-NEXT: vadd.f32 s9, s1, s5
-; CHECK-NEXT: vadd.f32 s8, s0, s4
-; CHECK-NEXT: vorr q0, q2, q2
+; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: bx lr
%val = call <4 x float> @llvm.experimental.constrained.fadd.v4f32(<4 x float> %x, <4 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret <4 x float> %val
@@ -17,11 +13,7 @@ define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) #0 {
define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) #0 {
; CHECK-LABEL: sub_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vsub.f32 s11, s3, s7
-; CHECK-NEXT: vsub.f32 s10, s2, s6
-; CHECK-NEXT: vsub.f32 s9, s1, s5
-; CHECK-NEXT: vsub.f32 s8, s0, s4
-; CHECK-NEXT: vorr q0, q2, q2
+; CHECK-NEXT: vsub.f32 q0, q0, q1
; CHECK-NEXT: bx lr
%val = call <4 x float> @llvm.experimental.constrained.fsub.v4f32(<4 x float> %x, <4 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret <4 x float> %val
@@ -30,11 +22,7 @@ define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) #0 {
define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) #0 {
; CHECK-LABEL: mul_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmul.f32 s11, s3, s7
-; CHECK-NEXT: vmul.f32 s10, s2, s6
-; CHECK-NEXT: vmul.f32 s9, s1, s5
-; CHECK-NEXT: vmul.f32 s8, s0, s4
-; CHECK-NEXT: vorr q0, q2, q2
+; CHECK-NEXT: vmul.f32 q0, q0, q1
; CHECK-NEXT: bx lr
%val = call <4 x float> @llvm.experimental.constrained.fmul.v4f32(<4 x float> %x, <4 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret <4 x float> %val
@@ -56,10 +44,7 @@ define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) #0 {
define <4 x float> @fma_v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z) #0 {
; CHECK-LABEL: fma_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vfma.f32 s11, s3, s7
-; CHECK-NEXT: vfma.f32 s10, s2, s6
-; CHECK-NEXT: vfma.f32 s9, s1, s5
-; CHECK-NEXT: vfma.f32 s8, s0, s4
+; CHECK-NEXT: vfma.f32 q2, q0, q1
; CHECK-NEXT: vorr q0, q2, q2
; CHECK-NEXT: bx lr
%val = call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
@@ -69,19 +54,7 @@ define <4 x float> @fma_v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z) #0
define <4 x i32> @fptosi_v4i32_v4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fptosi_v4i32_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vcvt.s32.f32 s4, s2
-; CHECK-NEXT: vcvt.s32.f32 s6, s0
-; CHECK-NEXT: vcvt.s32.f32 s0, s1
-; CHECK-NEXT: vmov r0, s4
-; CHECK-NEXT: vcvt.s32.f32 s4, s3
-; CHECK-NEXT: vmov.32 d17[0], r0
-; CHECK-NEXT: vmov r0, s6
-; CHECK-NEXT: vmov.32 d16[0], r0
-; CHECK-NEXT: vmov r0, s4
-; CHECK-NEXT: vmov.32 d17[1], r0
-; CHECK-NEXT: vmov r0, s0
-; CHECK-NEXT: vmov.32 d16[1], r0
-; CHECK-NEXT: vorr q0, q8, q8
+; CHECK-NEXT: vcvt.s32.f32 q0, q0
; CHECK-NEXT: bx lr
%val = call <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f32(<4 x float> %x, metadata !"fpexcept.strict") #0
ret <4 x i32> %val
@@ -187,43 +160,8 @@ define <4 x i64> @fptoui_v4i64_v4f32(<4 x float> %x) #0 {
define <4 x float> @sitofp_v4f32_v4i32(<4 x i32> %x) #0 {
; CHECK-LABEL: sitofp_v4f32_v4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #32
-; CHECK-NEXT: sub sp, sp, #32
-; CHECK-NEXT: vmov r12, r1, d0
-; CHECK-NEXT: movw r0, #0
-; CHECK-NEXT: vmov r2, r3, d1
-; CHECK-NEXT: movt r0, #17200
-; CHECK-NEXT: str r0, [sp, #20]
-; CHECK-NEXT: vldr d16, .LCPI9_0
-; CHECK-NEXT: eor r1, r1, #-2147483648
-; CHECK-NEXT: str r1, [sp, #16]
-; CHECK-NEXT: str r0, [sp, #12]
-; CHECK-NEXT: eor r1, r2, #-2147483648
-; CHECK-NEXT: vldr d17, [sp, #16]
-; CHECK-NEXT: stmib sp, {r0, r1}
-; CHECK-NEXT: eor r1, r3, #-2147483648
-; CHECK-NEXT: vsub.f64 d17, d17, d16
-; CHECK-NEXT: vldr d18, [sp, #8]
-; CHECK-NEXT: str r1, [sp]
-; CHECK-NEXT: str r0, [sp, #28]
-; CHECK-NEXT: eor r0, r12, #-2147483648
-; CHECK-NEXT: vldr d19, [sp]
-; CHECK-NEXT: str r0, [sp, #24]
-; CHECK-NEXT: vsub.f64 d18, d18, d16
-; CHECK-NEXT: vsub.f64 d19, d19, d16
-; CHECK-NEXT: vldr d20, [sp, #24]
-; CHECK-NEXT: vcvt.f32.f64 s3, d19
-; CHECK-NEXT: vsub.f64 d16, d20, d16
-; CHECK-NEXT: vcvt.f32.f64 s2, d18
-; CHECK-NEXT: vcvt.f32.f64 s1, d17
-; CHECK-NEXT: vcvt.f32.f64 s0, d16
-; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: vcvt.f32.s32 q0, q0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 3
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI9_0:
-; CHECK-NEXT: .long 2147483648 @ double 4503601774854144
-; CHECK-NEXT: .long 1127219200
%val = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i32(<4 x i32> %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret <4 x float> %val
}
@@ -812,30 +750,10 @@ define <2 x i64> @fptoui_v2i64_v2f64(<2 x double> %x) #0 {
define <2 x double> @sitofp_v2f64_v2i32(<2 x i32> %x) #0 {
; CHECK-LABEL: sitofp_v2f64_v2i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, sp, #16
-; CHECK-NEXT: vmov.32 r0, d0[1]
-; CHECK-NEXT: movw r2, #0
-; CHECK-NEXT: vmov.32 r1, d0[0]
-; CHECK-NEXT: movt r2, #17200
-; CHECK-NEXT: str r2, [sp, #4]
-; CHECK-NEXT: vldr d16, .LCPI34_0
-; CHECK-NEXT: eor r0, r0, #-2147483648
-; CHECK-NEXT: str r0, [sp]
-; CHECK-NEXT: str r2, [sp, #12]
-; CHECK-NEXT: eor r0, r1, #-2147483648
-; CHECK-NEXT: vldr d17, [sp]
-; CHECK-NEXT: str r0, [sp, #8]
-; CHECK-NEXT: vldr d18, [sp, #8]
-; CHECK-NEXT: vsub.f64 d1, d17, d16
-; CHECK-NEXT: vsub.f64 d0, d18, d16
-; CHECK-NEXT: add sp, sp, #16
+; CHECK-NEXT: vcvt.f64.s32 d17, s1
+; CHECK-NEXT: vcvt.f64.s32 d16, s0
+; CHECK-NEXT: vorr q0, q8, q8
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 3
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI34_0:
-; CHECK-NEXT: .long 2147483648 @ double 4503601774854144
-; CHECK-NEXT: .long 1127219200
%val = call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i32(<2 x i32> %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret <2 x double> %val
}
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-round.ll b/llvm/test/CodeGen/PowerPC/fp-strict-round.ll
index eac4fb6f98bf7..a073b1d22eb60 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-round.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-round.ll
@@ -205,96 +205,12 @@ define double @nearbyint_f64(double %f1, double %f2) strictfp {
define <4 x float> @nearbyint_v4f32(<4 x float> %vf1, <4 x float> %vf2) strictfp {
; P8-LABEL: nearbyint_v4f32:
; P8: # %bb.0:
-; P8-NEXT: mflr r0
-; P8-NEXT: stdu r1, -176(r1)
-; P8-NEXT: std r0, 192(r1)
-; P8-NEXT: .cfi_def_cfa_offset 176
-; P8-NEXT: .cfi_offset lr, 16
-; P8-NEXT: .cfi_offset v29, -48
-; P8-NEXT: .cfi_offset v30, -32
-; P8-NEXT: .cfi_offset v31, -16
-; P8-NEXT: xxsldwi vs0, v2, v2, 3
-; P8-NEXT: li r3, 128
-; P8-NEXT: xscvspdpn f1, vs0
-; P8-NEXT: stxvd2x v29, r1, r3 # 16-byte Folded Spill
-; P8-NEXT: li r3, 144
-; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill
-; P8-NEXT: li r3, 160
-; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill
-; P8-NEXT: vmr v31, v2
-; P8-NEXT: bl nearbyintf
-; P8-NEXT: nop
-; P8-NEXT: xxsldwi vs0, v31, v31, 1
-; P8-NEXT: xxlor v30, f1, f1
-; P8-NEXT: xscvspdpn f1, vs0
-; P8-NEXT: bl nearbyintf
-; P8-NEXT: nop
-; P8-NEXT: xxmrghd vs0, vs1, v30
-; P8-NEXT: xscvspdpn f1, v31
-; P8-NEXT: xvcvdpsp v29, vs0
-; P8-NEXT: bl nearbyintf
-; P8-NEXT: nop
-; P8-NEXT: xxswapd vs0, v31
-; P8-NEXT: xxlor v30, f1, f1
-; P8-NEXT: xscvspdpn f1, vs0
-; P8-NEXT: bl nearbyintf
-; P8-NEXT: nop
-; P8-NEXT: xxmrghd vs0, v30, vs1
-; P8-NEXT: li r3, 160
-; P8-NEXT: xvcvdpsp v2, vs0
-; P8-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload
-; P8-NEXT: li r3, 144
-; P8-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload
-; P8-NEXT: li r3, 128
-; P8-NEXT: vmrgew v2, v2, v29
-; P8-NEXT: lxvd2x v29, r1, r3 # 16-byte Folded Reload
-; P8-NEXT: addi r1, r1, 176
-; P8-NEXT: ld r0, 16(r1)
-; P8-NEXT: mtlr r0
+; P8-NEXT: vrfin v2, v2
; P8-NEXT: blr
;
; P9-LABEL: nearbyint_v4f32:
; P9: # %bb.0:
-; P9-NEXT: mflr r0
-; P9-NEXT: stdu r1, -80(r1)
-; P9-NEXT: std r0, 96(r1)
-; P9-NEXT: .cfi_def_cfa_offset 80
-; P9-NEXT: .cfi_offset lr, 16
-; P9-NEXT: .cfi_offset v29, -48
-; P9-NEXT: .cfi_offset v30, -32
-; P9-NEXT: .cfi_offset v31, -16
-; P9-NEXT: xxsldwi vs0, v2, v2, 3
-; P9-NEXT: stxv v29, 32(r1) # 16-byte Folded Spill
-; P9-NEXT: xscvspdpn f1, vs0
-; P9-NEXT: stxv v30, 48(r1) # 16-byte Folded Spill
-; P9-NEXT: stxv v31, 64(r1) # 16-byte Folded Spill
-; P9-NEXT: vmr v31, v2
-; P9-NEXT: bl nearbyintf
-; P9-NEXT: nop
-; P9-NEXT: xxsldwi vs0, v31, v31, 1
-; P9-NEXT: xscpsgndp v30, f1, f1
-; P9-NEXT: xscvspdpn f1, vs0
-; P9-NEXT: bl nearbyintf
-; P9-NEXT: nop
-; P9-NEXT: xxmrghd vs0, vs1, v30
-; P9-NEXT: xscvspdpn f1, v31
-; P9-NEXT: xvcvdpsp v29, vs0
-; P9-NEXT: bl nearbyintf
-; P9-NEXT: nop
-; P9-NEXT: xxswapd vs0, v31
-; P9-NEXT: xscpsgndp v30, f1, f1
-; P9-NEXT: xscvspdpn f1, vs0
-; P9-NEXT: bl nearbyintf
-; P9-NEXT: nop
-; P9-NEXT: xxmrghd vs0, v30, vs1
-; P9-NEXT: lxv v31, 64(r1) # 16-byte Folded Reload
-; P9-NEXT: lxv v30, 48(r1) # 16-byte Folded Reload
-; P9-NEXT: xvcvdpsp v2, vs0
-; P9-NEXT: vmrgew v2, v2, v29
-; P9-NEXT: lxv v29, 32(r1) # 16-byte Folded Reload
-; P9-NEXT: addi r1, r1, 80
-; P9-NEXT: ld r0, 16(r1)
-; P9-NEXT: mtlr r0
+; P9-NEXT: vrfin v2, v2
; P9-NEXT: blr
%res = call <4 x float> @llvm.experimental.constrained.nearbyint.v4f32(
<4 x float> %vf1,
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict.ll b/llvm/test/CodeGen/PowerPC/fp-strict.ll
index d3025f1da658a..ac2fed7cf7961 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict.ll
@@ -89,28 +89,7 @@ define <4 x float> @fadd_v4f32(<4 x float> %vf1, <4 x float> %vf2) #0 {
;
; NOVSX-LABEL: fadd_v4f32:
; NOVSX: # %bb.0:
-; NOVSX-NEXT: addi r3, r1, -32
-; NOVSX-NEXT: stvx v3, 0, r3
-; NOVSX-NEXT: addi r3, r1, -48
-; NOVSX-NEXT: stvx v2, 0, r3
-; NOVSX-NEXT: addi r3, r1, -16
-; NOVSX-NEXT: lfs f0, -20(r1)
-; NOVSX-NEXT: lfs f1, -36(r1)
-; NOVSX-NEXT: fadds f0, f1, f0
-; NOVSX-NEXT: lfs f1, -40(r1)
-; NOVSX-NEXT: stfs f0, -4(r1)
-; NOVSX-NEXT: lfs f0, -24(r1)
-; NOVSX-NEXT: fadds f0, f1, f0
-; NOVSX-NEXT: lfs f1, -44(r1)
-; NOVSX-NEXT: stfs f0, -8(r1)
-; NOVSX-NEXT: lfs f0, -28(r1)
-; NOVSX-NEXT: fadds f0, f1, f0
-; NOVSX-NEXT: lfs f1, -48(r1)
-; NOVSX-NEXT: stfs f0, -12(r1)
-; NOVSX-NEXT: lfs f0, -32(r1)
-; NOVSX-NEXT: fadds f0, f1, f0
-; NOVSX-NEXT: stfs f0, -16(r1)
-; NOVSX-NEXT: lvx v2, 0, r3
+; NOVSX-NEXT: vaddfp v2, v2, v3
; NOVSX-NEXT: blr
;
; SPE-LABEL: fadd_v4f32:
@@ -215,28 +194,7 @@ define <4 x float> @fsub_v4f32(<4 x float> %vf1, <4 x float> %vf2) #0 {
;
; NOVSX-LABEL: fsub_v4f32:
; NOVSX: # %bb.0:
-; NOVSX-NEXT: addi r3, r1, -32
-; NOVSX-NEXT: stvx v3, 0, r3
-; NOVSX-NEXT: addi r3, r1, -48
-; NOVSX-NEXT: stvx v2, 0, r3
-; NOVSX-NEXT: addi r3, r1, -16
-; NOVSX-NEXT: lfs f0, -20(r1)
-; NOVSX-NEXT: lfs f1, -36(r1)
-; NOVSX-NEXT: fsubs f0, f1, f0
-; NOVSX-NEXT: lfs f1, -40(r1)
-; NOVSX-NEXT: stfs f0, -4(r1)
-; NOVSX-NEXT: lfs f0, -24(r1)
-; NOVSX-NEXT: fsubs f0, f1, f0
-; NOVSX-NEXT: lfs f1, -44(r1)
-; NOVSX-NEXT: stfs f0, -8(r1)
-; NOVSX-NEXT: lfs f0, -28(r1)
-; NOVSX-NEXT: fsubs f0, f1, f0
-; NOVSX-NEXT: lfs f1, -48(r1)
-; NOVSX-NEXT: stfs f0, -12(r1)
-; NOVSX-NEXT: lfs f0, -32(r1)
-; NOVSX-NEXT: fsubs f0, f1, f0
-; NOVSX-NEXT: stfs f0, -16(r1)
-; NOVSX-NEXT: lvx v2, 0, r3
+; NOVSX-NEXT: vsubfp v2, v2, v3
; NOVSX-NEXT: blr
;
; SPE-LABEL: fsub_v4f32:
@@ -341,28 +299,9 @@ define <4 x float> @fmul_v4f32(<4 x float> %vf1, <4 x float> %vf2) #0 {
;
; NOVSX-LABEL: fmul_v4f32:
; NOVSX: # %bb.0:
-; NOVSX-NEXT: addi r3, r1, -32
-; NOVSX-NEXT: stvx v3, 0, r3
-; NOVSX-NEXT: addi r3, r1, -48
-; NOVSX-NEXT: stvx v2, 0, r3
-; NOVSX-NEXT: addi r3, r1, -16
-; NOVSX-NEXT: lfs f0, -20(r1)
-; NOVSX-NEXT: lfs f1, -36(r1)
-; NOVSX-NEXT: fmuls f0, f1, f0
-; NOVSX-NEXT: lfs f1, -40(r1)
-; NOVSX-NEXT: stfs f0, -4(r1)
-; NOVSX-NEXT: lfs f0, -24(r1)
-; NOVSX-NEXT: fmuls f0, f1, f0
-; NOVSX-NEXT: lfs f1, -44(r1)
-; NOVSX-NEXT: stfs f0, -8(r1)
-; NOVSX-NEXT: lfs f0, -28(r1)
-; NOVSX-NEXT: fmuls f0, f1, f0
-; NOVSX-NEXT: lfs f1, -48(r1)
-; NOVSX-NEXT: stfs f0, -12(r1)
-; NOVSX-NEXT: lfs f0, -32(r1)
-; NOVSX-NEXT: fmuls f0, f1, f0
-; NOVSX-NEXT: stfs f0, -16(r1)
-; NOVSX-NEXT: lvx v2, 0, r3
+; NOVSX-NEXT: vspltisw v4, -1
+; NOVSX-NEXT: vslw v4, v4, v4
+; NOVSX-NEXT: vmaddfp v2, v2, v3, v4
; NOVSX-NEXT: blr
;
; SPE-LABEL: fmul_v4f32:
@@ -648,34 +587,7 @@ define <4 x float> @fmadd_v4f32(<4 x float> %vf0, <4 x float> %vf1, <4 x float>
;
; NOVSX-LABEL: fmadd_v4f32:
; NOVSX: # %bb.0:
-; NOVSX-NEXT: addi r3, r1, -32
-; NOVSX-NEXT: stvx v4, 0, r3
-; NOVSX-NEXT: addi r3, r1, -48
-; NOVSX-NEXT: stvx v3, 0, r3
-; NOVSX-NEXT: addi r3, r1, -64
-; NOVSX-NEXT: stvx v2, 0, r3
-; NOVSX-NEXT: addi r3, r1, -16
-; NOVSX-NEXT: lfs f0, -20(r1)
-; NOVSX-NEXT: lfs f1, -36(r1)
-; NOVSX-NEXT: lfs f2, -52(r1)
-; NOVSX-NEXT: fmadds f0, f2, f1, f0
-; NOVSX-NEXT: lfs f1, -40(r1)
-; NOVSX-NEXT: lfs f2, -56(r1)
-; NOVSX-NEXT: stfs f0, -4(r1)
-; NOVSX-NEXT: lfs f0, -24(r1)
-; NOVSX-NEXT: fmadds f0, f2, f1, f0
-; NOVSX-NEXT: lfs f1, -44(r1)
-; NOVSX-NEXT: lfs f2, -60(r1)
-; NOVSX-NEXT: stfs f0, -8(r1)
-; NOVSX-NEXT: lfs f0, -28(r1)
-; NOVSX-NEXT: fmadds f0, f2, f1, f0
-; NOVSX-NEXT: lfs f1, -48(r1)
-; NOVSX-NEXT: lfs f2, -64(r1)
-; NOVSX-NEXT: stfs f0, -12(r1)
-; NOVSX-NEXT: lfs f0, -32(r1)
-; NOVSX-NEXT: fmadds f0, f2, f1, f0
-; NOVSX-NEXT: stfs f0, -16(r1)
-; NOVSX-NEXT: lvx v2, 0, r3
+; NOVSX-NEXT: vmaddfp v2, v2, v3, v4
; NOVSX-NEXT: blr
;
; SPE-LABEL: fmadd_v4f32:
@@ -911,36 +823,9 @@ define <4 x float> @fmsub_v4f32(<4 x float> %vf0, <4 x float> %vf1, <4 x float>
; NOVSX-LABEL: fmsub_v4f32:
; NOVSX: # %bb.0:
; NOVSX-NEXT: vspltisb v5, -1
-; NOVSX-NEXT: addi r3, r1, -48
; NOVSX-NEXT: vslw v5, v5, v5
-; NOVSX-NEXT: stvx v3, 0, r3
-; NOVSX-NEXT: addi r3, r1, -64
; NOVSX-NEXT: vxor v4, v4, v5
-; NOVSX-NEXT: stvx v2, 0, r3
-; NOVSX-NEXT: addi r3, r1, -32
-; NOVSX-NEXT: stvx v4, 0, r3
-; NOVSX-NEXT: addi r3, r1, -16
-; NOVSX-NEXT: lfs f0, -36(r1)
-; NOVSX-NEXT: lfs f1, -52(r1)
-; NOVSX-NEXT: lfs f2, -20(r1)
-; NOVSX-NEXT: fmadds f0, f1, f0, f2
-; NOVSX-NEXT: lfs f1, -56(r1)
-; NOVSX-NEXT: lfs f2, -24(r1)
-; NOVSX-NEXT: stfs f0, -4(r1)
-; NOVSX-NEXT: lfs f0, -40(r1)
-; NOVSX-NEXT: fmadds f0, f1, f0, f2
-; NOVSX-NEXT: lfs f1, -60(r1)
-; NOVSX-NEXT: lfs f2, -28(r1)
-; NOVSX-NEXT: stfs f0, -8(r1)
-; NOVSX-NEXT: lfs f0, -44(r1)
-; NOVSX-NEXT: fmadds f0, f1, f0, f2
-; NOVSX-NEXT: lfs f1, -64(r1)
-; NOVSX-NEXT: lfs f2, -32(r1)
-; NOVSX-NEXT: stfs f0, -12(r1)
-; NOVSX-NEXT: lfs f0, -48(r1)
-; NOVSX-NEXT: fmadds f0, f1, f0, f2
-; NOVSX-NEXT: stfs f0, -16(r1)
-; NOVSX-NEXT: lvx v2, 0, r3
+; NOVSX-NEXT: vmaddfp v2, v2, v3, v4
; NOVSX-NEXT: blr
;
; SPE-LABEL: fmsub_v4f32:
@@ -1183,36 +1068,9 @@ define <4 x float> @fnmadd_v4f32(<4 x float> %vf0, <4 x float> %vf1, <4 x float>
;
; NOVSX-LABEL: fnmadd_v4f32:
; NOVSX: # %bb.0:
-; NOVSX-NEXT: addi r3, r1, -32
+; NOVSX-NEXT: vmaddfp v2, v2, v3, v4
; NOVSX-NEXT: vspltisb v5, -1
-; NOVSX-NEXT: stvx v4, 0, r3
-; NOVSX-NEXT: addi r3, r1, -48
-; NOVSX-NEXT: stvx v3, 0, r3
-; NOVSX-NEXT: addi r3, r1, -64
; NOVSX-NEXT: vslw v3, v5, v5
-; NOVSX-NEXT: stvx v2, 0, r3
-; NOVSX-NEXT: addi r3, r1, -16
-; NOVSX-NEXT: lfs f0, -20(r1)
-; NOVSX-NEXT: lfs f1, -36(r1)
-; NOVSX-NEXT: lfs f2, -52(r1)
-; NOVSX-NEXT: fmadds f0, f2, f1, f0
-; NOVSX-NEXT: lfs f1, -40(r1)
-; NOVSX-NEXT: lfs f2, -56(r1)
-; NOVSX-NEXT: stfs f0, -4(r1)
-; NOVSX-NEXT: lfs f0, -24(r1)
-; NOVSX-NEXT: fmadds f0, f2, f1, f0
-; NOVSX-NEXT: lfs f1, -44(r1)
-; NOVSX-NEXT: lfs f2, -60(r1)
-; NOVSX-NEXT: stfs f0, -8(r1)
-; NOVSX-NEXT: lfs f0, -28(r1)
-; NOVSX-NEXT: fmadds f0, f2, f1, f0
-; NOVSX-NEXT: lfs f1, -48(r1)
-; NOVSX-NEXT: lfs f2, -64(r1)
-; NOVSX-NEXT: stfs f0, -12(r1)
-; NOVSX-NEXT: lfs f0, -32(r1)
-; NOVSX-NEXT: fmadds f0, f2, f1, f0
-; NOVSX-NEXT: stfs f0, -16(r1)
-; NOVSX-NEXT: lvx v2, 0, r3
; NOVSX-NEXT: vxor v2, v2, v3
; NOVSX-NEXT: blr
;
@@ -1457,38 +1315,7 @@ define <4 x float> @fnmsub_v4f32(<4 x float> %vf0, <4 x float> %vf1, <4 x float>
;
; NOVSX-LABEL: fnmsub_v4f32:
; NOVSX: # %bb.0:
-; NOVSX-NEXT: vspltisb v5, -1
-; NOVSX-NEXT: addi r3, r1, -48
-; NOVSX-NEXT: vslw v5, v5, v5
-; NOVSX-NEXT: stvx v3, 0, r3
-; NOVSX-NEXT: addi r3, r1, -64
-; NOVSX-NEXT: vxor v4, v4, v5
-; NOVSX-NEXT: stvx v2, 0, r3
-; NOVSX-NEXT: addi r3, r1, -32
-; NOVSX-NEXT: stvx v4, 0, r3
-; NOVSX-NEXT: addi r3, r1, -16
-; NOVSX-NEXT: lfs f0, -36(r1)
-; NOVSX-NEXT: lfs f1, -52(r1)
-; NOVSX-NEXT: lfs f2, -20(r1)
-; NOVSX-NEXT: fmadds f0, f1, f0, f2
-; NOVSX-NEXT: lfs f1, -56(r1)
-; NOVSX-NEXT: lfs f2, -24(r1)
-; NOVSX-NEXT: stfs f0, -4(r1)
-; NOVSX-NEXT: lfs f0, -40(r1)
-; NOVSX-NEXT: fmadds f0, f1, f0, f2
-; NOVSX-NEXT: lfs f1, -60(r1)
-; NOVSX-NEXT: lfs f2, -28(r1)
-; NOVSX-NEXT: stfs f0, -8(r1)
-; NOVSX-NEXT: lfs f0, -44(r1)
-; NOVSX-NEXT: fmadds f0, f1, f0, f2
-; NOVSX-NEXT: lfs f1, -64(r1)
-; NOVSX-NEXT: lfs f2, -32(r1)
-; NOVSX-NEXT: stfs f0, -12(r1)
-; NOVSX-NEXT: lfs f0, -48(r1)
-; NOVSX-NEXT: fmadds f0, f1, f0, f2
-; NOVSX-NEXT: stfs f0, -16(r1)
-; NOVSX-NEXT: lvx v2, 0, r3
-; NOVSX-NEXT: vxor v2, v2, v5
+; NOVSX-NEXT: vnmsubfp v2, v2, v3, v4
; NOVSX-NEXT: blr
;
; SPE-LABEL: fnmsub_v4f32:
diff --git a/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
index 614f7b243c7e2..4fb4080cc3f95 100644
--- a/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
@@ -250,28 +250,8 @@ define <2 x double> @constrained_vector_frem_v2f64() #0 {
;
; SZ13-LABEL: constrained_vector_frem_v2f64:
; SZ13: # %bb.0: # %entry
-; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
-; SZ13-NEXT: .cfi_offset %r14, -48
-; SZ13-NEXT: .cfi_offset %r15, -40
-; SZ13-NEXT: aghi %r15, -184
-; SZ13-NEXT: .cfi_def_cfa_offset 344
-; SZ13-NEXT: std %f8, 176(%r15) # 8-byte Spill
-; SZ13-NEXT: .cfi_offset %f8, -168
; SZ13-NEXT: larl %r1, .LCPI6_0
-; SZ13-NEXT: ld %f8, 0(%r1)
-; SZ13-NEXT: vgmg %v0, 1, 1
-; SZ13-NEXT: ldr %f2, %f8
-; SZ13-NEXT: brasl %r14, fmod at PLT
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: vgmg %v0, 2, 11
-; SZ13-NEXT: ldr %f2, %f8
-; SZ13-NEXT: brasl %r14, fmod at PLT
-; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: ld %f8, 176(%r15) # 8-byte Reload
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v24, %v0, %v1
-; SZ13-NEXT: lmg %r14, %r15, 296(%r15)
+; SZ13-NEXT: vl %v24, 0(%r1), 3
; SZ13-NEXT: br %r14
entry:
%rem = call <2 x double> @llvm.experimental.constrained.frem.v2f64(
@@ -508,43 +488,10 @@ define <4 x double> @constrained_vector_frem_v4f64() #0 {
;
; SZ13-LABEL: constrained_vector_frem_v4f64:
; SZ13: # %bb.0:
-; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
-; SZ13-NEXT: .cfi_offset %r14, -48
-; SZ13-NEXT: .cfi_offset %r15, -40
-; SZ13-NEXT: aghi %r15, -200
-; SZ13-NEXT: .cfi_def_cfa_offset 360
-; SZ13-NEXT: std %f8, 192(%r15) # 8-byte Spill
-; SZ13-NEXT: .cfi_offset %f8, -168
; SZ13-NEXT: larl %r1, .LCPI9_0
-; SZ13-NEXT: ld %f8, 0(%r1)
-; SZ13-NEXT: vgmg %v0, 1, 1
-; SZ13-NEXT: ldr %f2, %f8
-; SZ13-NEXT: brasl %r14, fmod at PLT
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: vgmg %v0, 2, 11
-; SZ13-NEXT: ldr %f2, %f8
-; SZ13-NEXT: brasl %r14, fmod at PLT
-; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: vl %v24, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI9_1
-; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ldr %f2, %f8
-; SZ13-NEXT: brasl %r14, fmod at PLT
-; SZ13-NEXT: larl %r1, .LCPI9_2
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ldr %f2, %f8
-; SZ13-NEXT: brasl %r14, fmod at PLT
-; SZ13-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: vl %v24, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: ld %f8, 192(%r15) # 8-byte Reload
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v26, %v0, %v1
-; SZ13-NEXT: lmg %r14, %r15, 312(%r15)
+; SZ13-NEXT: vl %v26, 0(%r1), 3
; SZ13-NEXT: br %r14
%rem = call <4 x double> @llvm.experimental.constrained.frem.v4f64(
<4 x double> <double 1.000000e+00, double 2.000000e+00,
@@ -4588,27 +4535,8 @@ define <2 x double> @constrained_vector_maxnum_v2f64() #0 {
;
; SZ13-LABEL: constrained_vector_maxnum_v2f64:
; SZ13: # %bb.0: # %entry
-; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
-; SZ13-NEXT: .cfi_offset %r14, -48
-; SZ13-NEXT: .cfi_offset %r15, -40
-; SZ13-NEXT: aghi %r15, -176
-; SZ13-NEXT: .cfi_def_cfa_offset 336
; SZ13-NEXT: larl %r1, .LCPI86_0
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI86_1
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmax at PLT
-; SZ13-NEXT: larl %r1, .LCPI86_2
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI86_3
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmax at PLT
-; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v24, %v0, %v1
-; SZ13-NEXT: lmg %r14, %r15, 288(%r15)
+; SZ13-NEXT: vl %v24, 0(%r1), 3
; SZ13-NEXT: br %r14
entry:
%max = call <2 x double> @llvm.experimental.constrained.maxnum.v2f64(
@@ -4844,44 +4772,10 @@ define <4 x double> @constrained_vector_maxnum_v4f64() #0 {
;
; SZ13-LABEL: constrained_vector_maxnum_v4f64:
; SZ13: # %bb.0: # %entry
-; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
-; SZ13-NEXT: .cfi_offset %r14, -48
-; SZ13-NEXT: .cfi_offset %r15, -40
-; SZ13-NEXT: aghi %r15, -192
-; SZ13-NEXT: .cfi_def_cfa_offset 352
; SZ13-NEXT: larl %r1, .LCPI89_0
-; SZ13-NEXT: ld %f0, 0(%r1)
+; SZ13-NEXT: vl %v24, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI89_1
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmax at PLT
-; SZ13-NEXT: larl %r1, .LCPI89_2
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI89_3
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmax at PLT
-; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v1
-; SZ13-NEXT: larl %r1, .LCPI89_4
-; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI89_5
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmax at PLT
-; SZ13-NEXT: larl %r1, .LCPI89_6
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI89_7
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmax at PLT
-; SZ13-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: vl %v24, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v26, %v0, %v1
-; SZ13-NEXT: lmg %r14, %r15, 304(%r15)
+; SZ13-NEXT: vl %v26, 0(%r1), 3
; SZ13-NEXT: br %r14
entry:
%max = call <4 x double> @llvm.experimental.constrained.maxnum.v4f64(
@@ -4961,27 +4855,8 @@ define <2 x double> @constrained_vector_minnum_v2f64() #0 {
;
; SZ13-LABEL: constrained_vector_minnum_v2f64:
; SZ13: # %bb.0: # %entry
-; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
-; SZ13-NEXT: .cfi_offset %r14, -48
-; SZ13-NEXT: .cfi_offset %r15, -40
-; SZ13-NEXT: aghi %r15, -176
-; SZ13-NEXT: .cfi_def_cfa_offset 336
; SZ13-NEXT: larl %r1, .LCPI91_0
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI91_1
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmin at PLT
-; SZ13-NEXT: larl %r1, .LCPI91_2
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI91_3
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmin at PLT
-; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v24, %v0, %v1
-; SZ13-NEXT: lmg %r14, %r15, 288(%r15)
+; SZ13-NEXT: vl %v24, 0(%r1), 3
; SZ13-NEXT: br %r14
entry:
%min = call <2 x double> @llvm.experimental.constrained.minnum.v2f64(
@@ -5221,44 +5096,10 @@ define <4 x double> @constrained_vector_minnum_v4f64() #0 {
;
; SZ13-LABEL: constrained_vector_minnum_v4f64:
; SZ13: # %bb.0: # %entry
-; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
-; SZ13-NEXT: .cfi_offset %r14, -48
-; SZ13-NEXT: .cfi_offset %r15, -40
-; SZ13-NEXT: aghi %r15, -192
-; SZ13-NEXT: .cfi_def_cfa_offset 352
; SZ13-NEXT: larl %r1, .LCPI94_0
-; SZ13-NEXT: ld %f0, 0(%r1)
+; SZ13-NEXT: vl %v24, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI94_1
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmin at PLT
-; SZ13-NEXT: larl %r1, .LCPI94_2
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI94_3
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmin at PLT
-; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v1
-; SZ13-NEXT: larl %r1, .LCPI94_4
-; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI94_5
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmin at PLT
-; SZ13-NEXT: larl %r1, .LCPI94_6
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: larl %r1, .LCPI94_7
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: brasl %r14, fmin at PLT
-; SZ13-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: vl %v24, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v26, %v0, %v1
-; SZ13-NEXT: lmg %r14, %r15, 304(%r15)
+; SZ13-NEXT: vl %v26, 0(%r1), 3
; SZ13-NEXT: br %r14
entry:
%min = call <4 x double> @llvm.experimental.constrained.minnum.v4f64(
diff --git a/llvm/test/CodeGen/X86/avx512fp16-frem.ll b/llvm/test/CodeGen/X86/avx512fp16-frem.ll
index 2164c2460f6d7..864f8b8b4f144 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-frem.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-frem.ll
@@ -895,21 +895,21 @@ define <8 x half> @frem_strict_vec8(<8 x half> %x, <8 x half> %y) nounwind #0 {
; CHECK-LABEL: frem_strict_vec8:
; CHECK: # %bb.0:
; CHECK-NEXT: subq $88, %rsp
-; CHECK-NEXT: vmovapd %xmm1, (%rsp) # 16-byte Spill
-; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm2, %xmm2, %xmm1
+; CHECK-NEXT: vmovapd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpsrldq {{.*#+}} xmm2 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm2, %xmm2, %xmm0
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm2, %xmm2, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -917,19 +917,19 @@ define <8 x half> @frem_strict_vec8(<8 x half> %x, <8 x half> %y) nounwind #0 {
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq $10, (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,0]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -938,34 +938,34 @@ define <8 x half> @frem_strict_vec8(<8 x half> %x, <8 x half> %y) nounwind #0 {
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrlq $48, (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrld $16, (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
@@ -985,25 +985,25 @@ define <16 x half> @frem_strict_vec16(<16 x half> %x, <16 x half> %y) nounwind #
; CHECK: # %bb.0:
; CHECK-NEXT: subq $168, %rsp
; CHECK-NEXT: vmovupd %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
-; CHECK-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovupd %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm1
; CHECK-NEXT: vmovapd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1011,19 +1011,19 @@ define <16 x half> @frem_strict_vec16(<16 x half> %x, <16 x half> %y) nounwind #
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,0]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1033,19 +1033,19 @@ define <16 x half> @frem_strict_vec16(<16 x half> %x, <16 x half> %y) nounwind #
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1053,19 +1053,19 @@ define <16 x half> @frem_strict_vec16(<16 x half> %x, <16 x half> %y) nounwind #
; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,0]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1075,35 +1075,35 @@ define <16 x half> @frem_strict_vec16(<16 x half> %x, <16 x half> %y) nounwind #
; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
@@ -1112,35 +1112,35 @@ define <16 x half> @frem_strict_vec16(<16 x half> %x, <16 x half> %y) nounwind #
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovdqa (%rsp), %xmm1 # 16-byte Reload
@@ -1161,25 +1161,25 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK: # %bb.0:
; CHECK-NEXT: subq $360, %rsp # imm = 0x168
; CHECK-NEXT: vmovupd %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
-; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT: vmovupd %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vextractf32x4 $3, %zmm1, %xmm1
; CHECK-NEXT: vmovapd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
-; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1187,19 +1187,19 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,0]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1211,22 +1211,22 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm0
; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
-; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm0
-; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload
+; CHECK-NEXT: vextractf32x4 $2, %zmm1, %xmm1
+; CHECK-NEXT: vmovapd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1234,19 +1234,19 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq $10, (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,0]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1259,22 +1259,22 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
-; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm1
+; CHECK-NEXT: vmovapd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1282,19 +1282,19 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,0]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1304,19 +1304,19 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1324,19 +1324,19 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,0]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
@@ -1347,35 +1347,35 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm0 # 32-byte Folded Reload
; CHECK-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
@@ -1384,34 +1384,34 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrlq $48, (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrld $16, (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
@@ -1421,35 +1421,35 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovdqa (%rsp), %xmm1 # 16-byte Reload
@@ -1458,35 +1458,35 @@ define <32 x half> @frem_strict_vec32(<32 x half> %x, <32 x half> %y) nounwind #
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklwd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm1
-; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpsrld $16, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: callq fmodf at PLT
; CHECK-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
diff --git a/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
index 88d3ad181d766..731cd27433f1d 100644
--- a/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
@@ -179,36 +179,12 @@ entry:
define <2 x double> @constrained_vector_frem_v2f64() #0 {
; CHECK-LABEL: constrained_vector_frem_v2f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [2.0E+0,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmod at PLT
-; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.0E+0,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmod at PLT
-; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
; CHECK-NEXT: retq
;
; AVX-LABEL: constrained_vector_frem_v2f64:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: subq $24, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 32
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [2.0E+0,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; AVX-NEXT: callq fmod at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [1.0E+0,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; AVX-NEXT: callq fmod at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: addq $24, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 8
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
; AVX-NEXT: retq
entry:
%rem = call <2 x double> @llvm.experimental.constrained.frem.v2f64(
@@ -278,51 +254,30 @@ entry:
define <3 x double> @constrained_vector_frem_v3f64() #0 {
; CHECK-LABEL: constrained_vector_frem_v3f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [2.0E+0,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmod at PLT
-; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.0E+0,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmod at PLT
-; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [3.0E+0,0.0E+0]
; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
; CHECK-NEXT: callq fmod at PLT
-; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movsd %xmm0, (%rsp)
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.0E+0,0.0E+0]
+; CHECK-NEXT: fldl (%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
-; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
-; CHECK-NEXT: # xmm1 = mem[0],zero
-; CHECK-NEXT: addq $24, %rsp
+; CHECK-NEXT: movsd {{.*#+}} xmm1 = [2.0E+0,0.0E+0]
+; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
;
; AVX-LABEL: constrained_vector_frem_v3f64:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: subq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 48
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [2.0E+0,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; AVX-NEXT: callq fmod at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [1.0E+0,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; AVX-NEXT: callq fmod at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
+; AVX-NEXT: pushq %rax
+; AVX-NEXT: .cfi_def_cfa_offset 16
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [3.0E+0,0.0E+0]
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; AVX-NEXT: vzeroupper
; AVX-NEXT: callq fmod at PLT
-; AVX-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
+; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [1.0E+0,2.0E+0]
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX-NEXT: addq $40, %rsp
+; AVX-NEXT: popq %rax
; AVX-NEXT: .cfi_def_cfa_offset 8
; AVX-NEXT: retq
entry:
@@ -337,59 +292,13 @@ entry:
define <4 x double> @constrained_vector_frem_v4f64() #0 {
; CHECK-LABEL: constrained_vector_frem_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: subq $40, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [2.0E+0,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmod at PLT
-; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.0E+0,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmod at PLT
-; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
-; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.0E+0,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmod at PLT
-; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [3.0E+0,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmod at PLT
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
-; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: addq $40, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [3.0E+0,4.0E+0]
; CHECK-NEXT: retq
;
; AVX-LABEL: constrained_vector_frem_v4f64:
; AVX: # %bb.0:
-; AVX-NEXT: subq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 48
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.0E+0,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; AVX-NEXT: callq fmod at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [3.0E+0,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; AVX-NEXT: callq fmod at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [2.0E+0,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; AVX-NEXT: callq fmod at PLT
-; AVX-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [1.0E+0,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+1,0.0E+0]
-; AVX-NEXT: callq fmod at PLT
-; AVX-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
-; AVX-NEXT: addq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 8
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
; AVX-NEXT: retq
%rem = call <4 x double> @llvm.experimental.constrained.frem.v4f64(
<4 x double> <double 1.000000e+00, double 2.000000e+00,
@@ -1058,11 +967,11 @@ define <3 x double> @constrained_vector_pow_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+0,0.0E+0]
; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+0,0.0E+0]
; CHECK-NEXT: callq pow at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
@@ -1072,9 +981,9 @@ define <3 x double> @constrained_vector_pow_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -1315,11 +1224,11 @@ define <3 x double> @constrained_vector_powi_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: movl $3, %edi
; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: movl $3, %edi
; CHECK-NEXT: callq __powidf2 at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
@@ -1329,9 +1238,9 @@ define <3 x double> @constrained_vector_powi_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -1556,10 +1465,10 @@ define <3 x double> @constrained_vector_sin_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq sin at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq sin at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -1567,9 +1476,9 @@ define <3 x double> @constrained_vector_sin_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -1781,10 +1690,10 @@ define <3 x double> @constrained_vector_cos_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq cos at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq cos at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -1792,9 +1701,9 @@ define <3 x double> @constrained_vector_cos_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -2006,10 +1915,10 @@ define <3 x double> @constrained_vector_exp_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq exp at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -2017,9 +1926,9 @@ define <3 x double> @constrained_vector_exp_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -2231,10 +2140,10 @@ define <3 x double> @constrained_vector_exp2_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq exp2 at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq exp2 at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -2242,9 +2151,9 @@ define <3 x double> @constrained_vector_exp2_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -2456,10 +2365,10 @@ define <3 x double> @constrained_vector_log_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq log at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq log at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -2467,9 +2376,9 @@ define <3 x double> @constrained_vector_log_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -2681,10 +2590,10 @@ define <3 x double> @constrained_vector_log10_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq log10 at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq log10 at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -2692,9 +2601,9 @@ define <3 x double> @constrained_vector_log10_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -2906,10 +2815,10 @@ define <3 x double> @constrained_vector_log2_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq log2 at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq log2 at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -2917,9 +2826,9 @@ define <3 x double> @constrained_vector_log2_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -3145,10 +3054,10 @@ define <3 x double> @constrained_vector_rint_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq rint at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq rint at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -3156,9 +3065,9 @@ define <3 x double> @constrained_vector_rint_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -3188,10 +3097,10 @@ define <3 x double> @constrained_vector_rint_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq rint at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq rint at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
@@ -3200,9 +3109,9 @@ define <3 x double> @constrained_vector_rint_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -3441,10 +3350,10 @@ define <3 x double> @constrained_vector_nearby_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq nearbyint at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq nearbyint at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -3452,9 +3361,9 @@ define <3 x double> @constrained_vector_nearby_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -3484,10 +3393,10 @@ define <3 x double> @constrained_vector_nearbyint_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq nearbyint at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq nearbyint at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
@@ -3496,9 +3405,9 @@ define <3 x double> @constrained_vector_nearbyint_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -3635,36 +3544,12 @@ entry:
define <2 x double> @constrained_vector_maxnum_v2f64() #0 {
; CHECK-LABEL: constrained_vector_maxnum_v2f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmax at PLT
-; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.3E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; CHECK-NEXT: callq fmax at PLT
-; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [4.3E+1,4.2E+1]
; CHECK-NEXT: retq
;
; AVX-LABEL: constrained_vector_maxnum_v2f64:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: subq $24, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 32
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; AVX-NEXT: callq fmax at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.3E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; AVX-NEXT: callq fmax at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: addq $24, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 8
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4.3E+1,4.2E+1]
; AVX-NEXT: retq
entry:
%max = call <2 x double> @llvm.experimental.constrained.maxnum.v2f64(
@@ -3732,51 +3617,30 @@ entry:
define <3 x double> @constrained_vector_max_v3f64() #0 {
; CHECK-LABEL: constrained_vector_max_v3f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.4E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; CHECK-NEXT: callq fmax at PLT
-; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.3E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmax at PLT
-; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.5E+1,0.0E+0]
; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq fmax at PLT
-; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movsd %xmm0, (%rsp)
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.3E+1,0.0E+0]
+; CHECK-NEXT: fldl (%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
-; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
-; CHECK-NEXT: # xmm1 = mem[0],zero
-; CHECK-NEXT: addq $24, %rsp
+; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.4E+1,0.0E+0]
+; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
;
; AVX-LABEL: constrained_vector_max_v3f64:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: subq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 48
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.4E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; AVX-NEXT: callq fmax at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.3E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; AVX-NEXT: callq fmax at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
+; AVX-NEXT: pushq %rax
+; AVX-NEXT: .cfi_def_cfa_offset 16
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.5E+1,0.0E+0]
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
-; AVX-NEXT: vzeroupper
; AVX-NEXT: callq fmax at PLT
-; AVX-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
+; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [4.3E+1,4.4E+1]
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX-NEXT: addq $40, %rsp
+; AVX-NEXT: popq %rax
; AVX-NEXT: .cfi_def_cfa_offset 8
; AVX-NEXT: retq
entry:
@@ -3790,59 +3654,13 @@ entry:
define <4 x double> @constrained_vector_maxnum_v4f64() #0 {
; CHECK-LABEL: constrained_vector_maxnum_v4f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $40, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.5E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; CHECK-NEXT: callq fmax at PLT
-; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.4E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmax at PLT
-; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
-; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.7E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.3E+1,0.0E+0]
-; CHECK-NEXT: callq fmax at PLT
-; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.6E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
-; CHECK-NEXT: callq fmax at PLT
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
-; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: addq $40, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [4.4E+1,4.5E+1]
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [4.6E+1,4.7E+1]
; CHECK-NEXT: retq
;
; AVX-LABEL: constrained_vector_maxnum_v4f64:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: subq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 48
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.7E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.3E+1,0.0E+0]
-; AVX-NEXT: callq fmax at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.6E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
-; AVX-NEXT: callq fmax at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.5E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; AVX-NEXT: callq fmax at PLT
-; AVX-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.4E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; AVX-NEXT: callq fmax at PLT
-; AVX-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
-; AVX-NEXT: addq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 8
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4.4E+1,4.5E+1,4.6E+1,4.7E+1]
; AVX-NEXT: retq
entry:
%max = call <4 x double> @llvm.experimental.constrained.maxnum.v4f64(
@@ -3886,36 +3704,12 @@ define <1 x float> @constrained_vector_minnum_v1f32() #0 {
define <2 x double> @constrained_vector_minnum_v2f64() #0 {
; CHECK-LABEL: constrained_vector_minnum_v2f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmin at PLT
-; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.3E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; CHECK-NEXT: callq fmin at PLT
-; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [4.1E+1,4.0E+1]
; CHECK-NEXT: retq
;
; AVX-LABEL: constrained_vector_minnum_v2f64:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: subq $24, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 32
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; AVX-NEXT: callq fmin at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.3E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; AVX-NEXT: callq fmin at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: addq $24, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 8
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4.1E+1,4.0E+1]
; AVX-NEXT: retq
entry:
%min = call <2 x double> @llvm.experimental.constrained.minnum.v2f64(
@@ -3983,51 +3777,30 @@ entry:
define <3 x double> @constrained_vector_min_v3f64() #0 {
; CHECK-LABEL: constrained_vector_min_v3f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.4E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; CHECK-NEXT: callq fmin at PLT
-; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.3E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmin at PLT
-; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.5E+1,0.0E+0]
; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq fmin at PLT
-; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movsd %xmm0, (%rsp)
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.0E+1,0.0E+0]
+; CHECK-NEXT: fldl (%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
-; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
-; CHECK-NEXT: # xmm1 = mem[0],zero
-; CHECK-NEXT: addq $24, %rsp
+; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
+; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
;
; AVX-LABEL: constrained_vector_min_v3f64:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: subq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 48
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.4E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; AVX-NEXT: callq fmin at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.3E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; AVX-NEXT: callq fmin at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
+; AVX-NEXT: pushq %rax
+; AVX-NEXT: .cfi_def_cfa_offset 16
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.5E+1,0.0E+0]
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
-; AVX-NEXT: vzeroupper
; AVX-NEXT: callq fmin at PLT
-; AVX-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
+; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [4.0E+1,4.1E+1]
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX-NEXT: addq $40, %rsp
+; AVX-NEXT: popq %rax
; AVX-NEXT: .cfi_def_cfa_offset 8
; AVX-NEXT: retq
entry:
@@ -4041,59 +3814,13 @@ entry:
define <4 x double> @constrained_vector_minnum_v4f64() #0 {
; CHECK-LABEL: constrained_vector_minnum_v4f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $40, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.5E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; CHECK-NEXT: callq fmin at PLT
-; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.4E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; CHECK-NEXT: callq fmin at PLT
-; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
-; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.7E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.3E+1,0.0E+0]
-; CHECK-NEXT: callq fmin at PLT
-; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.6E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
-; CHECK-NEXT: callq fmin at PLT
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
-; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
-; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; CHECK-NEXT: addq $40, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [4.0E+1,4.1E+1]
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [4.2E+1,4.3E+1]
; CHECK-NEXT: retq
;
; AVX-LABEL: constrained_vector_minnum_v4f64:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: subq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 48
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.7E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.3E+1,0.0E+0]
-; AVX-NEXT: callq fmin at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.6E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
-; AVX-NEXT: callq fmin at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.5E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.1E+1,0.0E+0]
-; AVX-NEXT: callq fmin at PLT
-; AVX-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.4E+1,0.0E+0]
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.0E+1,0.0E+0]
-; AVX-NEXT: callq fmin at PLT
-; AVX-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
-; AVX-NEXT: addq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 8
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4.0E+1,4.1E+1,4.2E+1,4.3E+1]
; AVX-NEXT: retq
entry:
%min = call <4 x double> @llvm.experimental.constrained.minnum.v4f64(
@@ -4301,32 +4028,12 @@ define <4 x i64> @constrained_vector_fptosi_v4i64_v4f32() #0 {
;
; AVX1-LABEL: constrained_vector_fptosi_v4i64_v4f32:
; AVX1: # %bb.0: # %entry
-; AVX1-NEXT: vcvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm0
-; AVX1-NEXT: vcvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm1
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; AVX1-NEXT: vcvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm1
-; AVX1-NEXT: vcvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm2
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [42,43,44,45]
; AVX1-NEXT: retq
;
; AVX512F-LABEL: constrained_vector_fptosi_v4i64_v4f32:
; AVX512F: # %bb.0: # %entry
-; AVX512F-NEXT: vcvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm0
-; AVX512F-NEXT: vcvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm1
-; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; AVX512F-NEXT: vcvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm1
-; AVX512F-NEXT: vcvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm2
-; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX512F-NEXT: vpmovsxbq {{.*#+}} ymm0 = [42,43,44,45]
; AVX512F-NEXT: retq
;
; AVX512DQ-LABEL: constrained_vector_fptosi_v4i64_v4f32:
@@ -4448,29 +4155,18 @@ entry:
define <2 x i64> @constrained_vector_fptosi_v2i64_v2f64() #0 {
; CHECK-LABEL: constrained_vector_fptosi_v2i64_v2f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; CHECK-NEXT: movq %rax, %xmm1
-; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; CHECK-NEXT: movq %rax, %xmm0
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [42,42]
; CHECK-NEXT: retq
;
; AVX1-LABEL: constrained_vector_fptosi_v2i64_v2f64:
; AVX1: # %bb.0: # %entry
-; AVX1-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm0
-; AVX1-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm1
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = [42,42]
+; AVX1-NEXT: # xmm0 = mem[0,0]
; AVX1-NEXT: retq
;
; AVX512F-LABEL: constrained_vector_fptosi_v2i64_v2f64:
; AVX512F: # %bb.0: # %entry
-; AVX512F-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm0
-; AVX512F-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm1
-; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX512F-NEXT: vpmovsxbq {{.*#+}} xmm0 = [42,42]
; AVX512F-NEXT: retq
;
; AVX512DQ-LABEL: constrained_vector_fptosi_v2i64_v2f64:
@@ -4529,46 +4225,18 @@ entry:
define <4 x i64> @constrained_vector_fptosi_v4i64_v4f64() #0 {
; CHECK-LABEL: constrained_vector_fptosi_v4i64_v4f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; CHECK-NEXT: movq %rax, %xmm1
-; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; CHECK-NEXT: movq %rax, %xmm0
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; CHECK-NEXT: movq %rax, %xmm2
-; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; CHECK-NEXT: movq %rax, %xmm1
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [42,42]
+; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: retq
;
; AVX1-LABEL: constrained_vector_fptosi_v4i64_v4f64:
; AVX1: # %bb.0: # %entry
-; AVX1-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm0
-; AVX1-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm1
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; AVX1-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm1
-; AVX1-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX1-NEXT: vmovq %rax, %xmm2
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm0 = [42,42,42,42]
; AVX1-NEXT: retq
;
; AVX512F-LABEL: constrained_vector_fptosi_v4i64_v4f64:
; AVX512F: # %bb.0: # %entry
-; AVX512F-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm0
-; AVX512F-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm1
-; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; AVX512F-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm1
-; AVX512F-NEXT: vcvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
-; AVX512F-NEXT: vmovq %rax, %xmm2
-; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX512F-NEXT: vbroadcastsd {{.*#+}} ymm0 = [42,42,42,42]
; AVX512F-NEXT: retq
;
; AVX512DQ-LABEL: constrained_vector_fptosi_v4i64_v4f64:
@@ -5977,10 +5645,10 @@ define <3 x double> @constrained_vector_ceil_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq ceil at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq ceil at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
@@ -5989,9 +5657,9 @@ define <3 x double> @constrained_vector_ceil_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -6120,10 +5788,10 @@ define <3 x double> @constrained_vector_floor_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq floor at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq floor at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
@@ -6132,9 +5800,9 @@ define <3 x double> @constrained_vector_floor_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -6204,20 +5872,11 @@ define <2 x double> @constrained_vector_round_v2f64_var(ptr %a) #0 {
;
; AVX-LABEL: constrained_vector_round_v2f64_var:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: subq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 48
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: callq round at PLT
-; AVX-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
-; AVX-NEXT: # xmm0 = mem[0],zero
-; AVX-NEXT: callq round at PLT
-; AVX-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: addq $40, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 8
+; AVX-NEXT: vmovapd (%rdi), %xmm0
+; AVX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vroundpd $11, %xmm0, %xmm0
; AVX-NEXT: retq
entry:
%b = load <2 x double>, ptr %a
@@ -6297,10 +5956,10 @@ define <3 x double> @constrained_vector_round_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq round at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq round at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
@@ -6309,9 +5968,9 @@ define <3 x double> @constrained_vector_round_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -6319,31 +5978,20 @@ define <3 x double> @constrained_vector_round_v3f64_var(ptr %a) #0 {
;
; AVX-LABEL: constrained_vector_round_v3f64_var:
; AVX: # %bb.0: # %entry
-; AVX-NEXT: pushq %rbx
-; AVX-NEXT: .cfi_def_cfa_offset 16
-; AVX-NEXT: subq $48, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 64
-; AVX-NEXT: .cfi_offset %rbx, -16
-; AVX-NEXT: movq %rdi, %rbx
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT: callq round at PLT
-; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
-; AVX-NEXT: # xmm0 = mem[0],zero
-; AVX-NEXT: callq round at PLT
-; AVX-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; AVX-NEXT: # xmm0 = xmm0[0],mem[0]
-; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; AVX-NEXT: subq $40, %rsp
+; AVX-NEXT: .cfi_def_cfa_offset 48
+; AVX-NEXT: vmovapd (%rdi), %xmm0
+; AVX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vroundpd $11, %xmm0, %xmm0
+; AVX-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vzeroupper
; AVX-NEXT: callq round at PLT
-; AVX-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload
+; AVX-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX-NEXT: addq $48, %rsp
-; AVX-NEXT: .cfi_def_cfa_offset 16
-; AVX-NEXT: popq %rbx
+; AVX-NEXT: addq $40, %rsp
; AVX-NEXT: .cfi_def_cfa_offset 8
; AVX-NEXT: retq
entry:
@@ -6461,10 +6109,10 @@ define <3 x double> @constrained_vector_trunc_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq trunc at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq trunc at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
@@ -6473,9 +6121,9 @@ define <3 x double> @constrained_vector_trunc_v3f64_var(ptr %a) #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -8217,10 +7865,10 @@ define <3 x double> @constrained_vector_tan_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq tan at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq tan at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -8228,9 +7876,9 @@ define <3 x double> @constrained_vector_tan_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -8442,10 +8090,10 @@ define <3 x double> @constrained_vector_acos_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq acos at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq acos at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -8453,9 +8101,9 @@ define <3 x double> @constrained_vector_acos_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -8667,10 +8315,10 @@ define <3 x double> @constrained_vector_asin_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq asin at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq asin at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -8678,9 +8326,9 @@ define <3 x double> @constrained_vector_asin_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -8892,10 +8540,10 @@ define <3 x double> @constrained_vector_atan_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq atan at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq atan at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -8903,9 +8551,9 @@ define <3 x double> @constrained_vector_atan_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -9132,13 +8780,13 @@ define <3 x double> @constrained_vector_atan2_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
-; CHECK-NEXT: movsd {{.*#+}} xmm1 = [2.3100000000000001E+1,0.0E+0]
-; CHECK-NEXT: callq atan2 at PLT
-; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: movsd {{.*#+}} xmm1 = [2.3E+1,0.0E+0]
; CHECK-NEXT: callq atan2 at PLT
+; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm1 = [2.3100000000000001E+1,0.0E+0]
+; CHECK-NEXT: callq atan2 at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
; CHECK-NEXT: movsd {{.*#+}} xmm1 = [2.3199999999999999E+1,0.0E+0]
@@ -9146,9 +8794,9 @@ define <3 x double> @constrained_vector_atan2_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -9374,10 +9022,10 @@ define <3 x double> @constrained_vector_cosh_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq cosh at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq cosh at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -9385,9 +9033,9 @@ define <3 x double> @constrained_vector_cosh_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -9599,10 +9247,10 @@ define <3 x double> @constrained_vector_sinh_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq sinh at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq sinh at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -9610,9 +9258,9 @@ define <3 x double> @constrained_vector_sinh_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
@@ -9824,10 +9472,10 @@ define <3 x double> @constrained_vector_tanh_v3f64() #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
; CHECK-NEXT: callq tanh at PLT
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
; CHECK-NEXT: callq tanh at PLT
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = [4.2200000000000003E+1,0.0E+0]
@@ -9835,9 +9483,9 @@ define <3 x double> @constrained_vector_tanh_v3f64() #0 {
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: wait
-; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
+; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
-; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
+; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
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