[llvm-branch-commits] [llvm] [AMDGPU] Fix register class in true16 for a few isel patterns (PR #219733)
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llvm-branch-commits at lists.llvm.org
Sat Aug 29 16:02:39 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Guo Chen (broxigarchen)
<details>
<summary>Changes</summary>
<sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
---
Patch is 2.03 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/219733.diff
67 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/BUFInstructions.td (+17-8)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+11-7)
- (modified) llvm/lib/Target/AMDGPU/VOP2Instructions.td (+23-1)
- (modified) llvm/lib/Target/AMDGPU/VOP3Instructions.td (+4)
- (modified) llvm/lib/Target/AMDGPU/VOPInstructions.td (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll (+13-6)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll (+431-477)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll (+58-58)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll (+173-187)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll (+172-178)
- (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+405-501)
- (modified) llvm/test/CodeGen/AMDGPU/big_alu.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/bswap.ll (+13-5)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll (+214-428)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll (+214-428)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll (+214-428)
- (modified) llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll (+58-66)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll (+542-1095)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll (+548-1101)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll (+548-1101)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll (+556-1109)
- (modified) llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll (+88-96)
- (modified) llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll (+88-96)
- (modified) llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll (+1410-1456)
- (modified) llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll (+21-29)
- (modified) llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll (+4-5)
- (modified) llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll (+21-29)
- (modified) llvm/test/CodeGen/AMDGPU/fract-match.ll (+215-33)
- (modified) llvm/test/CodeGen/AMDGPU/freeze.ll (+21-22)
- (modified) llvm/test/CodeGen/AMDGPU/fshl-illegal-types.ll (+3-10)
- (modified) llvm/test/CodeGen/AMDGPU/function-esm2-prologue-epilogue.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll (+555-1108)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll (+559-1112)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll (+559-1112)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll (+557-1110)
- (modified) llvm/test/CodeGen/AMDGPU/idot4s.ll (+49-52)
- (modified) llvm/test/CodeGen/AMDGPU/idot4u.ll (+36-39)
- (modified) llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll (+88-40)
- (modified) llvm/test/CodeGen/AMDGPU/literals.ll (+47)
- (modified) llvm/test/CodeGen/AMDGPU/llc-pipeline.ll (+25)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll (+359)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll (+19-12)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll (+48-22)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll (+21-13)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll (+53-24)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll (+17-22)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll (+17-22)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll (+128-213)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (+29-14)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.round.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/load-input-fold.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll (+11-23)
- (modified) llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll (+20-38)
- (modified) llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll (+20-38)
- (modified) llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir (+3)
- (modified) llvm/test/CodeGen/AMDGPU/pv.ll (+74)
- (modified) llvm/test/CodeGen/AMDGPU/r600.private-memory.ll (+20)
- (modified) llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll (+8380)
- (modified) llvm/test/CodeGen/AMDGPU/scmp.ll (+28-41)
- (modified) llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll (+13-15)
- (modified) llvm/test/CodeGen/AMDGPU/ucmp.ll (+12-20)
- (modified) llvm/test/CodeGen/AMDGPU/urem-constant-i128.ll (+3-12)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll (+96-146)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll (+96-146)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 5faa478407c34..e4790ffeecf0d 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -2384,13 +2384,15 @@ let OtherPredicates = [HasPackedD16VMem,HasMTBUFInsts] in {
} // End HasPackedD16VMem,HasMTBUFInsts.
multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
- string opcode, ValueType memoryVt = vt> {
+ string opcode, ValueType memoryVt = vt, bit isTrue16 = false> {
defvar st = !if(!eq(memoryVt, vt), name, mtbuf_intrinsic_store<name, memoryVt>);
def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, 0, 0, (BUFSOffset i32:$soffset), timm:$offset,
timm:$format, timm:$auxiliary, 0),
- (!cast<MTBUF_Pseudo>(opcode # _OFFSET_exact) getVregSrcForVT<vt>.ret:$vdata, SReg_128:$rsrc, SCSrc_b32:$soffset,
+ (!cast<MTBUF_Pseudo>(opcode # _OFFSET_exact)
+ !if(isTrue16, (lo16_to_vgpr32 $vdata), (vt getVregSrcForVT<vt>.ret:$vdata)),
+ SReg_128:$rsrc, SCSrc_b32:$soffset,
timm:$offset, (as_i8timm $format),
(extract_cpol $auxiliary), (extract_swz $auxiliary))
>;
@@ -2398,7 +2400,9 @@ multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, i32:$vindex, 0, (BUFSOffset i32:$soffset), timm:$offset,
timm:$format, timm:$auxiliary, timm),
- (!cast<MTBUF_Pseudo>(opcode # _IDXEN_exact) getVregSrcForVT<vt>.ret:$vdata, VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset,
+ (!cast<MTBUF_Pseudo>(opcode # _IDXEN_exact)
+ !if(isTrue16, (lo16_to_vgpr32 $vdata), (vt getVregSrcForVT<vt>.ret:$vdata)),
+ VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset,
timm:$offset, (as_i8timm $format),
(extract_cpol $auxiliary), (extract_swz $auxiliary))
>;
@@ -2406,7 +2410,9 @@ multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
def : GCNPat<
(st vt:$vdata, v4i32:$rsrc, 0, i32:$voffset, (BUFSOffset i32:$soffset), timm:$offset,
timm:$format, timm:$auxiliary, 0),
- (!cast<MTBUF_Pseudo>(opcode # _OFFEN_exact) getVregSrcForVT<vt>.ret:$vdata, VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset,
+ (!cast<MTBUF_Pseudo>(opcode # _OFFEN_exact)
+ !if(isTrue16, (lo16_to_vgpr32 $vdata), (vt getVregSrcForVT<vt>.ret:$vdata)),
+ VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset,
timm:$offset, (as_i8timm $format),
(extract_cpol $auxiliary), (extract_swz $auxiliary))
>;
@@ -2415,7 +2421,7 @@ multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
(st vt:$vdata, v4i32:$rsrc, i32:$vindex, i32:$voffset, (BUFSOffset i32:$soffset),
timm:$offset, timm:$format, timm:$auxiliary, timm),
(!cast<MTBUF_Pseudo>(opcode # _BOTHEN_exact)
- getVregSrcForVT<vt>.ret:$vdata,
+ !if(isTrue16, (lo16_to_vgpr32 $vdata), (vt getVregSrcForVT<vt>.ret:$vdata)),
(REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset, (as_i8timm $format),
(extract_cpol $auxiliary), (extract_swz $auxiliary))
@@ -2423,11 +2429,11 @@ multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
}
multiclass MTBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
- string opcode, ValueType memoryVt = vt> {
+ string opcode, ValueType memoryVt = vt, bit isTrue16 = false> {
let SubtargetPredicate = HasUnrestrictedSOffset in {
- defm : MTBUF_StoreIntrinsicPat_Common<name, vt, opcode, memoryVt>;
+ defm : MTBUF_StoreIntrinsicPat_Common<name, vt, opcode, memoryVt, isTrue16>;
}
- defm : MTBUF_StoreIntrinsicPat_Common<name, vt, opcode # "_VBUFFER", memoryVt>;
+ defm : MTBUF_StoreIntrinsicPat_Common<name, vt, opcode # "_VBUFFER", memoryVt, isTrue16>;
}
let OtherPredicates = [HasMTBUFInsts] in {
@@ -2457,6 +2463,9 @@ let OtherPredicates = [HasUnpackedD16VMem,HasMTBUFInsts] in {
let OtherPredicates = [HasPackedD16VMem,HasMTBUFInsts] in {
foreach vt = Reg16Types.types in {
+ let True16Predicate = UseRealTrue16Insts in
+ defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, vt, "TBUFFER_STORE_FORMAT_D16_X", vt, /*isTrue16*/true>;
+ let True16Predicate = NotUseRealTrue16Insts in
defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, vt, "TBUFFER_STORE_FORMAT_D16_X">;
}
defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, i32, "TBUFFER_STORE_FORMAT_D16_X">;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 441098168f450..ba922d9902bfa 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3173,16 +3173,16 @@ def : GCNPat <
let True16Predicate = UseRealTrue16Insts in {
def : GCNPat <
(i16 (DivergentSextInreg<i1> i16:$src)),
- (V_BFE_I32_e64
+ (EXTRACT_SUBREG (V_BFE_I32_e64
(REG_SEQUENCE VGPR_32, VGPR_16:$src, lo16, (i16 (IMPLICIT_DEF)), hi16),
- (i32 0), (i32 1))
+ (i32 0), (i32 1)), lo16)
>;
def : GCNPat <
(i16 (DivergentSextInreg<i8> i16:$src)),
- (V_BFE_I32_e64
+ (EXTRACT_SUBREG (V_BFE_I32_e64
(REG_SEQUENCE VGPR_32, VGPR_16:$src, lo16, (i16 (IMPLICIT_DEF)), hi16),
- (i32 0), (i32 8))
+ (i32 0), (i32 8)) , lo16)
>;
}
@@ -3754,12 +3754,15 @@ def : GCNPat <
let True16Predicate = UseRealTrue16Insts in {
def : GCNPat <
(i16 (bswap i16:$a)),
- (EXTRACT_SUBREG (V_PERM_B32_e64 (i32 0), (COPY VGPR_16:$a), (S_MOV_B32 (i32 0x0c0c0001))), lo16)
+ (EXTRACT_SUBREG (V_PERM_B32_e64 (i32 0),
+ (REG_SEQUENCE VGPR_32, VGPR_16:$a, lo16, (i16 (IMPLICIT_DEF)), hi16),
+ (S_MOV_B32 (i32 0x0c0c0001))), lo16)
>;
def : GCNPat <
(i32 (zext (bswap i16:$a))),
- (V_PERM_B32_e64 (i32 0), (COPY VGPR_16:$a), (S_MOV_B32 (i32 0x0c0c0001)))
+ (V_PERM_B32_e64 (i32 0), (REG_SEQUENCE VGPR_32, $a, lo16, (IMPLICIT_DEF), hi16),
+ (S_MOV_B32 (i32 0x0c0c0001)))
>;
}
@@ -4012,7 +4015,8 @@ def : GCNPat <
let True16Predicate = UseRealTrue16Insts in {
def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 0), (i16 VGPR_16:$src1))),
- (v2i16 (V_LSHLREV_B32_e64 (i16 16), VGPR_16:$src1))
+ (v2i16 (V_LSHLREV_B32_e64 (i16 16),
+ (REG_SEQUENCE VGPR_32, $src1, lo16, (i16 (IMPLICIT_DEF)), hi16)))
>;
def : GCNPat <
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index bcf2ca6e8729e..f132d2efa13d7 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1393,6 +1393,13 @@ class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
$src)
>;
+class ZExt_i16_i1_Pat_t16 <SDNode ext> : GCNPat <
+ (i16 (ext i1:$src)),
+ (V_CNDMASK_B16_t16_e64 0/*src0mod*/, 0/*src0*/,
+ 0/*src1mod*/, 1/*src1*/,
+ $src)
+>;
+
let True16Predicate = NotUseRealTrue16Insts in {
def : GCNPat <
(and i16:$src0, i16:$src1),
@@ -1453,17 +1460,32 @@ defm : Arithmetic_i16_0Hi_Pats<cashr_rev_16, V_ASHRREV_I16_e64>;
} // End Predicates = [Has16BitInsts, isGFX8GFX9]
-let Predicates = [Has16BitInsts] in {
+let OtherPredicates = [Has16BitInsts] in {
+let True16Predicate = NotUseRealTrue16Insts in {
def : ZExt_i16_i1_Pat<zext>;
def : ZExt_i16_i1_Pat<anyext>;
+}
+let True16Predicate = UseRealTrue16Insts in {
+def : ZExt_i16_i1_Pat_t16<zext>;
+def : ZExt_i16_i1_Pat_t16<anyext>;
+}
+
+let True16Predicate = NotUseRealTrue16Insts in
def : GCNPat <
(i16 (sext i1:$src)),
(V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
/*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
>;
+let True16Predicate = UseRealTrue16Insts in
+def : GCNPat <
+ (i16 (sext i1:$src)),
+ (V_CNDMASK_B16_t16_e64 /*src0mod*/0, /*src0*/0,
+ /*src1mod*/0, /*src1*/-1, $src)
+>;
+
} // End Predicates = [Has16BitInsts]
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 05f47f696393b..73c5f5c55b056 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -1807,6 +1807,10 @@ let SubtargetPredicate = HasBF16ConversionInsts in {
def : GCNPat<(v2bf16 (build_vector (bf16 (bf16_fpround (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(bf16 (bf16_fpround (f32 (VOP3Mods f32:$src1, i32:$src1_modifiers)))))),
(V_CVT_PK_BF16_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1)>;
+ let True16Predicate = UseRealTrue16Insts in
+ def : GCNPat<(bf16 (bf16_fpround (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
+ (EXTRACT_SUBREG (V_CVT_PK_BF16_F32_e64 $src0_modifiers, $src0, 0, (f32 (IMPLICIT_DEF))), lo16)>;
+ let True16Predicate = NotUseRealTrue16Insts in
def : GCNPat<(bf16 (bf16_fpround (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(V_CVT_PK_BF16_F32_e64 $src0_modifiers, $src0, 0, (f32 (IMPLICIT_DEF)))>;
}
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index a379785616c6c..f52d014e214bd 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -2406,8 +2406,8 @@ class ClassPat<Instruction inst, ValueType vt> : GCNPat <
>;
class ClassPat_t16<Instruction inst, ValueType vt> : GCNPat <
- (i1 (is_fpclass (vt (VOP3ModsNonCanonicalizing vt:$src0, i32:$src0_mods)), (i32 timm:$mask))),
- (inst i32:$src0_mods, vt:$src0, SRCMODS.NONE, (V_MOV_B32_e32 timm:$mask))
+ (i1 (is_fpclass (vt (VOP3ModsNonCanonicalizing vt:$src0, i32:$src0_mods)), (i16 timm:$mask))),
+ (inst i32:$src0_mods, vt:$src0, SRCMODS.NONE, (V_MOV_B16_t16_e64 0, timm:$mask, 0))
>;
def : ClassPat<V_CMP_CLASS_F16_e64, f16> {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
index 08be2ad4a8f26..dbddcd31730fa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
@@ -411,7 +411,7 @@ define amdgpu_ps i16 @s_bswap_i16(i16 inreg %src) {
;
; GFX11-LABEL: s_bswap_i16:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
@@ -517,11 +517,18 @@ define i32 @v_bswap_i16_zext_to_i32(i16 %src) {
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_bswap_i16_zext_to_i32:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_bswap_i16_zext_to_i32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bswap_i16_zext_to_i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
+; GFX11-NEXT: v_cvt_u32_u16_e32 v0, v0.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
%zext = zext i16 %bswap to i32
ret i32 %zext
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index 991071ac55bc5..46f5b6f207218 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -2936,85 +2936,79 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v7, v8 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_cndmask_b32 v2, v7, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/219733
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