[llvm-branch-commits] [llvm] aedf7d6 - [X86] LowerAVXCONCAT_VECTORS - fix some clang-format messiness. NFC. (#218504)

[Tobias Hieta via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2026-08-28T11:05:19+02:00
New Revision: aedf7d6749aa2e3f342584cc0954b9a52e158aaa

URL: https://github.com/llvm/llvm-project/commit/aedf7d6749aa2e3f342584cc0954b9a52e158aaa
DIFF: https://github.com/llvm/llvm-project/commit/aedf7d6749aa2e3f342584cc0954b9a52e158aaa.diff

LOG: [X86] LowerAVXCONCAT_VECTORS - fix some clang-format messiness. NFC. (#218504)

Bad indentation and missing braces

Pulled out of #218381 to simplify functional diff

(cherry picked from commit a6eb1e1e75a2d29f8f458c6ee513ae5b030ff9a0)

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1183ad64f1554..8f3b463a0c51d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -9899,17 +9899,16 @@ static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, const SDLoc &dl,
     if (SubVec.isUndef())
       continue;
     if (ISD::isFreezeUndef(SubVec.getNode())) {
-        // If the freeze(undef) has multiple uses then we must fold to zero.
-        if (SubVec.hasOneUse()) {
-          ++NumFreezeUndef;
-        } else {
-          ++NumZero;
-          Undefs.insert(SubVec);
-        }
-    }
-    else if (ISD::isBuildVectorAllZeros(SubVec.getNode()))
+      // If the freeze(undef) has multiple uses then we must fold to zero.
+      if (SubVec.hasOneUse()) {
+        ++NumFreezeUndef;
+      } else {
+        ++NumZero;
+        Undefs.insert(SubVec);
+      }
+    } else if (ISD::isBuildVectorAllZeros(SubVec.getNode())) {
       ++NumZero;
-    else {
+    } else {
       assert(i < sizeof(NonZeros) * CHAR_BIT); // Ensure the shift is in range.
       NonZeros |= 1 << i;
       ++NumNonZero;
@@ -9921,9 +9920,9 @@ static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, const SDLoc &dl,
     MVT HalfVT = ResVT.getHalfNumVectorElementsVT();
     ArrayRef<SDUse> Ops = Op->ops();
     SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
-                             Ops.slice(0, NumOperands/2));
+                             Ops.slice(0, NumOperands / 2));
     SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
-                             Ops.slice(NumOperands/2));
+                             Ops.slice(NumOperands / 2));
     return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
   }