[llvm-branch-commits] [llvm] [AMDGPU][GIsel][NPM] Port "AMDGPURegBankLegalize" to NPM (PR #217322)
Vikram Hegde via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Aug 25 05:05:28 PDT 2026
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/217322
>From 562442237911c391f33ffb58b51d2232bfa0171d Mon Sep 17 00:00:00 2001
From: vikhegde <vikram.hegde at amd.com>
Date: Wed, 19 Aug 2026 17:06:49 +0530
Subject: [PATCH] [AMDGPU][GIsel][NPM] Port "AMDGPURegBankLegalize" to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 24 ++++++-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 2 +-
.../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 67 ++++++++++++++-----
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 4 +-
.../AMDGPU/GlobalISel/regbankselect-add.mir | 1 +
.../AMDGPU/GlobalISel/regbankselect-load.mir | 3 +
.../AMDGPU/GlobalISel/regbankselect-mui.mir | 1 +
7 files changed, 79 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 10e35050c2464..ec510fa2ba67e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -62,7 +62,25 @@ class AMDGPURegBankSelectPass
return MachineFunctionProperties().setRegBankSelected();
}
};
-FunctionPass *createAMDGPURegBankLegalizePass();
+FunctionPass *createAMDGPURegBankLegalizeLegacyPass();
+
+class AMDGPURegBankLegalizePass
+ : public RequiredPassInfoMixin<AMDGPURegBankLegalizePass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties()
+ .setIsSSA()
+ .setLegalized()
+ .setRegBankSelected();
+ }
+
+ MachineFunctionProperties getClearedProperties() const {
+ return MachineFunctionProperties().setNoPHIs();
+ }
+};
// SI Passes
FunctionPass *createGCNDPPCombinePass();
@@ -246,8 +264,8 @@ extern char &AMDGPUGlobalISelDivergenceLoweringLegacyID;
void initializeAMDGPURegBankSelectLegacyPass(PassRegistry &);
extern char &AMDGPURegBankSelectLegacyID;
-void initializeAMDGPURegBankLegalizePass(PassRegistry &);
-extern char &AMDGPURegBankLegalizeID;
+void initializeAMDGPURegBankLegalizeLegacyPass(PassRegistry &);
+extern char &AMDGPURegBankLegalizeLegacyID;
void initializeAMDGPUMarkLastScratchLoadLegacyPass(PassRegistry &);
extern char &AMDGPUMarkLastScratchLoadID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 9164a5f92fbc7..00e27ed416a50 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -131,6 +131,7 @@ MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass()
MACHINE_FUNCTION_PASS("amdgpu-prelegalizer-combiner",
AMDGPUPreLegalizerCombinerPass())
MACHINE_FUNCTION_PASS("amdgpu-reg-bank-select", AMDGPURegBankSelectPass())
+MACHINE_FUNCTION_PASS("amdgpu-reg-bank-legalize", AMDGPURegBankLegalizePass())
MACHINE_FUNCTION_PASS("amdgpu-preload-kern-arg-prolog", AMDGPUPreloadKernArgPrologPass())
MACHINE_FUNCTION_PASS("amdgpu-prepare-agpr-alloc", AMDGPUPrepareAGPRAllocPass())
MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass())
@@ -167,7 +168,6 @@ MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass())
// Global ISel passes
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-postlegalizer-combiner",
AMDGPUPostLegalizerCombinerPass())
-DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbanklegalize", AMDGPURegBankLegalizePass())
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbank-combiner", AMDGPURegBankCombinerPass())
#undef DUMMY_MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index 19ba2f5ca6fb5..754230ce45729 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -27,7 +27,9 @@
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"
@@ -47,12 +49,12 @@ m_GAMDGPUReadAnyLane(const SrcTy &Src) {
return UnaryOp_match<SrcTy, AMDGPU::G_AMDGPU_READANYLANE>(Src);
}
-class AMDGPURegBankLegalize : public MachineFunctionPass {
+class AMDGPURegBankLegalizeLegacy : public MachineFunctionPass {
public:
static char ID;
public:
- AMDGPURegBankLegalize() : MachineFunctionPass(ID) {}
+ AMDGPURegBankLegalizeLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
@@ -77,21 +79,21 @@ class AMDGPURegBankLegalize : public MachineFunctionPass {
} // End anonymous namespace.
-INITIALIZE_PASS_BEGIN(AMDGPURegBankLegalize, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(AMDGPURegBankLegalizeLegacy, DEBUG_TYPE,
"AMDGPU Register Bank Legalize", false, false)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineUniformityAnalysisPass)
INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
-INITIALIZE_PASS_END(AMDGPURegBankLegalize, DEBUG_TYPE,
+INITIALIZE_PASS_END(AMDGPURegBankLegalizeLegacy, DEBUG_TYPE,
"AMDGPU Register Bank Legalize", false, false)
-char AMDGPURegBankLegalize::ID = 0;
+char AMDGPURegBankLegalizeLegacy::ID = 0;
-char &llvm::AMDGPURegBankLegalizeID = AMDGPURegBankLegalize::ID;
+char &llvm::AMDGPURegBankLegalizeLegacyID = AMDGPURegBankLegalizeLegacy::ID;
-FunctionPass *llvm::createAMDGPURegBankLegalizePass() {
- return new AMDGPURegBankLegalize();
+FunctionPass *llvm::createAMDGPURegBankLegalizeLegacyPass() {
+ return new AMDGPURegBankLegalizeLegacy();
}
const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
@@ -416,15 +418,19 @@ void AMDGPURegBankLegalizeCombiner::tryCombineS1AnyExt(MachineInstr &MI) {
return {};
}
-bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
+static bool
+runRegBankLegalize(MachineFunction &MF,
+ function_ref<GISelCSEInfo *()> GetCSEInfo,
+ function_ref<const MachineUniformityInfo *()> GetMUI,
+ function_ref<GISelValueTracking *()> GetVT) {
if (MF.getProperties().hasFailedISel())
return false;
+ GISelCSEInfo &CSEInfo = *GetCSEInfo();
+ const MachineUniformityInfo &MUI = *GetMUI();
+ GISelValueTracking &VT = *GetVT();
+
// Setup the instruction builder with CSE.
- const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
- GISelCSEAnalysisWrapper &Wrapper =
- getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
- GISelCSEInfo &CSEInfo = Wrapper.get(TPC.getCSEConfig());
GISelObserverWrapper Observer;
Observer.addObserver(&CSEInfo);
@@ -438,10 +444,6 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
MachineRegisterInfo &MRI = MF.getRegInfo();
const RegisterBankInfo &RBI = *ST.getRegBankInfo();
- const MachineUniformityInfo &MUI =
- getAnalysis<MachineUniformityAnalysisPass>().getUniformityInfo();
- GISelValueTracking &VT =
- getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
// RegBankLegalizeRules is initialized with assigning sets of IDs to opcodes.
const RegBankLegalizeRules &RBLRules = getRules(ST, MRI);
@@ -509,3 +511,34 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
return true;
}
+
+bool AMDGPURegBankLegalizeLegacy::runOnMachineFunction(MachineFunction &MF) {
+ return runRegBankLegalize(
+ MF,
+ [&]() {
+ GISelCSEAnalysisWrapper &Wrapper =
+ getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
+ return &Wrapper.get(getAnalysis<TargetPassConfig>().getCSEConfig());
+ },
+ [&]() {
+ return &getAnalysis<MachineUniformityAnalysisPass>()
+ .getUniformityInfo();
+ },
+ [&]() {
+ return &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
+ });
+}
+
+PreservedAnalyses
+AMDGPURegBankLegalizePass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+
+ if (!runRegBankLegalize(
+ MF, [&]() { return MFAM.getResult<GISelCSEAnalysis>(MF).get(); },
+ [&]() { return &MFAM.getResult<MachineUniformityAnalysis>(MF); },
+ [&]() { return &MFAM.getResult<GISelValueTrackingAnalysis>(MF); }))
+ return PreservedAnalyses::all();
+
+ return getMachineFunctionPassPreservedAnalyses();
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 716f4f2a5de6c..e5a681b95f88e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -689,7 +689,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeSILowerI1CopiesLegacyPass(*PR);
initializeAMDGPUGlobalISelDivergenceLoweringLegacyPass(*PR);
initializeAMDGPURegBankSelectLegacyPass(*PR);
- initializeAMDGPURegBankLegalizePass(*PR);
+ initializeAMDGPURegBankLegalizeLegacyPass(*PR);
initializeSILowerWWMCopiesLegacyPass(*PR);
initializeAMDGPUMarkLastScratchLoadLegacyPass(*PR);
initializeSILowerSGPRSpillsLegacyPass(*PR);
@@ -1805,7 +1805,7 @@ void GCNPassConfig::addPreRegBankSelect() {
bool GCNPassConfig::addRegBankSelect() {
addPass(createAMDGPURegBankSelectLegacyPass());
- addPass(createAMDGPURegBankLegalizePass());
+ addPass(createAMDGPURegBankLegalizeLegacyPass());
return false;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
index 77a614d89e849..9a278fa76e61d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-each -o - | FileCheck %s
---
name: add_s16_ss
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
index e5b81a7d12ba4..ffe2016c82c14 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
@@ -1,7 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu7.01-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX7
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu7.01-amd-amdhsa -passes='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-each -o - | FileCheck %s -check-prefixes=GCN,GFX7
# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.00-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX12
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.00-amd-amdhsa -passes='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-each -o - | FileCheck %s -check-prefixes=GCN,GFX12
# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.50-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s -check-prefixes=GCN,GFX12
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.50-amd-amdhsa -passes='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -verify-each %s -o - | FileCheck %s -check-prefixes=GCN,GFX12
--- |
define amdgpu_kernel void @load_global_v8i32_non_uniform(ptr addrspace(1) %in) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
index 42427e9e38a83..8b92c3ca2a675 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
@@ -1,6 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS
# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS
+# RUN: llc -mtriple=amdgpu10.10 -passes='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-each -o - | FileCheck %s -check-prefixes=NEW_RBS
---
name: uniform_in_vgpr
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