[llvm-branch-commits] [RISCV] Attach VLMAX range attribute for vsetvli/vsetvlimax in InstCombine (PR #218652)
Ramkumar Ramachandra via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Aug 25 03:27:21 PDT 2026
================
@@ -3752,6 +3752,58 @@ bool RISCVTTIImpl::shouldCopyAttributeWhenOutliningFrom(
std::optional<Instruction *>
RISCVTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
+ // Attach a range return attribute describing the result of vsetvli/vsetvlimax
+ // so generic value analyses can reason about it. The verifier guarantees an
+ // XLen result and constant VSEW/VLMUL encoding a valid vtype, so no defensive
+ // validation is needed here.
+ if (II.getIntrinsicID() == Intrinsic::riscv_vsetvli ||
+ II.getIntrinsicID() == Intrinsic::riscv_vsetvlimax) {
+ bool HasAVL = II.getIntrinsicID() == Intrinsic::riscv_vsetvli;
+ unsigned Offset = HasAVL ? 1 : 0;
+ unsigned Width = II.getType()->getScalarSizeInBits();
+ ConstantRange VLenRange(APInt(Width, ST->getRealMinVLen()),
+ APInt(Width, ST->getRealMaxVLen()) + 1);
+
+ uint64_t VSEW = cast<ConstantInt>(II.getArgOperand(Offset))->getZExtValue();
+ auto VLMUL = static_cast<RISCVVType::VLMUL>(
+ cast<ConstantInt>(II.getArgOperand(Offset + 1))->getZExtValue());
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artagnon wrote:
Will the zext value overflow 64 bits?
https://github.com/llvm/llvm-project/pull/218652
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