[llvm-branch-commits] [llvm] release/23.x: [AArch64] Do not allow anyext load in isEquivalentMaskless (#216288) (PR #216937)
Douglas Yung via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Aug 24 05:13:36 PDT 2026
https://github.com/dyung updated https://github.com/llvm/llvm-project/pull/216937
>From f54c0c47aa71103da3550ebb8b515ca204b9d38e Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Tue, 18 Aug 2026 08:11:59 +0100
Subject: [PATCH] [AArch64] Do not allow anyext load in isEquivalentMaskless
(#216288)
isEquivalentMaskless tries to prove that the `and` in `cmp(and(add(x,
C1), 0xff), C2)` is redundant and can be removed, providing that the
input x is know to be a sext or zext. AFAICT it should not apply to
anyext, which could take any value.
Fixes #215839
(cherry picked from commit 90c0c675b463b7aaace2c9f90dfe7fc4f851678c)
---
.../Target/AArch64/AArch64ISelLowering.cpp | 3 +
llvm/test/CodeGen/AArch64/pr215839.ll | 152 ++++++++++++++++++
2 files changed, 155 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/pr215839.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 507817e29ce2b..14488c04c25f4 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -28010,6 +28010,9 @@ bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
|| (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
+ if (LoadNode->getExtensionType() != ISD::SEXTLOAD &&
+ LoadNode->getExtensionType() != ISD::ZEXTLOAD)
+ return false;
ExtType = LoadNode->getExtensionType();
return true;
}
diff --git a/llvm/test/CodeGen/AArch64/pr215839.ll b/llvm/test/CodeGen/AArch64/pr215839.ll
new file mode 100644
index 0000000000000..2671057f2166e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr215839.ll
@@ -0,0 +1,152 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
+
+define i32 @reduced(<4 x i16> %vecins, i32 %conv) {
+; CHECK-LABEL: reduced:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: add x8, sp, #8
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: mov w9, #26065 // =0x65d1
+; CHECK-NEXT: mov w10, #9878 // =0x2696
+; CHECK-NEXT: bfi x8, x0, #1, #2
+; CHECK-NEXT: .LBB0_1: // %lbl_b59
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: str d0, [sp, #8]
+; CHECK-NEXT: ldrh w11, [x8]
+; CHECK-NEXT: add w11, w11, #1
+; CHECK-NEXT: and w11, w11, #0xffff
+; CHECK-NEXT: cmp w11, w9
+; CHECK-NEXT: ccmp w11, w10, #4, ne
+; CHECK-NEXT: b.ne .LBB0_1
+; CHECK-NEXT: // %bb.2: // %sw.bb
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: add sp, sp, #16
+; CHECK-NEXT: ret
+entry:
+ br label %lbl_b59
+
+lbl_b59: ; preds = %lbl_b59, %entry
+ %vecext = extractelement <4 x i16> %vecins, i32 %conv
+ %add4 = add i16 %vecext, 1
+ switch i16 %add4, label %lbl_b59 [
+ i16 9878, label %sw.bb
+ i16 26065, label %sw.bb
+ ]
+
+sw.bb: ; preds = %lbl_b59, %lbl_b59
+ ret i32 0
+}
+
+
+ at g1 = dso_local local_unnamed_addr global i32 1662431956, align 4
+ at g30 = dso_local local_unnamed_addr global i16 0, align 4
+ at g19 = dso_local local_unnamed_addr global i8 0, align 4
+ at f29_c9 = dso_local local_unnamed_addr global i8 0, align 1
+
+define i32 @original() {
+; CHECK-LABEL: original:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: adrp x8, g1
+; CHECK-NEXT: mov x10, #4611686018427387904 // =0x4000000000000000
+; CHECK-NEXT: mov w14, #24726 // =0x6096
+; CHECK-NEXT: ldr w8, [x8, :lo12:g1]
+; CHECK-NEXT: mov w11, #26065 // =0x65d1
+; CHECK-NEXT: mov w12, #9878 // =0x2696
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: lsl x9, x8, #31
+; CHECK-NEXT: cmp x8, x9, asr #31
+; CHECK-NEXT: add x8, x9, x10
+; CHECK-NEXT: mov w9, #860684288 // =0x334d0000
+; CHECK-NEXT: fmov d0, x9
+; CHECK-NEXT: ccmp x8, #0, #8, eq
+; CHECK-NEXT: adrp x8, g19
+; CHECK-NEXT: cset w9, mi
+; CHECK-NEXT: mov w10, #-28618 // =0xffff9036
+; CHECK-NEXT: .LBB1_1: // %lbl_b59
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ext v1.8b, v0.8b, v0.8b, #6
+; CHECK-NEXT: trn1 v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: fmov x13, d0
+; CHECK-NEXT: lsr x13, x13, #61
+; CHECK-NEXT: cmp x13, #1
+; CHECK-NEXT: rev16 w13, w14
+; CHECK-NEXT: b.ne .LBB1_4
+; CHECK-NEXT: // %bb.2: // %lbl_br68
+; CHECK-NEXT: // in Loop: Header=BB1_1 Depth=1
+; CHECK-NEXT: mov v0.h[0], w13
+; CHECK-NEXT: and w14, w13, #0xffff
+; CHECK-NEXT: cmp w9, #0
+; CHECK-NEXT: csel w14, wzr, w14, ne
+; CHECK-NEXT: add x15, sp, #8
+; CHECK-NEXT: bfi x15, x14, #1, #2
+; CHECK-NEXT: str d0, [sp, #8]
+; CHECK-NEXT: ldrsh w15, [x15]
+; CHECK-NEXT: add w14, w15, w10
+; CHECK-NEXT: cmp w15, #1
+; CHECK-NEXT: and w15, w14, #0xffff
+; CHECK-NEXT: cset w16, lt
+; CHECK-NEXT: cmp w15, w11
+; CHECK-NEXT: strb w16, [x8, :lo12:g19]
+; CHECK-NEXT: ccmp w15, w12, #4, ne
+; CHECK-NEXT: b.ne .LBB1_1
+; CHECK-NEXT: // %bb.3: // %sw.bb
+; CHECK-NEXT: adrp x8, g30
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: strh w13, [x8, :lo12:g30]
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB1_4: // %if.end
+; CHECK-NEXT: adrp x8, g30
+; CHECK-NEXT: strh w13, [x8, :lo12:g30]
+; CHECK-NEXT: bl abort
+entry:
+ %0 = load i32, ptr @g1, align 4
+ %1 = zext i32 %0 to i33
+ %2 = tail call { i33, i1 } @llvm.sadd.with.overflow.i33(i33 %1, i33 %1)
+ %3 = extractvalue { i33, i1 } %2, 1
+ %4 = extractvalue { i33, i1 } %2, 0
+ %5 = add i33 %4, 2147483648
+ %6 = icmp slt i33 %5, 0
+ %7 = or i1 %3, %6
+ br label %lbl_b59
+
+lbl_b59: ; preds = %lbl_br68, %entry
+ %v10.0 = phi i16 [ 24726, %entry ], [ %add, %lbl_br68 ]
+ %bc4.0 = phi <4 x i16> [ <i16 0, i16 13133, i16 0, i16 0>, %entry ], [ %vecins, %lbl_br68 ]
+ %8 = tail call i16 @llvm.bswap.i16(i16 %v10.0)
+ %shuffle = shufflevector <4 x i16> %bc4.0, <4 x i16> poison, <4 x i32> <i32 0, i32 3, i32 2, i32 1>
+ %9 = bitcast <4 x i16> %shuffle to i64
+ %10 = and i64 %9, -2305843009213693952
+ %cmp = icmp eq i64 %10, 2305843009213693952
+ br i1 %cmp, label %lbl_br68, label %if.end
+
+if.end: ; preds = %lbl_b59
+ store i16 %8, ptr @g30, align 4
+ tail call void @abort() #3
+ unreachable
+
+lbl_br68: ; preds = %lbl_b59
+ %vecins = insertelement <4 x i16> %shuffle, i16 %8, i64 0
+ %conv = zext i16 %8 to i32
+ %cond = select i1 %7, i32 0, i32 %conv
+ %vecext = extractelement <4 x i16> %vecins, i32 %cond
+ %cmp2 = icmp slt i16 %vecext, 1
+ %storedv = zext i1 %cmp2 to i8
+ store i8 %storedv, ptr @g19, align 4
+ %add = add i16 %vecext, -28618
+ switch i16 %add, label %lbl_b59 [
+ i16 9878, label %sw.bb
+ i16 26065, label %sw.bb
+ ]
+
+sw.bb: ; preds = %lbl_br68, %lbl_br68
+ store i16 %8, ptr @g30, align 4
+ ret i32 0
+}
+
+declare void @abort()
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