[llvm-branch-commits] [llvm] [MIR][AMDGPU] Serialize register allocation anti-hints (PR #218073)

[Lukas Sommer via llvm-branch-commits]

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@@ -772,6 +772,22 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
                          FlagStringValue.Value + "'");
       Info.Flags |= FlagValue;
     }
+    if (!VReg.AntiHints.empty() && Info.Kind != VRegInfo::NORMAL)
+      return error(VReg.AntiHints.front().SourceRange.Start,
+                   Twine("anti-hints can only be set for normal vregs"));
+
+    for (const auto &AntiHintValue : VReg.AntiHints) {
+      Register AntiHintReg;
+      if (parseRegisterReference(PFS, AntiHintReg, AntiHintValue.Value, Error))
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sommerlukas wrote:

Does this support named virtual registers? Do we want to support them? 

https://github.com/llvm/llvm-project/pull/218073