[llvm-branch-commits] [llvm] [DAG] Remove trivial VP SDNodes. NFC (PR #217866)
Luke Lau via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Aug 21 19:15:17 PDT 2026
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/217866
>From f29947179745657e783719fd8569b0b73d40e8cd Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Fri, 21 Aug 2026 17:30:01 +0800
Subject: [PATCH] [DAG] Remove trivial VP SDNodes. NFC
This removes the codegen parts of the trivial VP intrinsics. It's quite far reaching, but the general categories of code removed are:
- Removing definitions from VPIntrinsics.def
- Legalization and expansion code
- MatchContext used to match over both VP and non-VP nodes
- Some dead DAGCombines and folds in SelectionDAGBuilder
There are still more things to be cleaned up after this, e.g. removing more of the VPIntrinsic class hierarchy, removing ExpandVectorPredication/moving expansion into other places, removing MatchContext from SDPatternMatch
---
llvm/include/llvm/CodeGen/SDPatternMatch.h | 2 +
llvm/include/llvm/CodeGen/SelectionDAG.h | 37 --
llvm/include/llvm/CodeGen/TargetLowering.h | 50 +--
llvm/include/llvm/IR/VPIntrinsics.def | 343 +----------------
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 71 +---
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 44 +--
.../SelectionDAG/LegalizeIntegerTypes.cpp | 331 +++-------------
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 5 -
.../SelectionDAG/LegalizeTypesGeneric.cpp | 2 +-
.../SelectionDAG/LegalizeVectorOps.cpp | 224 +----------
.../SelectionDAG/LegalizeVectorTypes.cpp | 363 ++++--------------
llvm/lib/CodeGen/SelectionDAG/MatchContext.h | 182 ---------
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 57 ---
.../SelectionDAG/SelectionDAGBuilder.cpp | 58 ---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 342 +----------------
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 4 -
.../CodeGen/SelectionDAGPatternMatchTest.cpp | 89 -----
17 files changed, 189 insertions(+), 2015 deletions(-)
delete mode 100644 llvm/lib/CodeGen/SelectionDAG/MatchContext.h
diff --git a/llvm/include/llvm/CodeGen/SDPatternMatch.h b/llvm/include/llvm/CodeGen/SDPatternMatch.h
index 1affc9a1f6b49..18fa8ef12e730 100644
--- a/llvm/include/llvm/CodeGen/SDPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/SDPatternMatch.h
@@ -32,6 +32,8 @@ namespace SDPatternMatch {
/// a certain context. For instance, `m_SpecificOpc(ISD::ADD)` matches plain ADD
/// nodes in normal circumstances, but matches VP_ADD nodes under a custom
/// VPMatchContext. This design is meant to facilitate code / pattern reusing.
+/// TODO: Remove now that we don't need to match over VP nodes.
+
class BasicMatchContext {
const SelectionDAG *DAG;
const TargetLowering *TLI;
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index e2ad79c4ca931..e1d3548816883 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1092,11 +1092,6 @@ class SelectionDAG {
/// value assuming it was the smaller SrcTy value.
LLVM_ABI SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);
- /// Return the expression required to zero extend the Op
- /// value assuming it was the smaller SrcTy value.
- LLVM_ABI SDValue getVPZeroExtendInReg(SDValue Op, SDValue Mask, SDValue EVL,
- const SDLoc &DL, EVT VT);
-
/// Convert Op, which must be of integer type, to the integer type VT, by
/// either truncating it or performing either zero or sign extension as
/// appropriate extension for the pointer's semantics.
@@ -1122,26 +1117,6 @@ class SelectionDAG {
/// Create a logical NOT operation as (XOR Val, BooleanOne).
LLVM_ABI SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT);
- /// Create a vector-predicated logical NOT operation as (VP_XOR Val,
- /// BooleanOne, Mask, EVL).
- LLVM_ABI SDValue getVPLogicalNOT(const SDLoc &DL, SDValue Val, SDValue Mask,
- SDValue EVL, EVT VT);
-
- /// Convert a vector-predicated Op, which must be an integer vector, to the
- /// vector-type VT, by performing either vector-predicated zext or truncating
- /// it. The Op will be returned as-is if Op and VT are vectors containing
- /// integer with same width.
- LLVM_ABI SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op,
- SDValue Mask, SDValue EVL);
-
- /// Convert a vector-predicated Op, which must be of integer type, to the
- /// vector-type integer type VT, by either truncating it or performing either
- /// vector-predicated zero or sign extension as appropriate extension for the
- /// pointer's semantics. This function just redirects to getVPZExtOrTrunc
- /// right now.
- LLVM_ABI SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op,
- SDValue Mask, SDValue EVL);
-
/// Returns sum of the base pointer and offset.
/// Unlike getObjectPtrOffset this does not set NoUnsignedWrap and InBounds by
/// default.
@@ -1395,18 +1370,6 @@ class SelectionDAG {
return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Flags);
}
- /// Helper function to make it easier to build VP_SETCCs if you just have an
- /// ISD::CondCode instead of an SDValue.
- SDValue getSetCCVP(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS,
- ISD::CondCode Cond, SDValue Mask, SDValue EVL) {
- assert(LHS.getValueType().isVector() && RHS.getValueType().isVector() &&
- "Cannot compare scalars");
- assert(Cond != ISD::SETCC_INVALID &&
- "Cannot create a setCC of an invalid node.");
- return getNode(ISD::VP_SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Mask,
- EVL);
- }
-
/// Helper function to make it easier to build Select's if you just have
/// operands and don't want to check for vector.
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS,
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index a91b575dc82d2..4df2e674f2ef4 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -476,7 +476,7 @@ class LLVM_ABI TargetLoweringBase {
}
/// Returns the type to be used for the EVL/AVL operand of VP nodes:
- /// ISD::VP_ADD, ISD::VP_SUB, etc. It must be a legal scalar integer type,
+ /// ISD::VP_UDIV, ISD::VP_SDIV, etc. It must be a legal scalar integer type,
/// and must be at least as large as i32. The EVL is implicitly zero-extended
/// to any larger type.
virtual MVT getVPExplicitVectorLengthTy() const { return MVT::i32; }
@@ -3673,10 +3673,6 @@ class LLVM_ABI TargetLoweringBase {
if (isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, ToVT))
return ISD::STRICT_FP_TO_SINT;
break;
- case ISD::VP_FP_TO_UINT:
- if (isOperationLegalOrCustom(ISD::VP_FP_TO_SINT, ToVT))
- return ISD::VP_FP_TO_SINT;
- break;
default:
break;
}
@@ -5770,21 +5766,12 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// \returns The expansion result or SDValue() if it fails.
SDValue expandCTPOP(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_CTPOP nodes.
- /// \returns The expansion result or SDValue() if it fails.
- SDValue expandVPCTPOP(SDNode *N, SelectionDAG &DAG) const;
-
/// Expand CTLZ/CTLZ_ZERO_POISON nodes. Expands vector/scalar CTLZ nodes,
/// vector nodes can only succeed if all operations are legal/custom.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandCTLZ(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_CTLZ/VP_CTLZ_ZERO_POISON nodes.
- /// \param N Node to expand
- /// \returns The expansion result or SDValue() if it fails.
- SDValue expandVPCTLZ(SDNode *N, SelectionDAG &DAG) const;
-
/// Expand CTLS (count leading sign bits) nodes.
/// CTLS(x) = CTLZ(OR(SHL(XOR(x, SRA(x, BW-1)), 1), 1))
/// \param N Node to expand
@@ -5803,11 +5790,6 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// \returns The expansion result or SDValue() if it fails.
SDValue expandCTTZ(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_CTTZ/VP_CTTZ_ZERO_POISON nodes.
- /// \param N Node to expand
- /// \returns The expansion result or SDValue() if it fails.
- SDValue expandVPCTTZ(SDNode *N, SelectionDAG &DAG) const;
-
/// Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_POISON nodes.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
@@ -5853,22 +5835,12 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// \returns The expansion result or SDValue() if it fails.
SDValue expandBSWAP(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_BSWAP nodes. Expands VP_BSWAP nodes with
- /// i16/i32/i64 scalar types. Returns SDValue() if expand fails. \param N Node
- /// to expand \returns The expansion result or SDValue() if it fails.
- SDValue expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const;
-
/// Expand BITREVERSE nodes. Expands scalar/vector BITREVERSE nodes.
/// Returns SDValue() if expand fails.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_BITREVERSE nodes. Expands VP_BITREVERSE nodes with
- /// i8/i16/i32/i64 scalar types. \param N Node to expand \returns The
- /// expansion result or SDValue() if it fails.
- SDValue expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const;
-
/// Turn load of vector type into a load of the individual elements.
/// \param LD load to expand
/// \returns BUILD_VECTOR and TokenFactor nodes.
@@ -6030,32 +6002,30 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
SmallVectorImpl<SDValue> &Results,
std::optional<unsigned> CallRetResNo = {}) const;
- /// Legalize a SETCC or VP_SETCC with given LHS and RHS and condition code CC
- /// on the current target. A VP_SETCC will additionally be given a Mask
- /// and/or EVL not equal to SDValue().
+ /// Legalize a SETCC with given LHS and RHS and condition code CC
+ /// on the current target.
///
/// If the SETCC has been legalized using AND / OR, then the legalized node
/// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
- /// will be set to false. This will also hold if the VP_SETCC has been
- /// legalized using VP_AND / VP_OR.
+ /// will be set to false.
///
- /// If the SETCC / VP_SETCC has been legalized by using
+ /// If the SETCC has been legalized by using
/// getSetCCSwappedOperands(), then the values of LHS and RHS will be
/// swapped, CC will be set to the new condition, and NeedInvert will be set
/// to false.
///
- /// If the SETCC / VP_SETCC has been legalized using the inverse condcode,
+ /// If the SETCC has been legalized using the inverse condcode,
/// then LHS and RHS will be unchanged, CC will set to the inverted condcode,
/// and NeedInvert will be set to true. The caller must invert the result of
/// the SETCC with SelectionDAG::getLogicalNOT() or take equivalent action to
/// swap the effect of a true/false result.
///
- /// \returns true if the SETCC / VP_SETCC has been legalized, false if it
+ /// \returns true if the SETCC has been legalized, false if it
/// hasn't.
bool LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS,
- SDValue &RHS, SDValue &CC, SDValue Mask,
- SDValue EVL, bool &NeedInvert, const SDLoc &dl,
- SDValue &Chain, bool IsSignaling = false) const;
+ SDValue &RHS, SDValue &CC, bool &NeedInvert,
+ const SDLoc &dl, SDValue &Chain,
+ bool IsSignaling = false) const;
//===--------------------------------------------------------------------===//
// Instruction Emitting Hooks
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index 669343f5c2e5c..056e8a758d9cc 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -138,24 +138,6 @@
VP_PROPERTY_BINARYOP \
END_REGISTER_VP_SDNODE(VPSD)
-// llvm.vp.add(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_add, VP_ADD, Add, ADD)
-
-// llvm.vp.and(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_and, VP_AND, And, AND)
-
-// llvm.vp.ashr(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_ashr, VP_SRA, AShr, SRA)
-
-// llvm.vp.lshr(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_lshr, VP_SRL, LShr, SRL)
-
-// llvm.vp.mul(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_mul, VP_MUL, Mul, MUL)
-
-// llvm.vp.or(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_or, VP_OR, Or, OR)
-
// llvm.vp.sdiv(x,y,mask,vlen)
BEGIN_REGISTER_VP_INTRINSIC(vp_sdiv, 2, 3)
HELPER_MAP_VPID_TO_VPSD(vp_sdiv, VP_SDIV)
@@ -163,9 +145,6 @@ VP_PROPERTY_FUNCTIONAL_OPC(SDiv)
HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv, SDIV)
END_REGISTER_VP_INTRINSIC(vp_sdiv)
-// llvm.vp.shl(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_shl, VP_SHL, Shl, SHL)
-
// llvm.vp.srem(x,y,mask,vlen)
BEGIN_REGISTER_VP_INTRINSIC(vp_srem, 2, 3)
HELPER_MAP_VPID_TO_VPSD(vp_srem, VP_SREM)
@@ -173,9 +152,6 @@ VP_PROPERTY_FUNCTIONAL_OPC(SRem)
HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem, SREM)
END_REGISTER_VP_INTRINSIC(vp_srem)
-// llvm.vp.sub(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_SUB, Sub, SUB)
-
// llvm.vp.udiv(x,y,mask,vlen)
BEGIN_REGISTER_VP_INTRINSIC(vp_udiv, 2, 3)
HELPER_MAP_VPID_TO_VPSD(vp_udiv, VP_UDIV)
@@ -190,70 +166,8 @@ VP_PROPERTY_FUNCTIONAL_OPC(URem)
HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem, UREM)
END_REGISTER_VP_INTRINSIC(vp_urem)
-// llvm.vp.xor(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_xor, VP_XOR, Xor, XOR)
-
#undef HELPER_REGISTER_BINARY_INT_VP
-// llvm.vp.smin(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_SMIN, -1, vp_smin, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(SMIN)
-END_REGISTER_VP_SDNODE(VP_SMIN)
-
-// llvm.vp.smax(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_SMAX, -1, vp_smax, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(SMAX)
-END_REGISTER_VP_SDNODE(VP_SMAX)
-
-// llvm.vp.umin(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_UMIN, -1, vp_umin, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(UMIN)
-END_REGISTER_VP_SDNODE(VP_UMIN)
-
-// llvm.vp.umax(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_UMAX, -1, vp_umax, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(UMAX)
-END_REGISTER_VP_SDNODE(VP_UMAX)
-
-// llvm.vp.abs(x,is_int_min_poison,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_ABS, -1, vp_abs, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(ABS)
-END_REGISTER_VP_SDNODE(VP_ABS)
-
-// llvm.vp.bswap(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_BSWAP, -1, vp_bswap, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(BSWAP)
-END_REGISTER_VP_SDNODE(VP_BSWAP)
-
-// llvm.vp.bitreverse(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_BITREVERSE, -1, vp_bitreverse, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(BITREVERSE)
-END_REGISTER_VP_SDNODE(VP_BITREVERSE)
-
-// llvm.vp.ctpop(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_CTPOP, -1, vp_ctpop, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(CTPOP)
-END_REGISTER_VP_SDNODE(VP_CTPOP)
-
-// llvm.vp.ctlz(x,is_zero_poison,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ)
-END_REGISTER_VP_SDNODE(VP_CTLZ)
-BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_POISON, -1, vp_ctlz_zero_poison, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ_ZERO_POISON)
-END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_POISON)
-
-// llvm.vp.cttz(x,is_zero_poison,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(CTTZ)
-END_REGISTER_VP_SDNODE(VP_CTTZ)
-BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_POISON, -1, vp_cttz_zero_poison, 1, 2)
-END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_POISON)
-
// llvm.vp.cttz.elts(x,is_zero_poison,mask,vl)
BEGIN_REGISTER_VP_INTRINSIC(vp_cttz_elts, 2, 3)
VP_PROPERTY_NO_FUNCTIONAL
@@ -263,254 +177,8 @@ BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_POISON, 0, vp_cttz_elts_zero_poison,
END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_POISON)
END_REGISTER_VP_INTRINSIC(vp_cttz_elts)
-// llvm.vp.fshl(x,y,z,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FSHL, -1, vp_fshl, 3, 4)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FSHL)
-END_REGISTER_VP_SDNODE(VP_FSHL)
-
-// llvm.vp.fshr(x,y,z,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FSHR, -1, vp_fshr, 3, 4)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FSHR)
-END_REGISTER_VP_SDNODE(VP_FSHR)
-
-// llvm.vp.sadd.sat(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_SADDSAT, -1, vp_sadd_sat, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(SADDSAT)
-END_REGISTER_VP_SDNODE(VP_SADDSAT)
-
-// llvm.vp.uadd.sat(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_UADDSAT, -1, vp_uadd_sat, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(UADDSAT)
-END_REGISTER_VP_SDNODE(VP_UADDSAT)
-
-// llvm.vp.ssub.sat(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_SSUBSAT, -1, vp_ssub_sat, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(SSUBSAT)
-END_REGISTER_VP_SDNODE(VP_SSUBSAT)
-
-// llvm.vp.usub.sat(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_USUBSAT, -1, vp_usub_sat, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(USUBSAT)
-END_REGISTER_VP_SDNODE(VP_USUBSAT)
///// } Integer Arithmetic
-///// Floating-Point Arithmetic {
-
-// Specialized helper macro for floating-point binary operators
-// <operation>(%x, %y, %mask, %evl).
-#ifdef HELPER_REGISTER_BINARY_FP_VP
-#error \
- "The internal helper macro HELPER_REGISTER_BINARY_FP_VP is already defined!"
-#endif
-#define HELPER_REGISTER_BINARY_FP_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
- BEGIN_REGISTER_VP_SDNODE(VPSD, -1, vp_##OPSUFFIX, 2, 3) \
- VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_##OPSUFFIX) \
- VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
- VP_PROPERTY_BINARYOP \
- END_REGISTER_VP_SDNODE(VPSD)
-
-// llvm.vp.fadd(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_FP_VP(fadd, VP_FADD, FAdd, FADD)
-
-// llvm.vp.fsub(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_FP_VP(fsub, VP_FSUB, FSub, FSUB)
-
-// llvm.vp.fmul(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_FP_VP(fmul, VP_FMUL, FMul, FMUL)
-
-// llvm.vp.fdiv(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_FP_VP(fdiv, VP_FDIV, FDiv, FDIV)
-
-// llvm.vp.frem(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_FP_VP(frem, VP_FREM, FRem, FREM)
-
-#undef HELPER_REGISTER_BINARY_FP_VP
-
-// llvm.vp.fneg(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FNEG, -1, vp_fneg, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FNEG)
-END_REGISTER_VP_SDNODE(VP_FNEG)
-
-// llvm.vp.fabs(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FABS, -1, vp_fabs, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FABS)
-END_REGISTER_VP_SDNODE(VP_FABS)
-
-// llvm.vp.sqrt(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_SQRT, -1, vp_sqrt, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FSQRT)
-END_REGISTER_VP_SDNODE(VP_SQRT)
-
-// llvm.vp.fma(x,y,z,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FMA, -1, vp_fma, 3, 4)
-VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_fma)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FMA)
-END_REGISTER_VP_SDNODE(VP_FMA)
-
-// llvm.vp.fmuladd(x,y,z,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FMULADD, -1, vp_fmuladd, 3, 4)
-VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_fmuladd)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FMAD)
-END_REGISTER_VP_SDNODE(VP_FMULADD)
-
-// llvm.vp.copysign(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FCOPYSIGN, -1, vp_copysign, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(FCOPYSIGN)
-END_REGISTER_VP_SDNODE(VP_FCOPYSIGN)
-
-// llvm.vp.minnum(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FMINNUM, -1, vp_minnum, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(FMINNUM)
-END_REGISTER_VP_SDNODE(VP_FMINNUM)
-
-// llvm.vp.maxnum(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FMAXNUM, -1, vp_maxnum, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXNUM)
-END_REGISTER_VP_SDNODE(VP_FMAXNUM)
-
-// llvm.vp.minimum(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FMINIMUM, -1, vp_minimum, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(FMINIMUM)
-END_REGISTER_VP_SDNODE(VP_FMINIMUM)
-
-// llvm.vp.maximum(x,y,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FMAXIMUM, -1, vp_maximum, 2, 3)
-VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXIMUM)
-END_REGISTER_VP_SDNODE(VP_FMAXIMUM)
-
-// llvm.vp.ceil(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FCEIL, -1, vp_ceil, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FCEIL)
-END_REGISTER_VP_SDNODE(VP_FCEIL)
-
-// llvm.vp.floor(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FFLOOR, -1, vp_floor, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FFLOOR)
-END_REGISTER_VP_SDNODE(VP_FFLOOR)
-
-// llvm.vp.round(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FROUND, -1, vp_round, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FROUND)
-END_REGISTER_VP_SDNODE(VP_FROUND)
-
-// llvm.vp.roundeven(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FROUNDEVEN, -1, vp_roundeven, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FROUNDEVEN)
-END_REGISTER_VP_SDNODE(VP_FROUNDEVEN)
-
-// llvm.vp.roundtozero(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FROUNDTOZERO, -1, vp_roundtozero, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FTRUNC)
-END_REGISTER_VP_SDNODE(VP_FROUNDTOZERO)
-
-// llvm.vp.rint(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FRINT, -1, vp_rint, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FRINT)
-END_REGISTER_VP_SDNODE(VP_FRINT)
-
-// llvm.vp.nearbyint(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_FNEARBYINT, -1, vp_nearbyint, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(FNEARBYINT)
-END_REGISTER_VP_SDNODE(VP_FNEARBYINT)
-
-// llvm.vp.lrint(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_LRINT, 0, vp_lrint, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(LRINT)
-END_REGISTER_VP_SDNODE(VP_LRINT)
-
-// llvm.vp.llrint(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_LLRINT, 0, vp_llrint, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(LLRINT)
-END_REGISTER_VP_SDNODE(VP_LLRINT)
-
-///// } Floating-Point Arithmetic
-
-///// Type Casts {
-// Specialized helper macro for type conversions.
-// <operation>(%x, %mask, %evl).
-#ifdef HELPER_REGISTER_FP_CAST_VP
-#error \
- "The internal helper macro HELPER_REGISTER_FP_CAST_VP is already defined!"
-#endif
-#define HELPER_REGISTER_FP_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
- BEGIN_REGISTER_VP_SDNODE(VPSD, -1, vp_##OPSUFFIX, 1, 2) \
- VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
- VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_##OPSUFFIX) \
- END_REGISTER_VP_SDNODE(VPSD)
-
-// llvm.vp.fptoui(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(fptoui, VP_FP_TO_UINT, FPToUI, FP_TO_UINT)
-
-// llvm.vp.fptosi(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(fptosi, VP_FP_TO_SINT, FPToSI, FP_TO_SINT)
-
-// llvm.vp.uitofp(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(uitofp, VP_UINT_TO_FP, UIToFP, UINT_TO_FP)
-
-// llvm.vp.sitofp(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(sitofp, VP_SINT_TO_FP, SIToFP, SINT_TO_FP)
-
-// llvm.vp.fptrunc(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_ROUND, FPTrunc, FP_ROUND)
-
-// llvm.vp.fpext(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(fpext, VP_FP_EXTEND, FPExt, FP_EXTEND)
-
-#undef HELPER_REGISTER_FP_CAST_VP
-
-// Specialized helper macro for integer type conversions.
-// <operation>(%x, %mask, %evl).
-#ifdef HELPER_REGISTER_INT_CAST_VP
-#error \
- "The internal helper macro HELPER_REGISTER_INT_CAST_VP is already defined!"
-#endif
-#define HELPER_REGISTER_INT_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
- BEGIN_REGISTER_VP_SDNODE(VPSD, -1, vp_##OPSUFFIX, 1, 2) \
- VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
- END_REGISTER_VP_SDNODE(VPSD)
-
-// llvm.vp.trunc(x,mask,vlen)
-HELPER_REGISTER_INT_CAST_VP(trunc, VP_TRUNCATE, Trunc, TRUNCATE)
-
-// llvm.vp.zext(x,mask,vlen)
-HELPER_REGISTER_INT_CAST_VP(zext, VP_ZERO_EXTEND, ZExt, ZERO_EXTEND)
-
-// llvm.vp.sext(x,mask,vlen)
-HELPER_REGISTER_INT_CAST_VP(sext, VP_SIGN_EXTEND, SExt, SIGN_EXTEND)
-
-// llvm.vp.ptrtoint(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_PTRTOINT, -1, vp_ptrtoint, 1, 2)
-END_REGISTER_VP_SDNODE(VP_PTRTOINT)
-
-// llvm.vp.inttoptr(x,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_INTTOPTR, -1, vp_inttoptr, 1, 2)
-END_REGISTER_VP_SDNODE(VP_INTTOPTR)
-
-#undef HELPER_REGISTER_INT_CAST_VP
-
-///// } Type Casts
-
-///// Comparisons {
-
-// VP_SETCC (ISel only)
-BEGIN_REGISTER_VP_SDNODE(VP_SETCC, 0, vp_setcc, 3, 4)
-END_REGISTER_VP_SDNODE(VP_SETCC)
-
-///// } Comparisons
-
-// llvm.vp.is.fpclass(on_true,on_false,mask,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_IS_FPCLASS, 0, vp_is_fpclass, 2, 3)
-END_REGISTER_VP_SDNODE(VP_IS_FPCLASS)
-
///// Memory Operations {
// llvm.vp.store(val,ptr,mask,vlen)
BEGIN_REGISTER_VP_INTRINSIC(vp_store, 2, 3)
@@ -675,15 +343,10 @@ HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fmul, VP_REDUCE_FMUL,
///// Shuffles {
-// The mask 'cond' operand of llvm.vp.select and llvm.vp.merge are not reported
-// as masks with the BEGIN_REGISTER_VP_* macros. This is because, unlike other
-// VP intrinsics, these two have a defined result on lanes where the mask is
+// The mask 'cond' operand of llvm.vp.merge is not reported
+// as masks with the BEGIN_REGISTER_VP_* macros. This is because, unlike other
+// VP intrinsics, vp.merge has a defined result on lanes where the mask is
// false.
-//
-// llvm.vp.select(cond,on_true,on_false,vlen)
-BEGIN_REGISTER_VP_SDNODE(VP_SELECT, -1, vp_select, std::nullopt, 3)
-VP_PROPERTY_FUNCTIONAL_SDOPC(VSELECT)
-END_REGISTER_VP_SDNODE(VP_SELECT)
// llvm.vp.merge(cond,on_true,on_false,pivot)
BEGIN_REGISTER_VP(vp_merge, std::nullopt, 3, VP_MERGE, -1)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 09e26fe2aa58c..c0c7c49f12f4a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -79,7 +79,6 @@
#include <utility>
#include <variant>
-#include "MatchContext.h"
#include "SDNodeDbgValue.h"
using namespace llvm;
@@ -484,7 +483,6 @@ namespace {
SDValue visitCTPOP(SDNode *N);
SDValue visitSELECT(SDNode *N);
SDValue visitVSELECT(SDNode *N);
- SDValue visitVP_SELECT(SDNode *N);
SDValue visitSELECT_CC(SDNode *N);
SDValue visitSETCC(SDNode *N);
SDValue visitSETCCCARRY(SDNode *N);
@@ -4158,15 +4156,12 @@ SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N, const SDLoc &DL) {
// -->
//
// (ctlz_zero_poison (not (shl Src BitWidthDiff)))
-template <class MatchContextClass>
static SDValue foldSubCtlzNot(SDNode *N, SelectionDAG &DAG) {
const SDLoc DL(N);
SDValue N0 = N->getOperand(0);
EVT VT = N0.getValueType();
unsigned BitWidth = VT.getScalarSizeInBits();
- MatchContextClass Matcher(DAG, DAG.getTargetLoweringInfo(), N);
-
APInt AndMask;
APInt XorMask;
uint64_t BitWidthDiff;
@@ -4174,19 +4169,17 @@ static SDValue foldSubCtlzNot(SDNode *N, SelectionDAG &DAG) {
SDValue CtlzOp;
SDValue Src;
- if (!sd_context_match(
- N, Matcher, m_Sub(m_Ctlz(m_Value(CtlzOp)), m_ConstInt(BitWidthDiff))))
+ if (!sd_match(N, m_Sub(m_Ctlz(m_Value(CtlzOp)), m_ConstInt(BitWidthDiff))))
return SDValue();
- if (sd_context_match(CtlzOp, Matcher, m_ZExt(m_Not(m_Value(Src))))) {
+ if (sd_match(CtlzOp, m_ZExt(m_Not(m_Value(Src))))) {
// DAG Legalisation Pattern:
// (sub (ctlz (zero_extend (not Op)) BitWidthDiff))
if ((BitWidth - Src.getValueType().getScalarSizeInBits()) != BitWidthDiff)
return SDValue();
Src = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Src);
- } else if (sd_context_match(CtlzOp, Matcher,
- m_And(m_Xor(m_Value(Src), m_ConstInt(XorMask)),
+ } else if (sd_match(CtlzOp, m_And(m_Xor(m_Value(Src), m_ConstInt(XorMask)),
m_ConstInt(AndMask)))) {
// Type Legalisation Pattern:
// (sub (ctlz (and (xor Op XorMask) AndMask)) BitWidthDiff)
@@ -4199,11 +4192,11 @@ static SDValue foldSubCtlzNot(SDNode *N, SelectionDAG &DAG) {
return SDValue();
SDValue ShiftConst = DAG.getShiftAmountConstant(BitWidthDiff, VT, DL);
- SDValue LShift = Matcher.getNode(ISD::SHL, DL, VT, Src, ShiftConst);
+ SDValue LShift = DAG.getNode(ISD::SHL, DL, VT, Src, ShiftConst);
SDValue Not =
- Matcher.getNode(ISD::XOR, DL, VT, LShift, DAG.getAllOnesConstant(DL, VT));
+ DAG.getNode(ISD::XOR, DL, VT, LShift, DAG.getAllOnesConstant(DL, VT));
- return Matcher.getNode(ISD::CTLZ_ZERO_POISON, DL, VT, Not);
+ return DAG.getNode(ISD::CTLZ_ZERO_POISON, DL, VT, Not);
}
// Fold sub(x, mul(divrem(x,y)[0], y)) to divrem(x, y)[1]
@@ -4276,7 +4269,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
unsigned BitWidth = VT.getScalarSizeInBits();
SDLoc DL(N);
- if (SDValue V = foldSubCtlzNot<EmptyMatchContext>(N, DAG))
+ if (SDValue V = foldSubCtlzNot(N, DAG))
return V;
// fold (sub x, x) -> 0
@@ -13094,17 +13087,13 @@ SDValue DAGCombiner::foldSelectOfConstants(SDNode *N) {
return SDValue();
}
-template <class MatchContextClass>
static SDValue foldBoolSelectToLogic(SDNode *N, const SDLoc &DL,
SelectionDAG &DAG) {
- assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT ||
- N->getOpcode() == ISD::VP_SELECT) &&
- "Expected a (v)(vp.)select");
+ assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) &&
+ "Expected a (v)select");
SDValue Cond = N->getOperand(0);
SDValue T = N->getOperand(1), F = N->getOperand(2);
EVT VT = N->getValueType(0);
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- MatchContextClass matcher(DAG, TLI, N);
if (VT != Cond.getValueType() || VT.getScalarSizeInBits() != 1)
return SDValue();
@@ -13112,25 +13101,25 @@ static SDValue foldBoolSelectToLogic(SDNode *N, const SDLoc &DL,
// select Cond, Cond, F --> or Cond, freeze(F)
// select Cond, 1, F --> or Cond, freeze(F)
if (Cond == T || isOneOrOneSplat(T, /* AllowUndefs */ true))
- return matcher.getNode(ISD::OR, DL, VT, Cond, DAG.getFreeze(F));
+ return DAG.getNode(ISD::OR, DL, VT, Cond, DAG.getFreeze(F));
// select Cond, T, Cond --> and Cond, freeze(T)
// select Cond, T, 0 --> and Cond, freeze(T)
if (Cond == F || isNullOrNullSplat(F, /* AllowUndefs */ true))
- return matcher.getNode(ISD::AND, DL, VT, Cond, DAG.getFreeze(T));
+ return DAG.getNode(ISD::AND, DL, VT, Cond, DAG.getFreeze(T));
// select Cond, T, 1 --> or (not Cond), freeze(T)
if (isOneOrOneSplat(F, /* AllowUndefs */ true)) {
SDValue NotCond =
- matcher.getNode(ISD::XOR, DL, VT, Cond, DAG.getAllOnesConstant(DL, VT));
- return matcher.getNode(ISD::OR, DL, VT, NotCond, DAG.getFreeze(T));
+ DAG.getNode(ISD::XOR, DL, VT, Cond, DAG.getAllOnesConstant(DL, VT));
+ return DAG.getNode(ISD::OR, DL, VT, NotCond, DAG.getFreeze(T));
}
// select Cond, 0, F --> and (not Cond), freeze(F)
if (isNullOrNullSplat(T, /* AllowUndefs */ true)) {
SDValue NotCond =
- matcher.getNode(ISD::XOR, DL, VT, Cond, DAG.getAllOnesConstant(DL, VT));
- return matcher.getNode(ISD::AND, DL, VT, NotCond, DAG.getFreeze(F));
+ DAG.getNode(ISD::XOR, DL, VT, Cond, DAG.getAllOnesConstant(DL, VT));
+ return DAG.getNode(ISD::AND, DL, VT, NotCond, DAG.getFreeze(F));
}
return SDValue();
@@ -13482,7 +13471,7 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
if (SDValue V = DAG.simplifySelect(N0, N1, N2))
return V;
- if (SDValue V = foldBoolSelectToLogic<EmptyMatchContext>(N, DL, DAG))
+ if (SDValue V = foldBoolSelectToLogic(N, DL, DAG))
return V;
// select (not Cond), N1, N2 -> select Cond, N2, N1
@@ -14495,21 +14484,6 @@ SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) {
return SDValue();
}
-SDValue DAGCombiner::visitVP_SELECT(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDLoc DL(N);
-
- if (SDValue V = DAG.simplifySelect(N0, N1, N2))
- return V;
-
- if (SDValue V = foldBoolSelectToLogic<VPMatchContext>(N, DL, DAG))
- return V;
-
- return SDValue();
-}
-
static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
SDValue FVal,
const TargetLowering &TLI,
@@ -14626,7 +14600,7 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
if (SDValue V = DAG.simplifySelect(N0, N1, N2))
return V;
- if (SDValue V = foldBoolSelectToLogic<EmptyMatchContext>(N, DL, DAG))
+ if (SDValue V = foldBoolSelectToLogic(N, DL, DAG))
return V;
// vselect (not Cond), N1, N2 -> vselect Cond, N2, N1
@@ -30397,17 +30371,8 @@ SDValue DAGCombiner::visitVPOp(SDNode *N) {
ISD::isConstantSplatVectorAllZeros(N->getOperand(*MaskIdx).getNode());
// This is the only generic VP combine we support for now.
- if (!AreAllEltsDisabled) {
- switch (N->getOpcode()) {
- case ISD::VP_SELECT:
- return visitVP_SELECT(N);
- case ISD::VP_SUB:
- return foldSubCtlzNot<VPMatchContext>(N, DAG);
- default:
- break;
- }
+ if (!AreAllEltsDisabled)
return SDValue();
- }
// Binary operations can be replaced by UNDEF.
if (ISD::isVPBinaryOp(N->getOpcode()))
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 70e094bc0d255..cc27c430b297d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1067,15 +1067,14 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
case ISD::STRICT_FSETCCS:
case ISD::SETCC:
case ISD::SETCCCARRY:
- case ISD::VP_SETCC:
case ISD::BR_CC: {
unsigned Opc = Node->getOpcode();
- unsigned CCOperand = Opc == ISD::SELECT_CC ? 4
- : Opc == ISD::STRICT_FSETCC ? 3
- : Opc == ISD::STRICT_FSETCCS ? 3
- : Opc == ISD::SETCCCARRY ? 3
- : (Opc == ISD::SETCC || Opc == ISD::VP_SETCC) ? 2
- : 1;
+ unsigned CCOperand = Opc == ISD::SELECT_CC ? 4
+ : Opc == ISD::STRICT_FSETCC ? 3
+ : Opc == ISD::STRICT_FSETCCS ? 3
+ : Opc == ISD::SETCCCARRY ? 3
+ : Opc == ISD::SETCC ? 2
+ : 1;
unsigned CompareOperand = Opc == ISD::BR_CC ? 2
: Opc == ISD::STRICT_FSETCC ? 1
: Opc == ISD::STRICT_FSETCCS ? 1
@@ -4420,10 +4419,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Results.push_back(Tmp1);
break;
case ISD::SETCC:
- case ISD::VP_SETCC:
case ISD::STRICT_FSETCC:
case ISD::STRICT_FSETCCS: {
- bool IsVP = Node->getOpcode() == ISD::VP_SETCC;
bool IsStrict = Node->getOpcode() == ISD::STRICT_FSETCC ||
Node->getOpcode() == ISD::STRICT_FSETCCS;
bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS;
@@ -4432,14 +4429,9 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp1 = Node->getOperand(0 + Offset);
Tmp2 = Node->getOperand(1 + Offset);
Tmp3 = Node->getOperand(2 + Offset);
- SDValue Mask, EVL;
- if (IsVP) {
- Mask = Node->getOperand(3 + Offset);
- EVL = Node->getOperand(4 + Offset);
- }
- bool Legalized = TLI.LegalizeSetCCCondCode(
- DAG, Node->getValueType(0), Tmp1, Tmp2, Tmp3, Mask, EVL, NeedInvert, dl,
- Chain, IsSignaling);
+ bool Legalized =
+ TLI.LegalizeSetCCCondCode(DAG, Node->getValueType(0), Tmp1, Tmp2, Tmp3,
+ NeedInvert, dl, Chain, IsSignaling);
if (Legalized) {
// If we expanded the SETCC by swapping LHS and RHS, or by inverting the
@@ -4449,9 +4441,6 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getVTList(),
{Chain, Tmp1, Tmp2, Tmp3}, Node->getFlags());
Chain = Tmp1.getValue(1);
- } else if (IsVP) {
- Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0),
- {Tmp1, Tmp2, Tmp3, Mask, EVL}, Node->getFlags());
} else {
Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1,
Tmp2, Tmp3, Node->getFlags());
@@ -4461,11 +4450,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// If we expanded the SETCC by inverting the condition code, then wrap
// the existing SETCC in a NOT to restore the intended condition.
if (NeedInvert) {
- if (!IsVP)
- Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
- else
- Tmp1 =
- DAG.getVPLogicalNOT(dl, Tmp1, Mask, EVL, Tmp1->getValueType(0));
+ Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
}
Results.push_back(Tmp1);
@@ -4481,7 +4466,6 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// Otherwise, SETCC for the given comparison type must be completely
// illegal; expand it into a SELECT_CC.
- // FIXME: This drops the mask/evl for VP_SETCC.
EVT VT = Node->getValueType(0);
EVT Tmp1VT = Tmp1.getValueType();
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
@@ -4543,7 +4527,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
if (!Legalized) {
Legalized = TLI.LegalizeSetCCCondCode(
DAG, getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC,
- /*Mask*/ SDValue(), /*EVL*/ SDValue(), NeedInvert, dl, Chain);
+ NeedInvert, dl, Chain);
assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
@@ -4575,9 +4559,9 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp3 = Node->getOperand(3); // RHS
Tmp4 = Node->getOperand(1); // CC
- bool Legalized = TLI.LegalizeSetCCCondCode(
- DAG, getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3, Tmp4,
- /*Mask*/ SDValue(), /*EVL*/ SDValue(), NeedInvert, dl, Chain);
+ bool Legalized =
+ TLI.LegalizeSetCCCondCode(DAG, getSetCCResultType(Tmp2.getValueType()),
+ Tmp2, Tmp3, Tmp4, NeedInvert, dl, Chain);
(void)Legalized;
assert(Legalized && "Can't legalize BR_CC with legal condition!");
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 2f409a704d186..43e41ed39ca1d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -60,22 +60,15 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
- case ISD::VP_BITREVERSE:
case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
- case ISD::VP_BSWAP:
case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
- case ISD::VP_CTLZ_ZERO_POISON:
- case ISD::VP_CTLZ:
case ISD::CTLZ_ZERO_POISON:
case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
case ISD::CTLS: Res = PromoteIntRes_CTLS(N); break;
case ISD::PARITY:
- case ISD::VP_CTPOP:
case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
- case ISD::VP_CTTZ_ZERO_POISON:
- case ISD::VP_CTTZ:
case ISD::CTTZ_ZERO_POISON:
case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
case ISD::CTTZ_ELTS_ZERO_POISON:
@@ -99,7 +92,6 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
break;
case ISD::SELECT:
case ISD::VSELECT:
- case ISD::VP_SELECT:
case ISD::VP_MERGE:
Res = PromoteIntRes_Select(N);
break;
@@ -112,15 +104,11 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::UMIN:
case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
- case ISD::SHL:
- case ISD::VP_SHL: Res = PromoteIntRes_SHL(N); break;
+ case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
case ISD::SIGN_EXTEND_INREG:
Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
- case ISD::SRA:
- case ISD::VP_SRA: Res = PromoteIntRes_SRA(N); break;
- case ISD::SRL:
- case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break;
- case ISD::VP_TRUNCATE:
+ case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
+ case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
case ISD::POISON:
case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
@@ -179,13 +167,9 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
break;
case ISD::SIGN_EXTEND:
- case ISD::VP_SIGN_EXTEND:
case ISD::ZERO_EXTEND:
- case ISD::VP_ZERO_EXTEND:
case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
- case ISD::VP_FP_TO_SINT:
- case ISD::VP_FP_TO_UINT:
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
@@ -213,29 +197,19 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::XOR:
case ISD::ADD:
case ISD::SUB:
- case ISD::MUL:
- case ISD::VP_AND:
- case ISD::VP_OR:
- case ISD::VP_XOR:
- case ISD::VP_ADD:
- case ISD::VP_SUB:
- case ISD::VP_MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
+ case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
case ISD::ABDS:
case ISD::AVGCEILS:
case ISD::AVGFLOORS:
- case ISD::VP_SMIN:
- case ISD::VP_SMAX:
case ISD::SDIV:
case ISD::SREM:
case ISD::VP_SDIV:
- case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
+ case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
case ISD::ABDU:
case ISD::AVGCEILU:
case ISD::AVGFLOORU:
- case ISD::VP_UMIN:
- case ISD::VP_UMAX:
case ISD::UDIV:
case ISD::UREM:
case ISD::VP_UDIV:
@@ -271,13 +245,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::USUBSAT:
case ISD::SSHLSAT:
case ISD::USHLSAT:
- Res = PromoteIntRes_ADDSUBSHLSAT<EmptyMatchContext>(N);
- break;
- case ISD::VP_SADDSAT:
- case ISD::VP_UADDSAT:
- case ISD::VP_SSUBSAT:
- case ISD::VP_USUBSAT:
- Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
+ Res = PromoteIntRes_ADDSUBSHLSAT(N);
break;
case ISD::SCMP:
@@ -365,11 +333,6 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
Res = PromoteIntRes_FunnelShift(N);
break;
- case ISD::VP_FSHL:
- case ISD::VP_FSHR:
- Res = PromoteIntRes_VPFunnelShift(N);
- break;
-
case ISD::CLMUL:
case ISD::CLMULH:
case ISD::CLMULR:
@@ -683,14 +646,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
SDValue ShAmt = DAG.getShiftAmountConstant(DiffBits, NVT, dl);
- if (N->getOpcode() == ISD::BSWAP)
- return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
- ShAmt);
- SDValue Mask = N->getOperand(1);
- SDValue EVL = N->getOperand(2);
- return DAG.getNode(ISD::VP_SRL, dl, NVT,
- DAG.getNode(ISD::VP_BSWAP, dl, NVT, Op, Mask, EVL), ShAmt,
- Mask, EVL);
+ return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
+ ShAmt);
}
SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
@@ -711,14 +668,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
SDValue ShAmt = DAG.getShiftAmountConstant(DiffBits, NVT, dl);
- if (N->getOpcode() == ISD::BITREVERSE)
- return DAG.getNode(ISD::SRL, dl, NVT,
- DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), ShAmt);
- SDValue Mask = N->getOperand(1);
- SDValue EVL = N->getOperand(2);
- return DAG.getNode(ISD::VP_SRL, dl, NVT,
- DAG.getNode(ISD::VP_BITREVERSE, dl, NVT, Op, Mask, EVL),
- ShAmt, Mask, EVL);
+ return DAG.getNode(ISD::SRL, dl, NVT,
+ DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), ShAmt);
}
SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
@@ -762,7 +713,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
}
unsigned CtlzOpcode = N->getOpcode();
- if (CtlzOpcode == ISD::CTLZ || CtlzOpcode == ISD::VP_CTLZ) {
+ if (CtlzOpcode == ISD::CTLZ) {
// Subtract off the extra leading bits in the bigger type.
SDValue ExtractLeadingBits = DAG.getConstant(
NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl, NVT);
@@ -771,34 +722,19 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
// At this stage SUB is guaranteed to be positive no-wrap,
// that to be used in further KnownBits optimizations.
- if (!N->isVPOpcode())
- return DAG.getNode(ISD::SUB, dl, NVT,
- DAG.getNode(N->getOpcode(), dl, NVT, Op),
- ExtractLeadingBits, SDNodeFlags::NoUnsignedWrap);
- SDValue Mask = N->getOperand(1);
- SDValue EVL = N->getOperand(2);
- return DAG.getNode(ISD::VP_SUB, dl, NVT,
- DAG.getNode(N->getOpcode(), dl, NVT, Op, Mask, EVL),
- ExtractLeadingBits, Mask, EVL,
- SDNodeFlags::NoUnsignedWrap);
- }
- if (CtlzOpcode == ISD::CTLZ_ZERO_POISON ||
- CtlzOpcode == ISD::VP_CTLZ_ZERO_POISON) {
+ return DAG.getNode(ISD::SUB, dl, NVT,
+ DAG.getNode(N->getOpcode(), dl, NVT, Op),
+ ExtractLeadingBits, SDNodeFlags::NoUnsignedWrap);
+ }
+ if (CtlzOpcode == ISD::CTLZ_ZERO_POISON) {
// Any Extend the argument
SDValue Op = GetPromotedInteger(N->getOperand(0));
// Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
unsigned SHLAmount = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
auto ShiftConst =
DAG.getShiftAmountConstant(SHLAmount, Op.getValueType(), dl);
- if (!N->isVPOpcode()) {
- Op = DAG.getNode(ISD::SHL, dl, NVT, Op, ShiftConst);
- return DAG.getNode(CtlzOpcode, dl, NVT, Op);
- }
-
- SDValue Mask = N->getOperand(1);
- SDValue EVL = N->getOperand(2);
- Op = DAG.getNode(ISD::VP_SHL, dl, NVT, Op, ShiftConst, Mask, EVL);
- return DAG.getNode(CtlzOpcode, dl, NVT, Op, Mask, EVL);
+ Op = DAG.getNode(ISD::SHL, dl, NVT, Op, ShiftConst);
+ return DAG.getNode(CtlzOpcode, dl, NVT, Op);
}
llvm_unreachable("Invalid CTLZ Opcode");
}
@@ -835,13 +771,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
// Zero extend to the promoted type and do the count or parity there.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
- if (!N->isVPOpcode())
- return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
-
- SDValue Mask = N->getOperand(1);
- SDValue EVL = N->getOperand(2);
- return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op, Mask,
- EVL);
+ return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
}
SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
@@ -866,25 +796,16 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
}
unsigned NewOpc = N->getOpcode();
- if (NewOpc == ISD::CTTZ || NewOpc == ISD::VP_CTTZ) {
+ if (NewOpc == ISD::CTTZ) {
// The count is the same in the promoted type except if the original
// value was zero. This can be handled by setting the bit just off
// the top of the original type.
auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
OVT.getScalarSizeInBits());
- if (NewOpc == ISD::CTTZ) {
- Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
- NewOpc = ISD::CTTZ_ZERO_POISON;
- } else {
- Op =
- DAG.getNode(ISD::VP_OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT),
- N->getOperand(1), N->getOperand(2));
- NewOpc = ISD::VP_CTTZ_ZERO_POISON;
- }
+ Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
+ NewOpc = ISD::CTTZ_ZERO_POISON;
}
- if (!N->isVPOpcode())
- return DAG.getNode(NewOpc, dl, NVT, Op);
- return DAG.getNode(NewOpc, dl, NVT, Op, N->getOperand(1), N->getOperand(2));
+ return DAG.getNode(NewOpc, dl, NVT, Op);
}
SDValue DAGTypeLegalizer::PromoteIntRes_VP_CttzElements(SDNode *N) {
@@ -931,9 +852,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
// Legalize the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
- } else if (NewOpc == ISD::VP_FP_TO_SINT || NewOpc == ISD::VP_FP_TO_UINT) {
- Res = DAG.getNode(NewOpc, dl, NVT, {N->getOperand(0), N->getOperand(1),
- N->getOperand(2)});
} else {
Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
}
@@ -946,8 +864,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
// before legalization: fp-to-uint16, 65534. -> 0xfffe
// after legalization: fp-to-sint32, 65534. -> 0x0000fffe
return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
- N->getOpcode() == ISD::STRICT_FP_TO_UINT ||
- N->getOpcode() == ISD::VP_FP_TO_UINT)
+ N->getOpcode() == ISD::STRICT_FP_TO_UINT)
? ISD::AssertZext
: ISD::AssertSext,
dl, NVT, Res,
@@ -1032,12 +949,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
}
// Otherwise, just extend the original operand all the way to the larger type.
- if (N->getNumOperands() != 1) {
- assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
- return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0),
- N->getOperand(1), N->getOperand(2));
- }
return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
}
@@ -1148,7 +1059,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
return DAG.getBoolExtOrTrunc(Res.getValue(1), dl, NVT, VT);
}
-template <class MatchContextClass>
SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
// If the promoted type is legal, we can convert this to:
// 1. ANY_EXTEND iN to iM
@@ -1160,16 +1070,15 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
SDLoc dl(N);
SDValue Op1 = N->getOperand(0);
SDValue Op2 = N->getOperand(1);
- MatchContextClass matcher(DAG, TLI, N);
- unsigned Opcode = matcher.getRootBaseOpcode();
+ unsigned Opcode = N->getOpcode();
unsigned OldBits = Op1.getScalarValueSizeInBits();
// USUBSAT can always be promoted as long as we have zero/sign-extended the
// args.
if (Opcode == ISD::USUBSAT) {
SExtOrZExtPromotedOperands(Op1, Op2);
- return matcher.getNode(ISD::USUBSAT, dl, Op1.getValueType(), Op1, Op2);
+ return DAG.getNode(ISD::USUBSAT, dl, Op1.getValueType(), Op1, Op2);
}
if (Opcode == ISD::UADDSAT) {
@@ -1179,7 +1088,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
if (TLI.isSExtCheaperThanZExt(OVT, NVT)) {
Op1 = SExtPromotedInteger(Op1);
Op2 = SExtPromotedInteger(Op2);
- return matcher.getNode(ISD::UADDSAT, dl, NVT, Op1, Op2);
+ return DAG.getNode(ISD::UADDSAT, dl, NVT, Op1, Op2);
}
Op1 = ZExtPromotedInteger(Op1);
@@ -1187,8 +1096,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
unsigned NewBits = NVT.getScalarSizeInBits();
APInt MaxVal = APInt::getLowBitsSet(NewBits, OldBits);
SDValue SatMax = DAG.getConstant(MaxVal, dl, NVT);
- SDValue Add = matcher.getNode(ISD::ADD, dl, NVT, Op1, Op2);
- return matcher.getNode(ISD::UMIN, dl, NVT, Add, SatMax);
+ SDValue Add = DAG.getNode(ISD::ADD, dl, NVT, Op1, Op2);
+ return DAG.getNode(ISD::UMIN, dl, NVT, Add, SatMax);
}
bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
@@ -1207,7 +1116,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
// Shift cannot use a min/max expansion, we can't detect overflow if all of
// the bits have been shifted out.
- if (IsShift || matcher.isOperationLegal(Opcode, PromotedType)) {
+ if (IsShift || TLI.isOperationLegal(Opcode, PromotedType)) {
unsigned ShiftOp;
switch (Opcode) {
case ISD::SADDSAT:
@@ -1228,10 +1137,10 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
DAG.getShiftAmountConstant(SHLAmount, PromotedType, dl);
Op1 = DAG.getNode(ISD::SHL, dl, PromotedType, Op1, ShiftAmount);
if (!IsShift)
- Op2 = matcher.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
+ Op2 = DAG.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
- SDValue Result = matcher.getNode(Opcode, dl, PromotedType, Op1, Op2);
- return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
+ SDValue Result = DAG.getNode(Opcode, dl, PromotedType, Op1, Op2);
+ return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
}
unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
@@ -1239,9 +1148,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
- SDValue Result = matcher.getNode(AddOp, dl, PromotedType, Op1, Op2);
- Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
- Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
+ SDValue Result = DAG.getNode(AddOp, dl, PromotedType, Op1, Op2);
+ Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
+ Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
return Result;
}
@@ -1440,7 +1349,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
SDValue RHS = GetPromotedInteger(N->getOperand(2));
unsigned Opcode = N->getOpcode();
- if (Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE)
+ if (Opcode == ISD::VP_MERGE)
return DAG.getNode(Opcode, SDLoc(N), LHS.getValueType(), Mask, LHS, RHS,
N->getOperand(3));
return DAG.getNode(Opcode, SDLoc(N), LHS.getValueType(), Mask, LHS, RHS);
@@ -1521,13 +1430,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
SDValue RHS = N->getOperand(1);
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
- if (N->getOpcode() != ISD::VP_SHL)
- return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
-
- SDValue Mask = N->getOperand(2);
- SDValue EVL = N->getOperand(3);
- return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
- Mask, EVL);
+ return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
@@ -1542,12 +1445,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
// that too is okay if they are integer operations.
SDValue LHS = GetPromotedInteger(N->getOperand(0));
SDValue RHS = GetPromotedInteger(N->getOperand(1));
- if (N->getNumOperands() == 2)
- return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
- assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
- return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
- N->getOperand(2), N->getOperand(3));
+ return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
@@ -1557,7 +1455,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
if (N->getNumOperands() == 2)
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
+ assert((N->getOpcode() == ISD::VP_SDIV || N->getOpcode() == ISD::VP_SREM) &&
+ "Expected VP opcode");
SDValue Mask = N->getOperand(2);
SDValue EVL = N->getOperand(3);
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
@@ -1571,7 +1470,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
if (N->getNumOperands() == 2)
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
+ assert((N->getOpcode() == ISD::VP_UDIV || N->getOpcode() == ISD::VP_UREM) &&
+ "Expected VP opcode");
// Zero extend the input.
SDValue Mask = N->getOperand(2);
SDValue EVL = N->getOperand(3);
@@ -1613,13 +1513,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
SDValue RHS = N->getOperand(1);
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
- if (N->getOpcode() != ISD::VP_SRA)
- return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
-
- SDValue Mask = N->getOperand(2);
- SDValue EVL = N->getOperand(3);
- return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
- Mask, EVL);
+ return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
@@ -1628,13 +1522,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
- if (N->getOpcode() != ISD::VP_SRL)
- return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
-
- SDValue Mask = N->getOperand(2);
- SDValue EVL = N->getOperand(3);
- return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
- Mask, EVL);
+ return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
@@ -1733,59 +1621,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
return DAG.getNode(Opcode, DL, VT, Hi, Lo, Amt);
}
-// A vp version of PromoteIntRes_FunnelShift.
-SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
- SDValue Hi = GetPromotedInteger(N->getOperand(0));
- SDValue Lo = GetPromotedInteger(N->getOperand(1));
- SDValue Amt = N->getOperand(2);
- SDValue Mask = N->getOperand(3);
- SDValue EVL = N->getOperand(4);
- if (getTypeAction(Amt.getValueType()) == TargetLowering::TypePromoteInteger)
- Amt = ZExtPromotedInteger(Amt);
- EVT AmtVT = Amt.getValueType();
-
- SDLoc DL(N);
- EVT OldVT = N->getOperand(0).getValueType();
- EVT VT = Lo.getValueType();
- unsigned Opcode = N->getOpcode();
- bool IsFSHR = Opcode == ISD::VP_FSHR;
- unsigned OldBits = OldVT.getScalarSizeInBits();
- unsigned NewBits = VT.getScalarSizeInBits();
-
- // Amount has to be interpreted modulo the old bit width.
- Amt = DAG.getNode(ISD::VP_UREM, DL, AmtVT, Amt,
- DAG.getConstant(OldBits, DL, AmtVT), Mask, EVL);
-
- // If the promoted type is twice the size (or more), then we use the
- // traditional funnel 'double' shift codegen. This isn't necessary if the
- // shift amount is constant.
- // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
- // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
- if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Amt) &&
- !TLI.isOperationLegalOrCustom(Opcode, VT)) {
- SDValue HiShift = DAG.getConstant(OldBits, DL, VT);
- Hi = DAG.getNode(ISD::VP_SHL, DL, VT, Hi, HiShift, Mask, EVL);
- Lo = DAG.getVPZeroExtendInReg(Lo, Mask, EVL, DL, OldVT);
- SDValue Res = DAG.getNode(ISD::VP_OR, DL, VT, Hi, Lo, Mask, EVL);
- Res = DAG.getNode(IsFSHR ? ISD::VP_SRL : ISD::VP_SHL, DL, VT, Res, Amt,
- Mask, EVL);
- if (!IsFSHR)
- Res = DAG.getNode(ISD::VP_SRL, DL, VT, Res, HiShift, Mask, EVL);
- return Res;
- }
-
- // Shift Lo up to occupy the upper bits of the promoted type.
- SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, AmtVT);
- Lo = DAG.getNode(ISD::VP_SHL, DL, VT, Lo, ShiftOffset, Mask, EVL);
-
- // Increase Amount to shift the result into the lower bits of the promoted
- // type.
- if (IsFSHR)
- Amt = DAG.getNode(ISD::VP_ADD, DL, AmtVT, Amt, ShiftOffset, Mask, EVL);
-
- return DAG.getNode(Opcode, DL, VT, Hi, Lo, Amt, Mask, EVL);
-}
-
SDValue DAGTypeLegalizer::PromoteIntRes_CLMUL(SDNode *N) {
unsigned Opcode = N->getOpcode();
@@ -1888,23 +1723,10 @@ SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
NumElts.divideCoefficientBy(2));
- if (N->getOpcode() == ISD::TRUNCATE) {
- EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
- EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
- } else {
- assert(N->getOpcode() == ISD::VP_TRUNCATE &&
- "Expected VP_TRUNCATE opcode");
- SDValue MaskLo, MaskHi, EVLLo, EVLHi;
- std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
- std::tie(EVLLo, EVLHi) =
- DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
- EOp1 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp1, MaskLo, EVLLo);
- EOp2 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp2, MaskHi, EVLHi);
- }
+ EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
+ EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
}
- // TODO: VP_TRUNCATE need to handle when TypeWidenVector access to some
- // targets.
case TargetLowering::TypeWidenVector: {
SDValue WideInOp = GetWidenedVector(InOp);
@@ -1926,9 +1748,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
}
// Truncate to NVT instead of VT
- if (N->getOpcode() == ISD::VP_TRUNCATE)
- return DAG.getNode(ISD::VP_TRUNCATE, dl, NVT, Res, N->getOperand(1),
- N->getOperand(2));
return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
}
@@ -2177,11 +1996,8 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::VSELECT:
case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
- case ISD::VP_SETCC:
case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
- case ISD::VP_SIGN_EXTEND: Res = PromoteIntOp_VP_SIGN_EXTEND(N); break;
- case ISD::VP_SINT_TO_FP:
case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
@@ -2200,11 +2016,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::VECTOR_COMPRESS:
Res = PromoteIntOp_VECTOR_COMPRESS(N, OpNo);
break;
- case ISD::VP_TRUNCATE:
case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
case ISD::BF16_TO_FP:
case ISD::FP16_TO_FP:
- case ISD::VP_UINT_TO_FP:
case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
case ISD::CONVERT_FROM_ARBITRARY_FP:
Res = PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(N);
@@ -2212,7 +2026,6 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::STRICT_FP16_TO_FP:
case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
- case ISD::VP_ZERO_EXTEND: Res = PromoteIntOp_VP_ZERO_EXTEND(N); break;
case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
@@ -2612,14 +2425,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
// The CC (#2) is always legal.
- if (N->getOpcode() == ISD::SETCC)
- return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
-
- assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
-
- return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
- N->getOperand(3), N->getOperand(4)),
- 0);
+ return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
}
SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
@@ -2654,29 +2460,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
Op, DAG.getValueType(N->getOperand(0).getValueType()));
}
-SDValue DAGTypeLegalizer::PromoteIntOp_VP_SIGN_EXTEND(SDNode *N) {
- SDLoc dl(N);
- EVT VT = N->getValueType(0);
- SDValue Op = GetPromotedInteger(N->getOperand(0));
- // FIXME: There is no VP_ANY_EXTEND yet.
- Op = DAG.getNode(ISD::VP_ZERO_EXTEND, dl, VT, Op, N->getOperand(1),
- N->getOperand(2));
- unsigned Diff =
- VT.getScalarSizeInBits() - N->getOperand(0).getScalarValueSizeInBits();
- SDValue ShAmt = DAG.getShiftAmountConstant(Diff, VT, dl);
- // FIXME: There is no VP_SIGN_EXTEND_INREG so use a pair of shifts.
- SDValue Shl = DAG.getNode(ISD::VP_SHL, dl, VT, Op, ShAmt, N->getOperand(1),
- N->getOperand(2));
- return DAG.getNode(ISD::VP_SRA, dl, VT, Shl, ShAmt, N->getOperand(1),
- N->getOperand(2));
-}
-
SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
- if (N->getOpcode() == ISD::VP_SINT_TO_FP)
- return SDValue(DAG.UpdateNodeOperands(N,
- SExtPromotedInteger(N->getOperand(0)),
- N->getOperand(1), N->getOperand(2)),
- 0);
return SDValue(DAG.UpdateNodeOperands(N,
SExtPromotedInteger(N->getOperand(0))), 0);
}
@@ -2817,18 +2601,10 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_COMPRESS(SDNode *N,
SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
SDValue Op = GetPromotedInteger(N->getOperand(0));
- if (N->getOpcode() == ISD::VP_TRUNCATE)
- return DAG.getNode(ISD::VP_TRUNCATE, SDLoc(N), N->getValueType(0), Op,
- N->getOperand(1), N->getOperand(2));
return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
}
SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
- if (N->getOpcode() == ISD::VP_UINT_TO_FP)
- return SDValue(DAG.UpdateNodeOperands(N,
- ZExtPromotedInteger(N->getOperand(0)),
- N->getOperand(1), N->getOperand(2)),
- 0);
return SDValue(DAG.UpdateNodeOperands(N,
ZExtPromotedInteger(N->getOperand(0))), 0);
}
@@ -2864,17 +2640,6 @@ SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
return DAG.getZeroExtendInReg(Op, dl, Src.getValueType());
}
-SDValue DAGTypeLegalizer::PromoteIntOp_VP_ZERO_EXTEND(SDNode *N) {
- SDLoc dl(N);
- EVT VT = N->getValueType(0);
- SDValue Op = GetPromotedInteger(N->getOperand(0));
- // FIXME: There is no VP_ANY_EXTEND yet.
- Op = DAG.getNode(ISD::VP_ZERO_EXTEND, dl, VT, Op, N->getOperand(1),
- N->getOperand(2));
- return DAG.getVPZeroExtendInReg(Op, N->getOperand(1), N->getOperand(2), dl,
- N->getOperand(0).getValueType());
-}
-
SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
return SDValue(
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index ab252f5db2dcf..bc52b8357582c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -15,7 +15,6 @@
#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
#define LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
-#include "MatchContext.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLowering.h"
@@ -348,7 +347,6 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntRes_VAARG(SDNode *N);
SDValue PromoteIntRes_VSCALE(SDNode *N);
SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
- template <class MatchContextClass>
SDValue PromoteIntRes_ADDSUBSHLSAT(SDNode *N);
SDValue PromoteIntRes_MULFIX(SDNode *N);
SDValue PromoteIntRes_DIVFIX(SDNode *N);
@@ -358,7 +356,6 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntRes_ABS(SDNode *N);
SDValue PromoteIntRes_Rotate(SDNode *N);
SDValue PromoteIntRes_FunnelShift(SDNode *N);
- SDValue PromoteIntRes_VPFunnelShift(SDNode *N);
SDValue PromoteIntRes_CLMUL(SDNode *N);
SDValue PromoteIntRes_PEXT(SDNode *N);
SDValue PromoteIntRes_PDEP(SDNode *N);
@@ -396,7 +393,6 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntOp_CMP(SDNode *N);
SDValue PromoteIntOp_FunnelShift(SDNode *N);
SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
- SDValue PromoteIntOp_VP_SIGN_EXTEND(SDNode *N);
SDValue PromoteIntOp_SINT_TO_FP(SDNode *N);
SDValue PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N);
SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
@@ -405,7 +401,6 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N);
SDValue PromoteIntOp_CONVERT_FROM_ARBITRARY_FP(SDNode *N);
SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N);
- SDValue PromoteIntOp_VP_ZERO_EXTEND(SDNode *N);
SDValue PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
SDValue PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo);
SDValue PromoteIntOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index 0cff883f83186..8c252c3491540 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -555,7 +555,7 @@ void DAGTypeLegalizer::SplitRes_Select(SDNode *N, SDValue &Lo, SDValue &Hi) {
std::tie(CL, CH) = DAG.SplitVector(Cond, dl);
}
- if (Opcode != ISD::VP_SELECT && Opcode != ISD::VP_MERGE) {
+ if (Opcode != ISD::VP_MERGE) {
Lo = DAG.getNode(Opcode, dl, LL.getValueType(), CL, LL, RL);
Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH);
return;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index f85e6e58b88c8..787f2683080e2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -132,12 +132,8 @@ class VectorLegalizer {
/// Implement vselect in terms of XOR, AND, OR when blend is not
/// supported by the target.
SDValue ExpandVSELECT(SDNode *Node);
- SDValue ExpandVP_SELECT(SDNode *Node);
SDValue ExpandVP_MERGE(SDNode *Node);
SDValue ExpandVP_REM(SDNode *Node);
- SDValue ExpandVP_FNEG(SDNode *Node);
- SDValue ExpandVP_FABS(SDNode *Node);
- SDValue ExpandVP_FCOPYSIGN(SDNode *Node);
SDValue ExpandLOOP_DEPENDENCE_MASK(SDNode *N);
SDValue ExpandMaskedBinOp(SDNode *N);
SDValue ExpandSELECT(SDNode *Node);
@@ -558,12 +554,6 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::VPID: { \
EVT LegalizeVT = LEGALPOS < 0 ? Node->getValueType(-(1 + LEGALPOS)) \
: Node->getOperand(LEGALPOS).getValueType(); \
- if (ISD::VPID == ISD::VP_SETCC) { \
- ISD::CondCode CCCode = cast<CondCodeSDNode>(Node->getOperand(2))->get(); \
- Action = TLI.getCondCodeAction(CCCode, LegalizeVT.getSimpleVT()); \
- if (Action != TargetLowering::Legal) \
- break; \
- } \
/* Defer non-vector results to LegalizeDAG. */ \
if (!Node->getValueType(0).isVector() && \
Node->getValueType(0) != MVT::Other) { \
@@ -654,11 +644,6 @@ void VectorLegalizer::PromoteSETCC(SDNode *Node,
Operands[1] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(1));
Operands[2] = Node->getOperand(2);
- if (Node->getOpcode() == ISD::VP_SETCC) {
- Operands[3] = Node->getOperand(3); // mask
- Operands[4] = Node->getOperand(4); // evl
- }
-
EVT ResVT =
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), NewVecVT);
SDValue Res =
@@ -772,7 +757,6 @@ void VectorLegalizer::Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
// Promote the operation by extending the operand.
PromoteFP_TO_INT(Node, Results);
return;
- case ISD::VP_SETCC:
case ISD::SETCC:
// Promote the operation by extending the operand.
PromoteSETCC(Node, Results);
@@ -804,11 +788,6 @@ void VectorLegalizer::Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
// These operations are used to do promotion so they can't be promoted
// themselves.
llvm_unreachable("Don't know how to promote this operation!");
- case ISD::VP_FABS:
- case ISD::VP_FCOPYSIGN:
- case ISD::VP_FNEG:
- // Promoting fabs, fneg, and fcopysign changes their semantics.
- llvm_unreachable("These operations should not be promoted");
}
// There are currently two cases of vector promotion:
@@ -833,17 +812,7 @@ void VectorLegalizer::Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
.getVectorElementType()
.isFloatingPoint() &&
NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
- if (ISD::isVPOpcode(Node->getOpcode())) {
- unsigned EVLIdx =
- *ISD::getVPExplicitVectorLengthIdx(Node->getOpcode());
- unsigned MaskIdx = *ISD::getVPMaskIdx(Node->getOpcode());
- Operands[j] =
- DAG.getNode(ISD::VP_FP_EXTEND, dl, NVT, Node->getOperand(j),
- Node->getOperand(MaskIdx), Node->getOperand(EVLIdx));
- } else {
- Operands[j] =
- DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j));
- }
+ Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j));
else
Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(j));
else
@@ -856,15 +825,8 @@ void VectorLegalizer::Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
(VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
- if (ISD::isVPOpcode(Node->getOpcode())) {
- unsigned EVLIdx = *ISD::getVPExplicitVectorLengthIdx(Node->getOpcode());
- unsigned MaskIdx = *ISD::getVPMaskIdx(Node->getOpcode());
- Res = DAG.getNode(ISD::VP_FP_ROUND, dl, VT, Res,
- Node->getOperand(MaskIdx), Node->getOperand(EVLIdx));
- } else {
- Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res,
- DAG.getIntPtrConstant(0, dl, /*isTarget=*/true));
- }
+ Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res,
+ DAG.getIntPtrConstant(0, dl, /*isTarget=*/true));
else
Res = DAG.getNode(ISD::BITCAST, dl, VT, Res);
@@ -1004,21 +966,12 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
return;
}
break;
- case ISD::VP_BSWAP:
- Results.push_back(TLI.expandVPBSWAP(Node, DAG));
- return;
case ISD::VSELECT:
if (SDValue Expanded = ExpandVSELECT(Node)) {
Results.push_back(Expanded);
return;
}
break;
- case ISD::VP_SELECT:
- if (SDValue Expanded = ExpandVP_SELECT(Node)) {
- Results.push_back(Expanded);
- return;
- }
- break;
case ISD::VP_SREM:
case ISD::VP_UREM:
if (SDValue Expanded = ExpandVP_REM(Node)) {
@@ -1026,24 +979,6 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
return;
}
break;
- case ISD::VP_FNEG:
- if (SDValue Expanded = ExpandVP_FNEG(Node)) {
- Results.push_back(Expanded);
- return;
- }
- break;
- case ISD::VP_FABS:
- if (SDValue Expanded = ExpandVP_FABS(Node)) {
- Results.push_back(Expanded);
- return;
- }
- break;
- case ISD::VP_FCOPYSIGN:
- if (SDValue Expanded = ExpandVP_FCOPYSIGN(Node)) {
- Results.push_back(Expanded);
- return;
- }
- break;
case ISD::SELECT:
if (SDValue Expanded = ExpandSELECT(Node)) {
Results.push_back(Expanded);
@@ -1107,7 +1042,6 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
ExpandFSUB(Node, Results);
return;
case ISD::SETCC:
- case ISD::VP_SETCC:
ExpandSETCC(Node, Results);
return;
case ISD::ABS:
@@ -1139,24 +1073,12 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
return;
}
break;
- case ISD::VP_BITREVERSE:
- if (SDValue Expanded = TLI.expandVPBITREVERSE(Node, DAG)) {
- Results.push_back(Expanded);
- return;
- }
- break;
case ISD::CTPOP:
if (SDValue Expanded = TLI.expandCTPOP(Node, DAG)) {
Results.push_back(Expanded);
return;
}
break;
- case ISD::VP_CTPOP:
- if (SDValue Expanded = TLI.expandVPCTPOP(Node, DAG)) {
- Results.push_back(Expanded);
- return;
- }
- break;
case ISD::CTLZ:
case ISD::CTLZ_ZERO_POISON:
if (SDValue Expanded = TLI.expandCTLZ(Node, DAG)) {
@@ -1164,13 +1086,6 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
return;
}
break;
- case ISD::VP_CTLZ:
- case ISD::VP_CTLZ_ZERO_POISON:
- if (SDValue Expanded = TLI.expandVPCTLZ(Node, DAG)) {
- Results.push_back(Expanded);
- return;
- }
- break;
case ISD::CTTZ:
case ISD::CTTZ_ZERO_POISON:
if (SDValue Expanded = TLI.expandCTTZ(Node, DAG)) {
@@ -1178,17 +1093,8 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
return;
}
break;
- case ISD::VP_CTTZ:
- case ISD::VP_CTTZ_ZERO_POISON:
- if (SDValue Expanded = TLI.expandVPCTTZ(Node, DAG)) {
- Results.push_back(Expanded);
- return;
- }
- break;
case ISD::FSHL:
- case ISD::VP_FSHL:
case ISD::FSHR:
- case ISD::VP_FSHR:
if (SDValue Expanded = TLI.expandFunnelShift(Node, DAG)) {
Results.push_back(Expanded);
return;
@@ -1758,37 +1664,6 @@ SDValue VectorLegalizer::ExpandVSELECT(SDNode *Node) {
return DAG.getNode(ISD::BITCAST, DL, Node->getValueType(0), Val);
}
-SDValue VectorLegalizer::ExpandVP_SELECT(SDNode *Node) {
- // Implement VP_SELECT in terms of VP_XOR, VP_AND and VP_OR on platforms which
- // do not support it natively.
- SDLoc DL(Node);
-
- SDValue Mask = Node->getOperand(0);
- SDValue Op1 = Node->getOperand(1);
- SDValue Op2 = Node->getOperand(2);
- SDValue EVL = Node->getOperand(3);
-
- EVT VT = Mask.getValueType();
-
- // If we can't even use the basic vector operations of
- // VP_AND,VP_OR,VP_XOR, we will have to scalarize the op.
- if (TLI.getOperationAction(ISD::VP_AND, VT) == TargetLowering::Expand ||
- TLI.getOperationAction(ISD::VP_XOR, VT) == TargetLowering::Expand ||
- TLI.getOperationAction(ISD::VP_OR, VT) == TargetLowering::Expand)
- return SDValue();
-
- // This operation also isn't safe when the operands aren't also booleans.
- if (Op1.getValueType().getVectorElementType() != MVT::i1)
- return SDValue();
-
- SDValue Ones = DAG.getAllOnesConstant(DL, VT);
- SDValue NotMask = DAG.getNode(ISD::VP_XOR, DL, VT, Mask, Ones, Ones, EVL);
-
- Op1 = DAG.getNode(ISD::VP_AND, DL, VT, Op1, Mask, Ones, EVL);
- Op2 = DAG.getNode(ISD::VP_AND, DL, VT, Op2, NotMask, Ones, EVL);
- return DAG.getNode(ISD::VP_OR, DL, VT, Op1, Op2, Ones, EVL);
-}
-
SDValue VectorLegalizer::ExpandVP_MERGE(SDNode *Node) {
// Implement VP_MERGE in terms of VSELECT. Construct a mask where vector
// indices less than the EVL/pivot are true. Combine that with the original
@@ -1854,77 +1729,6 @@ SDValue VectorLegalizer::ExpandVP_REM(SDNode *Node) {
return DAG.getNode(ISD::SUB, DL, VT, Dividend, Mul);
}
-SDValue VectorLegalizer::ExpandVP_FNEG(SDNode *Node) {
- EVT VT = Node->getValueType(0);
- EVT IntVT = VT.changeVectorElementTypeToInteger();
-
- if (!TLI.isOperationLegalOrCustom(ISD::VP_XOR, IntVT))
- return SDValue();
-
- SDValue Mask = Node->getOperand(1);
- SDValue EVL = Node->getOperand(2);
-
- SDLoc DL(Node);
- SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
- SDValue SignMask = DAG.getConstant(
- APInt::getSignMask(IntVT.getScalarSizeInBits()), DL, IntVT);
- SDValue Xor = DAG.getNode(ISD::VP_XOR, DL, IntVT, Cast, SignMask, Mask, EVL);
- return DAG.getNode(ISD::BITCAST, DL, VT, Xor);
-}
-
-SDValue VectorLegalizer::ExpandVP_FABS(SDNode *Node) {
- EVT VT = Node->getValueType(0);
- EVT IntVT = VT.changeVectorElementTypeToInteger();
-
- if (!TLI.isOperationLegalOrCustom(ISD::VP_AND, IntVT))
- return SDValue();
-
- SDValue Mask = Node->getOperand(1);
- SDValue EVL = Node->getOperand(2);
-
- SDLoc DL(Node);
- SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
- SDValue ClearSignMask = DAG.getConstant(
- APInt::getSignedMaxValue(IntVT.getScalarSizeInBits()), DL, IntVT);
- SDValue ClearSign =
- DAG.getNode(ISD::VP_AND, DL, IntVT, Cast, ClearSignMask, Mask, EVL);
- return DAG.getNode(ISD::BITCAST, DL, VT, ClearSign);
-}
-
-SDValue VectorLegalizer::ExpandVP_FCOPYSIGN(SDNode *Node) {
- EVT VT = Node->getValueType(0);
-
- if (VT != Node->getOperand(1).getValueType())
- return SDValue();
-
- EVT IntVT = VT.changeVectorElementTypeToInteger();
- if (!TLI.isOperationLegalOrCustom(ISD::VP_AND, IntVT) ||
- !TLI.isOperationLegalOrCustom(ISD::VP_XOR, IntVT))
- return SDValue();
-
- SDValue Mask = Node->getOperand(2);
- SDValue EVL = Node->getOperand(3);
-
- SDLoc DL(Node);
- SDValue Mag = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
- SDValue Sign = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(1));
-
- SDValue SignMask = DAG.getConstant(
- APInt::getSignMask(IntVT.getScalarSizeInBits()), DL, IntVT);
- SDValue SignBit =
- DAG.getNode(ISD::VP_AND, DL, IntVT, Sign, SignMask, Mask, EVL);
-
- SDValue ClearSignMask = DAG.getConstant(
- APInt::getSignedMaxValue(IntVT.getScalarSizeInBits()), DL, IntVT);
- SDValue ClearedSign =
- DAG.getNode(ISD::VP_AND, DL, IntVT, Mag, ClearSignMask, Mask, EVL);
-
- SDValue CopiedSign = DAG.getNode(ISD::VP_OR, DL, IntVT, ClearedSign, SignBit,
- Mask, EVL, SDNodeFlags::Disjoint);
-
- return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);
-}
-
SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {
return TLI.expandLoopDependenceMask(N, DAG);
}
@@ -2215,7 +2019,6 @@ void VectorLegalizer::ExpandFSUB(SDNode *Node,
void VectorLegalizer::ExpandSETCC(SDNode *Node,
SmallVectorImpl<SDValue> &Results) {
bool NeedInvert = false;
- bool IsVP = Node->getOpcode() == ISD::VP_SETCC;
bool IsStrict = Node->getOpcode() == ISD::STRICT_FSETCC ||
Node->getOpcode() == ISD::STRICT_FSETCCS;
bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS;
@@ -2238,16 +2041,10 @@ void VectorLegalizer::ExpandSETCC(SDNode *Node,
return;
}
- SDValue Mask, EVL;
- if (IsVP) {
- Mask = Node->getOperand(3 + Offset);
- EVL = Node->getOperand(4 + Offset);
- }
-
SDLoc dl(Node);
bool Legalized =
- TLI.LegalizeSetCCCondCode(DAG, Node->getValueType(0), LHS, RHS, CC, Mask,
- EVL, NeedInvert, dl, Chain, IsSignaling);
+ TLI.LegalizeSetCCCondCode(DAG, Node->getValueType(0), LHS, RHS, CC,
+ NeedInvert, dl, Chain, IsSignaling);
if (Legalized) {
// If we expanded the SETCC by swapping LHS and RHS, or by inverting the
@@ -2257,9 +2054,6 @@ void VectorLegalizer::ExpandSETCC(SDNode *Node,
LHS = DAG.getNode(Node->getOpcode(), dl, Node->getVTList(),
{Chain, LHS, RHS, CC}, Node->getFlags());
Chain = LHS.getValue(1);
- } else if (IsVP) {
- LHS = DAG.getNode(ISD::VP_SETCC, dl, Node->getValueType(0),
- {LHS, RHS, CC, Mask, EVL}, Node->getFlags());
} else {
LHS = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), LHS, RHS, CC,
Node->getFlags());
@@ -2268,12 +2062,8 @@ void VectorLegalizer::ExpandSETCC(SDNode *Node,
// If we expanded the SETCC by inverting the condition code, then wrap
// the existing SETCC in a NOT to restore the intended condition.
- if (NeedInvert) {
- if (!IsVP)
- LHS = DAG.getLogicalNOT(dl, LHS, LHS->getValueType(0));
- else
- LHS = DAG.getVPLogicalNOT(dl, LHS, Mask, EVL, LHS->getValueType(0));
- }
+ if (NeedInvert)
+ LHS = DAG.getLogicalNOT(dl, LHS, LHS->getValueType(0));
} else {
assert(!IsStrict && "Don't know how to expand for strict nodes.");
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 3417c9734af3b..35ab9c930213d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1396,8 +1396,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::AssertSext: SplitVecRes_AssertSext(N, Lo, Hi); break;
case ISD::VSELECT:
case ISD::SELECT:
- case ISD::VP_MERGE:
- case ISD::VP_SELECT: SplitRes_Select(N, Lo, Hi); break;
+ case ISD::VP_MERGE: SplitRes_Select(N, Lo, Hi); break;
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
case ISD::POISON:
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
@@ -1445,7 +1444,6 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
SplitVecRes_VECTOR_COMPRESS(N, Lo, Hi);
break;
case ISD::SETCC:
- case ISD::VP_SETCC:
SplitVecRes_SETCC(N, Lo, Hi);
break;
case ISD::VECTOR_REVERSE:
@@ -1476,75 +1474,51 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ABS:
case ISD::ABS_MIN_POISON:
- case ISD::VP_ABS:
case ISD::BITREVERSE:
- case ISD::VP_BITREVERSE:
case ISD::BSWAP:
- case ISD::VP_BSWAP:
case ISD::CTLZ:
- case ISD::VP_CTLZ:
case ISD::CTTZ:
- case ISD::VP_CTTZ:
case ISD::CTLZ_ZERO_POISON:
- case ISD::VP_CTLZ_ZERO_POISON:
case ISD::CTTZ_ZERO_POISON:
- case ISD::VP_CTTZ_ZERO_POISON:
case ISD::CTPOP:
- case ISD::VP_CTPOP:
- case ISD::FABS: case ISD::VP_FABS:
+ case ISD::FABS:
case ISD::FACOS:
case ISD::FASIN:
case ISD::FATAN:
case ISD::FCEIL:
- case ISD::VP_FCEIL:
case ISD::FCOS:
case ISD::FCOSH:
case ISD::FEXP:
case ISD::FEXP2:
case ISD::FEXP10:
case ISD::FFLOOR:
- case ISD::VP_FFLOOR:
case ISD::FLOG:
case ISD::FLOG10:
case ISD::FLOG2:
case ISD::FNEARBYINT:
- case ISD::VP_FNEARBYINT:
- case ISD::FNEG: case ISD::VP_FNEG:
+ case ISD::FNEG:
case ISD::FREEZE:
case ISD::ARITH_FENCE:
case ISD::FP_EXTEND:
- case ISD::VP_FP_EXTEND:
case ISD::FP_ROUND:
- case ISD::VP_FP_ROUND:
case ISD::FP_TO_SINT:
- case ISD::VP_FP_TO_SINT:
case ISD::FP_TO_UINT:
- case ISD::VP_FP_TO_UINT:
case ISD::FRINT:
- case ISD::VP_FRINT:
case ISD::LRINT:
- case ISD::VP_LRINT:
case ISD::LLRINT:
- case ISD::VP_LLRINT:
case ISD::FROUND:
- case ISD::VP_FROUND:
case ISD::FROUNDEVEN:
- case ISD::VP_FROUNDEVEN:
case ISD::LROUND:
case ISD::LLROUND:
case ISD::FSIN:
case ISD::FSINH:
- case ISD::FSQRT: case ISD::VP_SQRT:
+ case ISD::FSQRT:
case ISD::FTAN:
case ISD::FTANH:
case ISD::FTRUNC:
- case ISD::VP_FROUNDTOZERO:
case ISD::SINT_TO_FP:
- case ISD::VP_SINT_TO_FP:
case ISD::TRUNCATE:
- case ISD::VP_TRUNCATE:
case ISD::UINT_TO_FP:
- case ISD::VP_UINT_TO_FP:
case ISD::FCANONICALIZE:
case ISD::AssertNoFPClass:
case ISD::CONVERT_FROM_ARBITRARY_FP:
@@ -1564,14 +1538,12 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ANY_EXTEND:
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND:
- case ISD::VP_SIGN_EXTEND:
- case ISD::VP_ZERO_EXTEND:
SplitVecRes_ExtendOp(N, Lo, Hi);
break;
- case ISD::ADD: case ISD::VP_ADD:
- case ISD::SUB: case ISD::VP_SUB:
- case ISD::MUL: case ISD::VP_MUL:
+ case ISD::ADD:
+ case ISD::SUB:
+ case ISD::MUL:
case ISD::CLMUL:
case ISD::CLMULR:
case ISD::CLMULH:
@@ -1585,48 +1557,43 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::AVGCEILU:
case ISD::AVGFLOORS:
case ISD::AVGFLOORU:
- case ISD::FADD: case ISD::VP_FADD:
- case ISD::FSUB: case ISD::VP_FSUB:
- case ISD::FMUL: case ISD::VP_FMUL:
+ case ISD::FADD:
+ case ISD::FSUB:
+ case ISD::FMUL:
case ISD::FMINNUM:
case ISD::FMINNUM_IEEE:
- case ISD::VP_FMINNUM:
case ISD::FMAXNUM:
case ISD::FMAXNUM_IEEE:
- case ISD::VP_FMAXNUM:
case ISD::FMINIMUM:
- case ISD::VP_FMINIMUM:
case ISD::FMAXIMUM:
- case ISD::VP_FMAXIMUM:
case ISD::FMINIMUMNUM:
case ISD::FMAXIMUMNUM:
case ISD::SDIV: case ISD::VP_SDIV:
case ISD::UDIV: case ISD::VP_UDIV:
- case ISD::FDIV: case ISD::VP_FDIV:
+ case ISD::FDIV:
case ISD::FPOW:
case ISD::FATAN2:
- case ISD::AND: case ISD::VP_AND:
- case ISD::OR: case ISD::VP_OR:
- case ISD::XOR: case ISD::VP_XOR:
- case ISD::SHL: case ISD::VP_SHL:
- case ISD::SRA: case ISD::VP_SRA:
- case ISD::SRL: case ISD::VP_SRL:
+ case ISD::AND:
+ case ISD::OR:
+ case ISD::XOR:
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::SRL:
case ISD::UREM: case ISD::VP_UREM:
case ISD::SREM: case ISD::VP_SREM:
- case ISD::FREM: case ISD::VP_FREM:
- case ISD::SMIN: case ISD::VP_SMIN:
- case ISD::SMAX: case ISD::VP_SMAX:
- case ISD::UMIN: case ISD::VP_UMIN:
- case ISD::UMAX: case ISD::VP_UMAX:
- case ISD::SADDSAT: case ISD::VP_SADDSAT:
- case ISD::UADDSAT: case ISD::VP_UADDSAT:
- case ISD::SSUBSAT: case ISD::VP_SSUBSAT:
- case ISD::USUBSAT: case ISD::VP_USUBSAT:
+ case ISD::FREM:
+ case ISD::SMIN:
+ case ISD::SMAX:
+ case ISD::UMIN:
+ case ISD::UMAX:
+ case ISD::SADDSAT:
+ case ISD::UADDSAT:
+ case ISD::SSUBSAT:
+ case ISD::USUBSAT:
case ISD::SSHLSAT:
case ISD::USHLSAT:
case ISD::ROTL:
case ISD::ROTR:
- case ISD::VP_FCOPYSIGN:
SplitVecRes_BinOp(N, Lo, Hi);
break;
case ISD::MASKED_UDIV:
@@ -1635,11 +1602,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::MASKED_SREM:
SplitVecRes_MaskedBinOp(N, Lo, Hi);
break;
- case ISD::FMA: case ISD::VP_FMA:
+ case ISD::FMA:
case ISD::FSHL:
- case ISD::VP_FSHL:
case ISD::FSHR:
- case ISD::VP_FSHR:
SplitVecRes_TernaryOp(N, Lo, Hi);
break;
@@ -1754,7 +1719,9 @@ void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi) {
}
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
+ assert((N->getOpcode() == ISD::VP_UDIV || N->getOpcode() == ISD::VP_SDIV ||
+ N->getOpcode() == ISD::VP_UREM || N->getOpcode() == ISD::VP_SREM) &&
+ "Expected VP opcode");
SDValue MaskLo, MaskHi;
std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(2));
@@ -1804,26 +1771,10 @@ void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
const SDNodeFlags Flags = N->getFlags();
unsigned Opcode = N->getOpcode();
- if (N->getNumOperands() == 3) {
- Lo = DAG.getNode(Opcode, dl, Op0Lo.getValueType(), Op0Lo, Op1Lo, Op2Lo, Flags);
- Hi = DAG.getNode(Opcode, dl, Op0Hi.getValueType(), Op0Hi, Op1Hi, Op2Hi, Flags);
- return;
- }
-
- assert(N->getNumOperands() == 5 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
-
- SDValue MaskLo, MaskHi;
- std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3));
-
- SDValue EVLLo, EVLHi;
- std::tie(EVLLo, EVLHi) =
- DAG.SplitEVL(N->getOperand(4), N->getValueType(0), dl);
-
- Lo = DAG.getNode(Opcode, dl, Op0Lo.getValueType(),
- {Op0Lo, Op1Lo, Op2Lo, MaskLo, EVLLo}, Flags);
- Hi = DAG.getNode(Opcode, dl, Op0Hi.getValueType(),
- {Op0Hi, Op1Hi, Op2Hi, MaskHi, EVLHi}, Flags);
+ Lo =
+ DAG.getNode(Opcode, dl, Op0Lo.getValueType(), Op0Lo, Op1Lo, Op2Lo, Flags);
+ Hi =
+ DAG.getNode(Opcode, dl, Op0Hi.getValueType(), Op0Hi, Op1Hi, Op2Hi, Flags);
}
void DAGTypeLegalizer::SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
@@ -2981,20 +2932,8 @@ void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
else
std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
- if (N->getOpcode() == ISD::SETCC) {
- Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
- Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
- } else {
- assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
- SDValue MaskLo, MaskHi, EVLLo, EVLHi;
- std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3));
- std::tie(EVLLo, EVLHi) =
- DAG.SplitEVL(N->getOperand(4), N->getValueType(0), DL);
- Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2), MaskLo,
- EVLLo);
- Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2), MaskHi,
- EVLHi);
- }
+ Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
+ Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
}
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
@@ -3021,30 +2960,15 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
N->getOperand(3), Flags);
return;
}
- if (N->getNumOperands() <= 2) {
- if (Opcode == ISD::FP_ROUND || Opcode == ISD::AssertNoFPClass ||
- Opcode == ISD::CONVERT_FROM_ARBITRARY_FP) {
- Lo = DAG.getNode(Opcode, dl, LoVT, Lo, N->getOperand(1), Flags);
- Hi = DAG.getNode(Opcode, dl, HiVT, Hi, N->getOperand(1), Flags);
- } else {
- Lo = DAG.getNode(Opcode, dl, LoVT, Lo, Flags);
- Hi = DAG.getNode(Opcode, dl, HiVT, Hi, Flags);
- }
- return;
- }
- assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
-
- SDValue MaskLo, MaskHi;
- std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
-
- SDValue EVLLo, EVLHi;
- std::tie(EVLLo, EVLHi) =
- DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
-
- Lo = DAG.getNode(Opcode, dl, LoVT, {Lo, MaskLo, EVLLo}, Flags);
- Hi = DAG.getNode(Opcode, dl, HiVT, {Hi, MaskHi, EVLHi}, Flags);
+ if (Opcode == ISD::FP_ROUND || Opcode == ISD::AssertNoFPClass ||
+ Opcode == ISD::CONVERT_FROM_ARBITRARY_FP) {
+ Lo = DAG.getNode(Opcode, dl, LoVT, Lo, N->getOperand(1), Flags);
+ Hi = DAG.getNode(Opcode, dl, HiVT, Hi, N->getOperand(1), Flags);
+ } else {
+ Lo = DAG.getNode(Opcode, dl, LoVT, Lo, Flags);
+ Hi = DAG.getNode(Opcode, dl, HiVT, Hi, Flags);
+ }
}
void DAGTypeLegalizer::SplitVecRes_ADDRSPACECAST(SDNode *N, SDValue &Lo,
@@ -3135,35 +3059,15 @@ void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
LLVM_DEBUG(dbgs() << "Split vector extend via incremental extend:";
- N->dump(&DAG); dbgs() << "\n");
- if (!N->isVPOpcode()) {
- // Extend the source vector by one step.
- SDValue NewSrc =
- DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
- // Get the low and high halves of the new, extended one step, vector.
- std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
- // Extend those vector halves the rest of the way.
- Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
- Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
- return;
- }
-
+ N->dump(&DAG); dbgs() << "\n");
// Extend the source vector by one step.
SDValue NewSrc =
- DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0),
- N->getOperand(1), N->getOperand(2));
+ DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
// Get the low and high halves of the new, extended one step, vector.
std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
-
- SDValue MaskLo, MaskHi;
- std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
-
- SDValue EVLLo, EVLHi;
- std::tie(EVLLo, EVLHi) =
- DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
// Extend those vector halves the rest of the way.
- Lo = DAG.getNode(N->getOpcode(), dl, LoVT, {Lo, MaskLo, EVLLo});
- Hi = DAG.getNode(N->getOpcode(), dl, HiVT, {Hi, MaskHi, EVLHi});
+ Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
+ Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
return;
}
}
@@ -3870,7 +3774,6 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
report_fatal_error("Do not know how to split this operator's "
"operand!\n");
- case ISD::VP_SETCC:
case ISD::STRICT_FSETCC:
case ISD::STRICT_FSETCCS:
case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
@@ -3882,12 +3785,10 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::VECTOR_FIND_LAST_ACTIVE:
Res = SplitVecOp_VECTOR_FIND_LAST_ACTIVE(N);
break;
- case ISD::VP_TRUNCATE:
case ISD::TRUNCATE:
Res = SplitVecOp_TruncateHelper(N);
break;
case ISD::STRICT_FP_ROUND:
- case ISD::VP_FP_ROUND:
case ISD::FP_ROUND:
case ISD::CONVERT_FROM_ARBITRARY_FP:
case ISD::CONVERT_TO_ARBITRARY_FP:
@@ -3933,8 +3834,6 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::STRICT_UINT_TO_FP:
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
- case ISD::VP_SINT_TO_FP:
- case ISD::VP_UINT_TO_FP:
if (N->getValueType(0).bitsLT(
N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType()))
Res = SplitVecOp_TruncateHelper(N);
@@ -3947,8 +3846,6 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
- case ISD::VP_FP_TO_SINT:
- case ISD::VP_FP_TO_UINT:
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::STRICT_FP_EXTEND:
@@ -4247,14 +4144,6 @@ SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
// Legalize the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), Ch);
- } else if (N->getNumOperands() == 3) {
- assert(N->isVPOpcode() && "Expected VP opcode");
- SDValue MaskLo, MaskHi, EVLLo, EVLHi;
- std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
- std::tie(EVLLo, EVLHi) =
- DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
- Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo, MaskLo, EVLLo);
- Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi, MaskHi, EVLHi);
} else {
Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
@@ -5050,7 +4939,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
if (Opc == ISD::SETCC) {
LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
- } else if (isStrict) {
+ } else {
+ assert(isStrict && "unexpected node");
LoRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)),
N->getOperand(0), Lo0, Lo1, N->getOperand(3));
HiRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)),
@@ -5058,16 +4948,6 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
LoRes.getValue(1), HiRes.getValue(1));
ReplaceValueWith(SDValue(N, 1), NewChain);
- } else {
- assert(Opc == ISD::VP_SETCC && "Expected VP_SETCC opcode");
- SDValue MaskLo, MaskHi, EVLLo, EVLHi;
- std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3));
- std::tie(EVLLo, EVLHi) =
- DAG.SplitEVL(N->getOperand(4), N->getValueType(0), DL);
- LoRes = DAG.getNode(ISD::VP_SETCC, DL, PartResVT, Lo0, Lo1,
- N->getOperand(2), MaskLo, EVLLo);
- HiRes = DAG.getNode(ISD::VP_SETCC, DL, PartResVT, Hi0, Hi1,
- N->getOperand(2), MaskHi, EVLHi);
}
EVT ConcatVT = PartResVT.getDoubleNumVectorElementsVT(*DAG.getContext());
@@ -5103,13 +4983,6 @@ SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
Lo.getValue(1), Hi.getValue(1));
ReplaceValueWith(SDValue(N, 1), NewChain);
- } else if (N->getOpcode() == ISD::VP_FP_ROUND) {
- SDValue MaskLo, MaskHi, EVLLo, EVLHi;
- std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
- std::tie(EVLLo, EVLHi) =
- DAG.SplitEVL(N->getOperand(2), N->getValueType(0), DL);
- Lo = DAG.getNode(ISD::VP_FP_ROUND, DL, OutVT, Lo, MaskLo, EVLLo);
- Hi = DAG.getNode(ISD::VP_FP_ROUND, DL, OutVT, Hi, MaskHi, EVLHi);
} else if (N->getOpcode() == ISD::CONVERT_TO_ARBITRARY_FP) {
Lo = DAG.getNode(N->getOpcode(), DL, OutVT, Lo, N->getOperand(1),
N->getOperand(2), N->getOperand(3));
@@ -5388,12 +5261,10 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
case ISD::VSELECT:
case ISD::SELECT:
- case ISD::VP_SELECT:
case ISD::VP_MERGE:
Res = WidenVecRes_Select(N);
break;
case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
- case ISD::VP_SETCC:
case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
case ISD::POISON:
case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
@@ -5437,19 +5308,19 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
WidenVecRes_VECTOR_DEINTERLEAVE(N);
break;
- case ISD::ADD: case ISD::VP_ADD:
- case ISD::AND: case ISD::VP_AND:
- case ISD::MUL: case ISD::VP_MUL:
+ case ISD::ADD:
+ case ISD::AND:
+ case ISD::MUL:
case ISD::MULHS:
case ISD::MULHU:
case ISD::ABDS:
case ISD::ABDU:
- case ISD::OR: case ISD::VP_OR:
- case ISD::SUB: case ISD::VP_SUB:
- case ISD::XOR: case ISD::VP_XOR:
- case ISD::SHL: case ISD::VP_SHL:
- case ISD::SRA: case ISD::VP_SRA:
- case ISD::SRL: case ISD::VP_SRL:
+ case ISD::OR:
+ case ISD::SUB:
+ case ISD::XOR:
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::SRL:
case ISD::CLMUL:
case ISD::CLMULR:
case ISD::CLMULH:
@@ -5457,24 +5328,20 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::PDEP:
case ISD::FMINNUM:
case ISD::FMINNUM_IEEE:
- case ISD::VP_FMINNUM:
case ISD::FMAXNUM:
case ISD::FMAXNUM_IEEE:
- case ISD::VP_FMAXNUM:
case ISD::FMINIMUM:
- case ISD::VP_FMINIMUM:
case ISD::FMAXIMUM:
- case ISD::VP_FMAXIMUM:
case ISD::FMINIMUMNUM:
case ISD::FMAXIMUMNUM:
- case ISD::SMIN: case ISD::VP_SMIN:
- case ISD::SMAX: case ISD::VP_SMAX:
- case ISD::UMIN: case ISD::VP_UMIN:
- case ISD::UMAX: case ISD::VP_UMAX:
- case ISD::UADDSAT: case ISD::VP_UADDSAT:
- case ISD::SADDSAT: case ISD::VP_SADDSAT:
- case ISD::USUBSAT: case ISD::VP_USUBSAT:
- case ISD::SSUBSAT: case ISD::VP_SSUBSAT:
+ case ISD::SMIN:
+ case ISD::SMAX:
+ case ISD::UMIN:
+ case ISD::UMAX:
+ case ISD::UADDSAT:
+ case ISD::SADDSAT:
+ case ISD::USUBSAT:
+ case ISD::SSUBSAT:
case ISD::SSHLSAT:
case ISD::USHLSAT:
case ISD::ROTL:
@@ -5492,12 +5359,6 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::VP_UDIV:
case ISD::VP_SREM:
case ISD::VP_UREM:
- case ISD::VP_FADD:
- case ISD::VP_FSUB:
- case ISD::VP_FMUL:
- case ISD::VP_FDIV:
- case ISD::VP_FREM:
- case ISD::VP_FCOPYSIGN:
Res = WidenVecRes_Binary(N);
break;
@@ -5581,23 +5442,14 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ANY_EXTEND:
case ISD::FP_EXTEND:
- case ISD::VP_FP_EXTEND:
case ISD::FP_ROUND:
- case ISD::VP_FP_ROUND:
case ISD::FP_TO_SINT:
- case ISD::VP_FP_TO_SINT:
case ISD::FP_TO_UINT:
- case ISD::VP_FP_TO_UINT:
case ISD::SIGN_EXTEND:
- case ISD::VP_SIGN_EXTEND:
case ISD::SINT_TO_FP:
- case ISD::VP_SINT_TO_FP:
- case ISD::VP_TRUNCATE:
case ISD::TRUNCATE:
case ISD::UINT_TO_FP:
- case ISD::VP_UINT_TO_FP:
case ISD::ZERO_EXTEND:
- case ISD::VP_ZERO_EXTEND:
case ISD::CONVERT_FROM_ARBITRARY_FP:
case ISD::CONVERT_TO_ARBITRARY_FP:
Res = WidenVecRes_Convert(N);
@@ -5610,8 +5462,6 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::LRINT:
case ISD::LLRINT:
- case ISD::VP_LRINT:
- case ISD::VP_LLRINT:
case ISD::LROUND:
case ISD::LLROUND:
Res = WidenVecRes_XROUND(N);
@@ -5649,42 +5499,24 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ABS:
case ISD::ABS_MIN_POISON:
- case ISD::VP_ABS:
case ISD::BITREVERSE:
- case ISD::VP_BITREVERSE:
case ISD::BSWAP:
- case ISD::VP_BSWAP:
case ISD::CTLZ:
- case ISD::VP_CTLZ:
case ISD::CTLZ_ZERO_POISON:
- case ISD::VP_CTLZ_ZERO_POISON:
case ISD::CTPOP:
- case ISD::VP_CTPOP:
case ISD::CTTZ:
- case ISD::VP_CTTZ:
case ISD::CTTZ_ZERO_POISON:
- case ISD::VP_CTTZ_ZERO_POISON:
- case ISD::FNEG: case ISD::VP_FNEG:
- case ISD::FABS: case ISD::VP_FABS:
- case ISD::VP_SQRT:
- case ISD::VP_FCEIL:
- case ISD::VP_FFLOOR:
- case ISD::VP_FRINT:
- case ISD::VP_FNEARBYINT:
- case ISD::VP_FROUND:
- case ISD::VP_FROUNDEVEN:
- case ISD::VP_FROUNDTOZERO:
+ case ISD::FNEG:
+ case ISD::FABS:
case ISD::FREEZE:
case ISD::ARITH_FENCE:
case ISD::FCANONICALIZE:
case ISD::AssertNoFPClass:
Res = WidenVecRes_Unary(N);
break;
- case ISD::FMA: case ISD::VP_FMA:
+ case ISD::FMA:
case ISD::FSHL:
- case ISD::VP_FSHL:
case ISD::FSHR:
- case ISD::VP_FSHR:
Res = WidenVecRes_Ternary(N);
break;
case ISD::FMODF:
@@ -5709,16 +5541,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
SDValue InOp1 = GetWidenedVector(N->getOperand(0));
SDValue InOp2 = GetWidenedVector(N->getOperand(1));
SDValue InOp3 = GetWidenedVector(N->getOperand(2));
- if (N->getNumOperands() == 3)
- return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
-
- assert(N->getNumOperands() == 5 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
-
- SDValue Mask =
- GetWidenedMask(N->getOperand(3), WidenVT.getVectorElementCount());
- return DAG.getNode(N->getOpcode(), dl, WidenVT,
- {InOp1, InOp2, InOp3, Mask, N->getOperand(4)});
+ return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
}
SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
@@ -5732,7 +5555,9 @@ SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
N->getFlags());
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
+ assert((N->getOpcode() == ISD::VP_UDIV || N->getOpcode() == ISD::VP_SDIV ||
+ N->getOpcode() == ISD::VP_UREM || N->getOpcode() == ISD::VP_SREM) &&
+ "Expected VP opcode");
SDValue Mask =
GetWidenedMask(N->getOperand(2), WidenVT.getVectorElementCount());
@@ -6184,14 +6009,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
InOp = GetWidenedVector(N->getOperand(0));
InVT = InOp.getValueType();
InVTEC = InVT.getVectorElementCount();
- if (InVTEC == WidenEC) {
- if (N->getNumOperands() == 3 && N->isVPOpcode()) {
- SDValue Mask =
- GetWidenedMask(N->getOperand(1), WidenVT.getVectorElementCount());
- return DAG.getNode(Opcode, DL, WidenVT, InOp, Mask, N->getOperand(2));
- }
+ if (InVTEC == WidenEC)
return MakeConvertNode(WidenVT, InOp);
- }
if (WidenVT.getSizeInBits() == InVT.getSizeInBits()) {
// If both input and result vector types are of same width, extend
// operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
@@ -6296,15 +6115,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_XROUND(SDNode *N) {
if (WidenNumElts != SrcVT.getVectorElementCount())
return DAG.UnrollVectorOp(N, WidenNumElts.getKnownMinValue());
- if (N->getNumOperands() == 1)
- return DAG.getNode(N->getOpcode(), dl, WidenVT, Src);
-
- assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
-
- SDValue Mask =
- GetWidenedMask(N->getOperand(1), WidenVT.getVectorElementCount());
- return DAG.getNode(N->getOpcode(), dl, WidenVT, Src, Mask, N->getOperand(2));
+ return DAG.getNode(N->getOpcode(), dl, WidenVT, Src);
}
SDValue DAGTypeLegalizer::WidenVecRes_Convert_StrictFP(SDNode *N) {
@@ -6438,17 +6249,9 @@ SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
SDValue InOp = GetWidenedVector(N->getOperand(0));
if (N->getNumOperands() == 1)
return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, N->getFlags());
- if (N->getOpcode() == ISD::AssertNoFPClass)
- return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp,
- N->getOperand(1), N->getFlags());
-
- assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
- assert(N->isVPOpcode() && "Expected VP opcode");
-
- SDValue Mask =
- GetWidenedMask(N->getOperand(1), WidenVT.getVectorElementCount());
- return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT,
- {InOp, Mask, N->getOperand(2)});
+ assert(N->getOpcode() == ISD::AssertNoFPClass && "unexpected opcode");
+ return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, N->getOperand(1),
+ N->getFlags());
}
SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
@@ -7500,7 +7303,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Select(SDNode *N) {
SDValue InOp1 = GetWidenedVector(N->getOperand(1));
SDValue InOp2 = GetWidenedVector(N->getOperand(2));
assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
- if (Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE)
+ if (Opcode == ISD::VP_MERGE)
return DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2,
N->getOperand(3));
return DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2);
@@ -7728,12 +7531,6 @@ SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
InOp2.getValueType() == WidenInVT &&
"Input not widened to expected type!");
(void)WidenInVT;
- if (N->getOpcode() == ISD::VP_SETCC) {
- SDValue Mask =
- GetWidenedMask(N->getOperand(3), WidenVT.getVectorElementCount());
- return DAG.getNode(ISD::VP_SETCC, SDLoc(N), WidenVT, InOp1, InOp2,
- N->getOperand(2), Mask, N->getOperand(4));
- }
return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT, InOp1, InOp2,
N->getOperand(2));
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/MatchContext.h b/llvm/lib/CodeGen/SelectionDAG/MatchContext.h
deleted file mode 100644
index ff564c0be40c4..0000000000000
--- a/llvm/lib/CodeGen/SelectionDAG/MatchContext.h
+++ /dev/null
@@ -1,182 +0,0 @@
-//===---------------- llvm/CodeGen/MatchContext.h --------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares the EmptyMatchContext class and VPMatchContext class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_MATCHCONTEXT_H
-#define LLVM_LIB_CODEGEN_SELECTIONDAG_MATCHCONTEXT_H
-
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/TargetLowering.h"
-
-namespace llvm {
-
-class EmptyMatchContext {
- SelectionDAG &DAG;
- const TargetLowering &TLI;
- SDNode *Root;
-
-public:
- EmptyMatchContext(SelectionDAG &DAG, const TargetLowering &TLI, SDNode *Root)
- : DAG(DAG), TLI(TLI), Root(Root) {}
-
- unsigned getRootBaseOpcode() { return Root->getOpcode(); }
- bool match(SDValue OpN, unsigned Opcode) const {
- return Opcode == OpN->getOpcode();
- }
-
- // Same as SelectionDAG::getNode().
- template <typename... ArgT> SDValue getNode(ArgT &&...Args) {
- return DAG.getNode(std::forward<ArgT>(Args)...);
- }
-
- bool isOperationLegal(unsigned Op, EVT VT) const {
- return TLI.isOperationLegal(Op, VT);
- }
-
- bool isOperationLegalOrCustom(unsigned Op, EVT VT,
- bool LegalOnly = false) const {
- return TLI.isOperationLegalOrCustom(Op, VT, LegalOnly);
- }
-
- unsigned getNumOperands(SDValue N) const { return N->getNumOperands(); }
-};
-
-class VPMatchContext {
- SelectionDAG &DAG;
- const TargetLowering &TLI;
- SDValue RootMaskOp;
- SDValue RootVectorLenOp;
- SDNode *Root;
-
-public:
- VPMatchContext(SelectionDAG &DAG, const TargetLowering &TLI, SDNode *_Root)
- : DAG(DAG), TLI(TLI), RootMaskOp(), RootVectorLenOp() {
- Root = _Root;
- assert(Root->isVPOpcode());
- if (auto RootMaskPos = ISD::getVPMaskIdx(Root->getOpcode()))
- RootMaskOp = Root->getOperand(*RootMaskPos);
- else if (Root->getOpcode() == ISD::VP_SELECT)
- RootMaskOp = DAG.getAllOnesConstant(SDLoc(Root),
- Root->getOperand(0).getValueType());
-
- if (auto RootVLenPos = ISD::getVPExplicitVectorLengthIdx(Root->getOpcode()))
- RootVectorLenOp = Root->getOperand(*RootVLenPos);
- }
-
- unsigned getRootBaseOpcode() {
- std::optional<unsigned> Opcode = ISD::getBaseOpcodeForVP(
- Root->getOpcode(), !Root->getFlags().hasNoFPExcept());
- assert(Opcode.has_value());
- return *Opcode;
- }
-
- /// whether \p OpVal is a node that is functionally compatible with the
- /// NodeType \p Opc
- bool match(SDValue OpVal, unsigned Opc) const {
- if (!OpVal->isVPOpcode())
- return OpVal->getOpcode() == Opc;
-
- auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(),
- !OpVal->getFlags().hasNoFPExcept());
- if (BaseOpc != Opc)
- return false;
-
- // Make sure the mask of OpVal is true mask or is same as Root's.
- unsigned VPOpcode = OpVal->getOpcode();
- if (auto MaskPos = ISD::getVPMaskIdx(VPOpcode)) {
- SDValue MaskOp = OpVal.getOperand(*MaskPos);
- if (RootMaskOp != MaskOp &&
- !ISD::isConstantSplatVectorAllOnes(MaskOp.getNode()))
- return false;
- }
-
- // Make sure the EVL of OpVal is same as Root's.
- if (auto VLenPos = ISD::getVPExplicitVectorLengthIdx(VPOpcode))
- if (RootVectorLenOp != OpVal.getOperand(*VLenPos))
- return false;
- return true;
- }
-
- // Specialize based on number of operands.
- // TODO emit VP intrinsics where MaskOp/VectorLenOp != null
- // SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT) { return
- // DAG.getNode(Opcode, DL, VT); }
- SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) {
- unsigned VPOpcode = *ISD::getVPForBaseOpcode(Opcode);
- assert(ISD::getVPMaskIdx(VPOpcode) == 1 &&
- ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 2);
- return DAG.getNode(VPOpcode, DL, VT,
- {Operand, RootMaskOp, RootVectorLenOp});
- }
-
- SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
- SDValue N2) {
- unsigned VPOpcode = *ISD::getVPForBaseOpcode(Opcode);
- assert(ISD::getVPMaskIdx(VPOpcode) == 2 &&
- ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 3);
- return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp});
- }
-
- SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
- SDValue N2, SDValue N3) {
- unsigned VPOpcode = *ISD::getVPForBaseOpcode(Opcode);
- assert(ISD::getVPMaskIdx(VPOpcode) == 3 &&
- ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 4);
- return DAG.getNode(VPOpcode, DL, VT,
- {N1, N2, N3, RootMaskOp, RootVectorLenOp});
- }
-
- SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand,
- SDNodeFlags Flags) {
- unsigned VPOpcode = *ISD::getVPForBaseOpcode(Opcode);
- assert(ISD::getVPMaskIdx(VPOpcode) == 1 &&
- ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 2);
- return DAG.getNode(VPOpcode, DL, VT, {Operand, RootMaskOp, RootVectorLenOp},
- Flags);
- }
-
- SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
- SDValue N2, SDNodeFlags Flags) {
- unsigned VPOpcode = *ISD::getVPForBaseOpcode(Opcode);
- assert(ISD::getVPMaskIdx(VPOpcode) == 2 &&
- ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 3);
- return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp},
- Flags);
- }
-
- SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
- SDValue N2, SDValue N3, SDNodeFlags Flags) {
- unsigned VPOpcode = *ISD::getVPForBaseOpcode(Opcode);
- assert(ISD::getVPMaskIdx(VPOpcode) == 3 &&
- ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 4);
- return DAG.getNode(VPOpcode, DL, VT,
- {N1, N2, N3, RootMaskOp, RootVectorLenOp}, Flags);
- }
-
- bool isOperationLegal(unsigned Op, EVT VT) const {
- unsigned VPOp = *ISD::getVPForBaseOpcode(Op);
- return TLI.isOperationLegal(VPOp, VT);
- }
-
- bool isOperationLegalOrCustom(unsigned Op, EVT VT,
- bool LegalOnly = false) const {
- unsigned VPOp = *ISD::getVPForBaseOpcode(Op);
- return TLI.isOperationLegalOrCustom(VPOp, VT, LegalOnly);
- }
-
- unsigned getNumOperands(SDValue N) const {
- return N->isVPOpcode() ? N->getNumOperands() - 2 : N->getNumOperands();
- }
-};
-
-} // namespace llvm
-
-#endif // LLVM_LIB_CODEGEN_SELECTIONDAG_MATCHCONTEXT_H
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 00cef99069347..87458fe010e77 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1661,25 +1661,6 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT));
}
-SDValue SelectionDAG::getVPZeroExtendInReg(SDValue Op, SDValue Mask,
- SDValue EVL, const SDLoc &DL,
- EVT VT) {
- EVT OpVT = Op.getValueType();
- assert(VT.isInteger() && OpVT.isInteger() &&
- "Cannot getVPZeroExtendInReg FP types");
- assert(VT.isVector() && OpVT.isVector() &&
- "getVPZeroExtendInReg type and operand type should be vector!");
- assert(VT.getVectorElementCount() == OpVT.getVectorElementCount() &&
- "Vector element counts must match in getZeroExtendInReg");
- assert(VT.getScalarType().bitsLE(OpVT.getScalarType()) && "Not extending!");
- if (OpVT == VT)
- return Op;
- APInt Imm = APInt::getLowBitsSet(OpVT.getScalarSizeInBits(),
- VT.getScalarSizeInBits());
- return getNode(ISD::VP_AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT), Mask,
- EVL);
-}
-
SDValue SelectionDAG::getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
// Only unsigned pointer semantics are supported right now. In the future this
// might delegate to TLI to check pointer signedness.
@@ -1706,26 +1687,6 @@ SDValue SelectionDAG::getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT) {
return getNode(ISD::XOR, DL, VT, Val, TrueValue);
}
-SDValue SelectionDAG::getVPLogicalNOT(const SDLoc &DL, SDValue Val,
- SDValue Mask, SDValue EVL, EVT VT) {
- SDValue TrueValue = getBoolConstant(true, DL, VT, VT);
- return getNode(ISD::VP_XOR, DL, VT, Val, TrueValue, Mask, EVL);
-}
-
-SDValue SelectionDAG::getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op,
- SDValue Mask, SDValue EVL) {
- return getVPZExtOrTrunc(DL, VT, Op, Mask, EVL);
-}
-
-SDValue SelectionDAG::getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op,
- SDValue Mask, SDValue EVL) {
- if (VT.bitsGT(Op.getValueType()))
- return getNode(ISD::VP_ZERO_EXTEND, DL, VT, Op, Mask, EVL);
- if (VT.bitsLT(Op.getValueType()))
- return getNode(ISD::VP_TRUNCATE, DL, VT, Op, Mask, EVL);
- return Op;
-}
-
SDValue SelectionDAG::getBoolConstant(bool V, const SDLoc &DL, EVT VT,
EVT OpVT) {
if (!V)
@@ -9194,13 +9155,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
if (N1.getValueType() == VT)
return N1;
break;
- case ISD::VP_TRUNCATE:
- case ISD::VP_SIGN_EXTEND:
- case ISD::VP_ZERO_EXTEND:
- // Don't create noop casts.
- if (N1.getValueType() == VT)
- return N1;
- break;
case ISD::VECTOR_COMPRESS: {
[[maybe_unused]] EVT VecVT = N1.getValueType();
[[maybe_unused]] EVT MaskVT = N2.getValueType();
@@ -12013,17 +11967,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
assert(Ops[2].getValueType() == Ops[3].getValueType() &&
"LHS/RHS of comparison should match types!");
break;
- case ISD::VP_ADD:
- case ISD::VP_SUB:
- // If it is VP_ADD/VP_SUB mask operation then turn it to VP_XOR
- if (VT.getScalarType() == MVT::i1)
- Opcode = ISD::VP_XOR;
- break;
- case ISD::VP_MUL:
- // If it is VP_MUL mask operation then turn it to VP_AND
- if (VT.getScalarType() == MVT::i1)
- Opcode = ISD::VP_AND;
- break;
case ISD::VP_REDUCE_MUL:
// If it is VP_REDUCE_MUL mask operation then turn it to VP_REDUCE_AND
if (VT == MVT::i1)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 81062dd6d3a11..4f990e1ff5b9e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9064,64 +9064,6 @@ void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
visitVPStridedStore(VPIntrin, OpValues);
break;
- case ISD::VP_FMULADD: {
- assert(OpValues.size() == 5 && "Unexpected number of operands");
- SDNodeFlags SDFlags;
- if (auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
- SDFlags.copyFMF(*FPMO);
- if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
- TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), ValueVTs[0])) {
- setValue(&VPIntrin, DAG.getNode(ISD::VP_FMA, DL, VTs, OpValues, SDFlags));
- } else {
- SDValue Mul = DAG.getNode(
- ISD::VP_FMUL, DL, VTs,
- {OpValues[0], OpValues[1], OpValues[3], OpValues[4]}, SDFlags);
- SDValue Add =
- DAG.getNode(ISD::VP_FADD, DL, VTs,
- {Mul, OpValues[2], OpValues[3], OpValues[4]}, SDFlags);
- setValue(&VPIntrin, Add);
- }
- break;
- }
- case ISD::VP_IS_FPCLASS: {
- const DataLayout DLayout = DAG.getDataLayout();
- EVT DestVT = TLI.getValueType(DLayout, VPIntrin.getType());
- auto Constant = OpValues[1]->getAsZExtVal();
- SDValue Check = DAG.getTargetConstant(Constant, DL, MVT::i32);
- SDValue V = DAG.getNode(ISD::VP_IS_FPCLASS, DL, DestVT,
- {OpValues[0], Check, OpValues[2], OpValues[3]});
- setValue(&VPIntrin, V);
- return;
- }
- case ISD::VP_INTTOPTR: {
- SDValue N = OpValues[0];
- EVT DestVT = TLI.getValueType(DAG.getDataLayout(), VPIntrin.getType());
- EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), VPIntrin.getType());
- N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1],
- OpValues[2]);
- N = DAG.getVPZExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1],
- OpValues[2]);
- setValue(&VPIntrin, N);
- break;
- }
- case ISD::VP_PTRTOINT: {
- SDValue N = OpValues[0];
- EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
- VPIntrin.getType());
- EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(),
- VPIntrin.getOperand(0)->getType());
- N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1],
- OpValues[2]);
- N = DAG.getVPZExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1],
- OpValues[2]);
- setValue(&VPIntrin, N);
- break;
- }
- case ISD::VP_ABS:
- case ISD::VP_CTLZ:
- case ISD::VP_CTLZ_ZERO_POISON:
- case ISD::VP_CTTZ:
- case ISD::VP_CTTZ_ZERO_POISON:
case ISD::VP_CTTZ_ELTS_ZERO_POISON:
case ISD::VP_CTTZ_ELTS: {
SDValue Result =
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 54faa7f252602..d4ddee142d4eb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8685,68 +8685,8 @@ static bool isNonZeroModBitWidthOrUndef(SDValue Z, unsigned BW) {
/*AllowUndefs=*/true, /*AllowTruncation=*/true);
}
-static SDValue expandVPFunnelShift(SDNode *Node, SelectionDAG &DAG) {
- EVT VT = Node->getValueType(0);
- SDValue ShX, ShY;
- SDValue ShAmt, InvShAmt;
- SDValue X = Node->getOperand(0);
- SDValue Y = Node->getOperand(1);
- SDValue Z = Node->getOperand(2);
- SDValue Mask = Node->getOperand(3);
- SDValue VL = Node->getOperand(4);
-
- unsigned BW = VT.getScalarSizeInBits();
- bool IsFSHL = Node->getOpcode() == ISD::VP_FSHL;
- SDLoc DL(SDValue(Node, 0));
-
- EVT ShVT = Z.getValueType();
- if (isNonZeroModBitWidthOrUndef(Z, BW)) {
- // fshl: X << C | Y >> (BW - C)
- // fshr: X << (BW - C) | Y >> C
- // where C = Z % BW is not zero
- SDValue BitWidthC = DAG.getConstant(BW, DL, ShVT);
- ShAmt = DAG.getNode(ISD::VP_UREM, DL, ShVT, Z, BitWidthC, Mask, VL);
- InvShAmt = DAG.getNode(ISD::VP_SUB, DL, ShVT, BitWidthC, ShAmt, Mask, VL);
- ShX = DAG.getNode(ISD::VP_SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt, Mask,
- VL);
- ShY = DAG.getNode(ISD::VP_SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt, Mask,
- VL);
- } else {
- // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW))
- // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW)
- SDValue BitMask = DAG.getConstant(BW - 1, DL, ShVT);
- if (isPowerOf2_32(BW)) {
- // Z % BW -> Z & (BW - 1)
- ShAmt = DAG.getNode(ISD::VP_AND, DL, ShVT, Z, BitMask, Mask, VL);
- // (BW - 1) - (Z % BW) -> ~Z & (BW - 1)
- SDValue NotZ = DAG.getNode(ISD::VP_XOR, DL, ShVT, Z,
- DAG.getAllOnesConstant(DL, ShVT), Mask, VL);
- InvShAmt = DAG.getNode(ISD::VP_AND, DL, ShVT, NotZ, BitMask, Mask, VL);
- } else {
- SDValue BitWidthC = DAG.getConstant(BW, DL, ShVT);
- ShAmt = DAG.getNode(ISD::VP_UREM, DL, ShVT, Z, BitWidthC, Mask, VL);
- InvShAmt = DAG.getNode(ISD::VP_SUB, DL, ShVT, BitMask, ShAmt, Mask, VL);
- }
-
- SDValue One = DAG.getConstant(1, DL, ShVT);
- if (IsFSHL) {
- ShX = DAG.getNode(ISD::VP_SHL, DL, VT, X, ShAmt, Mask, VL);
- SDValue ShY1 = DAG.getNode(ISD::VP_SRL, DL, VT, Y, One, Mask, VL);
- ShY = DAG.getNode(ISD::VP_SRL, DL, VT, ShY1, InvShAmt, Mask, VL);
- } else {
- SDValue ShX1 = DAG.getNode(ISD::VP_SHL, DL, VT, X, One, Mask, VL);
- ShX = DAG.getNode(ISD::VP_SHL, DL, VT, ShX1, InvShAmt, Mask, VL);
- ShY = DAG.getNode(ISD::VP_SRL, DL, VT, Y, ShAmt, Mask, VL);
- }
- }
- return DAG.getNode(ISD::VP_OR, DL, VT, ShX, ShY, Mask, VL);
-}
-
SDValue TargetLowering::expandFunnelShift(SDNode *Node,
SelectionDAG &DAG) const {
- if (Node->isVPOpcode())
- return expandVPFunnelShift(Node, DAG);
-
EVT VT = Node->getValueType(0);
if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
@@ -10896,75 +10836,6 @@ SDValue TargetLowering::expandCTPOP(SDNode *Node, SelectionDAG &DAG) const {
return DAG.getNode(ISD::SRL, dl, VT, V, DAG.getConstant(Len - 8, dl, ShVT));
}
-SDValue TargetLowering::expandVPCTPOP(SDNode *Node, SelectionDAG &DAG) const {
- SDLoc dl(Node);
- EVT VT = Node->getValueType(0);
- EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
- SDValue Op = Node->getOperand(0);
- SDValue Mask = Node->getOperand(1);
- SDValue VL = Node->getOperand(2);
- unsigned Len = VT.getScalarSizeInBits();
- assert(VT.isInteger() && "VP_CTPOP not implemented for this type.");
-
- // TODO: Add support for irregular type lengths.
- if (!(Len <= 128 && Len % 8 == 0))
- return SDValue();
-
- // This is same algorithm of expandCTPOP from
- // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
- SDValue Mask55 =
- DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl, VT);
- SDValue Mask33 =
- DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl, VT);
- SDValue Mask0F =
- DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl, VT);
-
- SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5;
-
- // v = v - ((v >> 1) & 0x55555555...)
- Tmp1 = DAG.getNode(ISD::VP_AND, dl, VT,
- DAG.getNode(ISD::VP_SRL, dl, VT, Op,
- DAG.getConstant(1, dl, ShVT), Mask, VL),
- Mask55, Mask, VL);
- Op = DAG.getNode(ISD::VP_SUB, dl, VT, Op, Tmp1, Mask, VL);
-
- // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
- Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Op, Mask33, Mask, VL);
- Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT,
- DAG.getNode(ISD::VP_SRL, dl, VT, Op,
- DAG.getConstant(2, dl, ShVT), Mask, VL),
- Mask33, Mask, VL);
- Op = DAG.getNode(ISD::VP_ADD, dl, VT, Tmp2, Tmp3, Mask, VL);
-
- // v = (v + (v >> 4)) & 0x0F0F0F0F...
- Tmp4 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(4, dl, ShVT),
- Mask, VL),
- Tmp5 = DAG.getNode(ISD::VP_ADD, dl, VT, Op, Tmp4, Mask, VL);
- Op = DAG.getNode(ISD::VP_AND, dl, VT, Tmp5, Mask0F, Mask, VL);
-
- if (Len <= 8)
- return Op;
-
- // v = (v * 0x01010101...) >> (Len - 8)
- SDValue V;
- if (isOperationLegalOrCustomOrPromote(
- ISD::VP_MUL, getTypeToTransformTo(*DAG.getContext(), VT))) {
- SDValue Mask01 =
- DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), dl, VT);
- V = DAG.getNode(ISD::VP_MUL, dl, VT, Op, Mask01, Mask, VL);
- } else {
- V = Op;
- for (unsigned Shift = 8; Shift < Len; Shift *= 2) {
- SDValue ShiftC = DAG.getShiftAmountConstant(Shift, VT, dl);
- V = DAG.getNode(ISD::VP_ADD, dl, VT, V,
- DAG.getNode(ISD::VP_SHL, dl, VT, V, ShiftC, Mask, VL),
- Mask, VL);
- }
- }
- return DAG.getNode(ISD::VP_SRL, dl, VT, V, DAG.getConstant(Len - 8, dl, ShVT),
- Mask, VL);
-}
-
SDValue TargetLowering::expandCTLZ(SDNode *Node, SelectionDAG &DAG) const {
SDLoc dl(Node);
EVT VT = Node->getValueType(0);
@@ -11015,33 +10886,6 @@ SDValue TargetLowering::expandCTLZ(SDNode *Node, SelectionDAG &DAG) const {
return DAG.getNode(ISD::CTPOP, dl, VT, Op);
}
-SDValue TargetLowering::expandVPCTLZ(SDNode *Node, SelectionDAG &DAG) const {
- SDLoc dl(Node);
- EVT VT = Node->getValueType(0);
- EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
- SDValue Op = Node->getOperand(0);
- SDValue Mask = Node->getOperand(1);
- SDValue VL = Node->getOperand(2);
- unsigned NumBitsPerElt = VT.getScalarSizeInBits();
-
- // do this:
- // x = x | (x >> 1);
- // x = x | (x >> 2);
- // ...
- // x = x | (x >>16);
- // x = x | (x >>32); // for 64-bit input
- // return popcount(~x);
- for (unsigned i = 0; (1U << i) < NumBitsPerElt; ++i) {
- SDValue Tmp = DAG.getConstant(1ULL << i, dl, ShVT);
- Op = DAG.getNode(ISD::VP_OR, dl, VT, Op,
- DAG.getNode(ISD::VP_SRL, dl, VT, Op, Tmp, Mask, VL), Mask,
- VL);
- }
- Op = DAG.getNode(ISD::VP_XOR, dl, VT, Op, DAG.getAllOnesConstant(dl, VT),
- Mask, VL);
- return DAG.getNode(ISD::VP_CTPOP, dl, VT, Op, Mask, VL);
-}
-
SDValue TargetLowering::expandCTLS(SDNode *Node, SelectionDAG &DAG) const {
SDLoc dl(Node);
EVT VT = Node->getValueType(0);
@@ -11164,22 +11008,6 @@ SDValue TargetLowering::expandCTTZ(SDNode *Node, SelectionDAG &DAG) const {
return DAG.getNode(ISD::CTPOP, dl, VT, Tmp);
}
-SDValue TargetLowering::expandVPCTTZ(SDNode *Node, SelectionDAG &DAG) const {
- SDValue Op = Node->getOperand(0);
- SDValue Mask = Node->getOperand(1);
- SDValue VL = Node->getOperand(2);
- SDLoc dl(Node);
- EVT VT = Node->getValueType(0);
-
- // Same as the vector part of expandCTTZ, use: popcount(~x & (x - 1))
- SDValue Not = DAG.getNode(ISD::VP_XOR, dl, VT, Op,
- DAG.getAllOnesConstant(dl, VT), Mask, VL);
- SDValue MinusOne = DAG.getNode(ISD::VP_SUB, dl, VT, Op,
- DAG.getConstant(1, dl, VT), Mask, VL);
- SDValue Tmp = DAG.getNode(ISD::VP_AND, dl, VT, Not, MinusOne, Mask, VL);
- return DAG.getNode(ISD::VP_CTPOP, dl, VT, Tmp, Mask, VL);
-}
-
SDValue TargetLowering::expandVPCTTZElements(SDNode *N,
SelectionDAG &DAG) const {
// %cond = to_bool_vec %source
@@ -11675,82 +11503,6 @@ SDValue TargetLowering::expandBSWAP(SDNode *N, SelectionDAG &DAG) const {
}
}
-SDValue TargetLowering::expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const {
- SDLoc dl(N);
- EVT VT = N->getValueType(0);
- SDValue Op = N->getOperand(0);
- SDValue Mask = N->getOperand(1);
- SDValue EVL = N->getOperand(2);
-
- if (!VT.isSimple())
- return SDValue();
-
- EVT SHVT = getShiftAmountTy(VT, DAG.getDataLayout());
- SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
- switch (VT.getSimpleVT().getScalarType().SimpleTy) {
- default:
- return SDValue();
- case MVT::i16:
- Tmp1 = DAG.getNode(ISD::VP_SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
- Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
- Mask, EVL);
- return DAG.getNode(ISD::VP_OR, dl, VT, Tmp1, Tmp2, Mask, EVL);
- case MVT::i32:
- Tmp4 = DAG.getNode(ISD::VP_SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT),
- Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Op, DAG.getConstant(0xFF00, dl, VT),
- Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp3, DAG.getConstant(8, dl, SHVT),
- Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
- Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
- DAG.getConstant(0xFF00, dl, VT), Mask, EVL);
- Tmp1 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT),
- Mask, EVL);
- Tmp4 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp4, Tmp3, Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp2, Tmp1, Mask, EVL);
- return DAG.getNode(ISD::VP_OR, dl, VT, Tmp4, Tmp2, Mask, EVL);
- case MVT::i64:
- Tmp8 = DAG.getNode(ISD::VP_SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT),
- Mask, EVL);
- Tmp7 = DAG.getNode(ISD::VP_AND, dl, VT, Op,
- DAG.getConstant(255ULL << 8, dl, VT), Mask, EVL);
- Tmp7 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp7, DAG.getConstant(40, dl, SHVT),
- Mask, EVL);
- Tmp6 = DAG.getNode(ISD::VP_AND, dl, VT, Op,
- DAG.getConstant(255ULL << 16, dl, VT), Mask, EVL);
- Tmp6 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp6, DAG.getConstant(24, dl, SHVT),
- Mask, EVL);
- Tmp5 = DAG.getNode(ISD::VP_AND, dl, VT, Op,
- DAG.getConstant(255ULL << 24, dl, VT), Mask, EVL);
- Tmp5 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp5, DAG.getConstant(8, dl, SHVT),
- Mask, EVL);
- Tmp4 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
- Mask, EVL);
- Tmp4 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp4,
- DAG.getConstant(255ULL << 24, dl, VT), Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT),
- Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp3,
- DAG.getConstant(255ULL << 16, dl, VT), Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT),
- Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
- DAG.getConstant(255ULL << 8, dl, VT), Mask, EVL);
- Tmp1 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT),
- Mask, EVL);
- Tmp8 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp8, Tmp7, Mask, EVL);
- Tmp6 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp6, Tmp5, Mask, EVL);
- Tmp4 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp4, Tmp3, Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp2, Tmp1, Mask, EVL);
- Tmp8 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp8, Tmp6, Mask, EVL);
- Tmp4 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp4, Tmp2, Mask, EVL);
- return DAG.getNode(ISD::VP_OR, dl, VT, Tmp8, Tmp4, Mask, EVL);
- }
-}
-
SDValue TargetLowering::expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const {
SDLoc dl(N);
EVT VT = N->getValueType(0);
@@ -11812,68 +11564,6 @@ SDValue TargetLowering::expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const {
return Tmp;
}
-SDValue TargetLowering::expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const {
- assert(N->getOpcode() == ISD::VP_BITREVERSE);
-
- SDLoc dl(N);
- EVT VT = N->getValueType(0);
- SDValue Op = N->getOperand(0);
- SDValue Mask = N->getOperand(1);
- SDValue EVL = N->getOperand(2);
- EVT SHVT = getShiftAmountTy(VT, DAG.getDataLayout());
- unsigned Sz = VT.getScalarSizeInBits();
-
- SDValue Tmp, Tmp2, Tmp3;
-
- // If we can, perform BSWAP first and then the mask+swap the i4, then i2
- // and finally the i1 pairs.
- // TODO: We can easily support i4/i2 legal types if any target ever does.
- if (Sz >= 8 && isPowerOf2_32(Sz)) {
- // Create the masks - repeating the pattern every byte.
- APInt Mask4 = APInt::getSplat(Sz, APInt(8, 0x0F));
- APInt Mask2 = APInt::getSplat(Sz, APInt(8, 0x33));
- APInt Mask1 = APInt::getSplat(Sz, APInt(8, 0x55));
-
- // BSWAP if the type is wider than a single byte.
- Tmp = (Sz > 8 ? DAG.getNode(ISD::VP_BSWAP, dl, VT, Op, Mask, EVL) : Op);
-
- // swap i4: ((V >> 4) & 0x0F) | ((V & 0x0F) << 4)
- Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Tmp, DAG.getConstant(4, dl, SHVT),
- Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
- DAG.getConstant(Mask4, dl, VT), Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp, DAG.getConstant(Mask4, dl, VT),
- Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT),
- Mask, EVL);
- Tmp = DAG.getNode(ISD::VP_OR, dl, VT, Tmp2, Tmp3, Mask, EVL);
-
- // swap i2: ((V >> 2) & 0x33) | ((V & 0x33) << 2)
- Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Tmp, DAG.getConstant(2, dl, SHVT),
- Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
- DAG.getConstant(Mask2, dl, VT), Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp, DAG.getConstant(Mask2, dl, VT),
- Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT),
- Mask, EVL);
- Tmp = DAG.getNode(ISD::VP_OR, dl, VT, Tmp2, Tmp3, Mask, EVL);
-
- // swap i1: ((V >> 1) & 0x55) | ((V & 0x55) << 1)
- Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Tmp, DAG.getConstant(1, dl, SHVT),
- Mask, EVL);
- Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
- DAG.getConstant(Mask1, dl, VT), Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp, DAG.getConstant(Mask1, dl, VT),
- Mask, EVL);
- Tmp3 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT),
- Mask, EVL);
- Tmp = DAG.getNode(ISD::VP_OR, dl, VT, Tmp2, Tmp3, Mask, EVL);
- return Tmp;
- }
- return SDValue();
-}
-
std::pair<SDValue, SDValue>
TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
SelectionDAG &DAG) const {
@@ -14182,15 +13872,12 @@ bool TargetLowering::expandMultipleResultFPLibCall(
bool TargetLowering::LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT,
SDValue &LHS, SDValue &RHS,
- SDValue &CC, SDValue Mask,
- SDValue EVL, bool &NeedInvert,
+ SDValue &CC, bool &NeedInvert,
const SDLoc &dl, SDValue &Chain,
bool IsSignaling) const {
MVT OpVT = LHS.getSimpleValueType();
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
NeedInvert = false;
- assert(!EVL == !Mask && "VP Mask and EVL must either both be set or unset");
- bool IsNonVP = !EVL;
switch (getCondCodeAction(CCCode, OpVT)) {
default:
llvm_unreachable("Unknown condition code action!");
@@ -14337,34 +14024,17 @@ bool TargetLowering::LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT,
if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
// If we aren't the ordered or unorder operation,
// then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
- if (IsNonVP) {
- SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling);
- SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2, Chain, IsSignaling);
- } else {
- SetCC1 = DAG.getSetCCVP(dl, VT, LHS, RHS, CC1, Mask, EVL);
- SetCC2 = DAG.getSetCCVP(dl, VT, LHS, RHS, CC2, Mask, EVL);
- }
+ SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling);
+ SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2, Chain, IsSignaling);
} else {
// Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
- if (IsNonVP) {
- SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling);
- SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2, Chain, IsSignaling);
- } else {
- SetCC1 = DAG.getSetCCVP(dl, VT, LHS, LHS, CC1, Mask, EVL);
- SetCC2 = DAG.getSetCCVP(dl, VT, RHS, RHS, CC2, Mask, EVL);
- }
+ SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling);
+ SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2, Chain, IsSignaling);
}
if (Chain)
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, SetCC1.getValue(1),
SetCC2.getValue(1));
- if (IsNonVP)
- LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
- else {
- // Transform the binary opcode to the VP equivalent.
- assert((Opc == ISD::OR || Opc == ISD::AND) && "Unexpected opcode");
- Opc = Opc == ISD::OR ? ISD::VP_OR : ISD::VP_AND;
- LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2, Mask, EVL);
- }
+ LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
RHS = SDValue();
CC = SDValue();
return true;
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 3188b193c25b3..9df1419d7349d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -7887,10 +7887,6 @@ unsigned NVPTXTargetLowering::getPreferredFPToIntOpcode(unsigned Op, EVT FromVT,
if (isOperationLegal(ISD::STRICT_FP_TO_SINT, ToVT))
return ISD::STRICT_FP_TO_SINT;
break;
- case ISD::VP_FP_TO_UINT:
- if (isOperationLegal(ISD::VP_FP_TO_SINT, ToVT))
- return ISD::VP_FP_TO_SINT;
- break;
default:
break;
}
diff --git a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
index 543b769b1a666..5b7c1e9ebc24f 100644
--- a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
@@ -1151,95 +1151,6 @@ TEST_F(SelectionDAGPatternMatchTest, matchIntrinsicWOChain) {
Add, m_IntrinsicWOChain<Intrinsic::x86_aadd32>(m_Value(), m_Value())));
}
-namespace {
-struct VPMatchContext : public SDPatternMatch::BasicMatchContext {
- using SDPatternMatch::BasicMatchContext::BasicMatchContext;
-
- bool match(SDValue OpVal, unsigned Opc) const {
- if (!OpVal->isVPOpcode())
- return OpVal->getOpcode() == Opc;
-
- auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), false);
- return BaseOpc == Opc;
- }
-
- unsigned getNumOperands(SDValue N) const {
- return N->isVPOpcode() ? N->getNumOperands() - 2 : N->getNumOperands();
- }
-};
-} // anonymous namespace
-TEST_F(SelectionDAGPatternMatchTest, matchContext) {
- SDLoc DL;
- auto BoolVT = EVT::getIntegerVT(Context, 1);
- auto Int32VT = EVT::getIntegerVT(Context, 32);
- auto VInt32VT = EVT::getVectorVT(Context, Int32VT, 4);
- auto MaskVT = EVT::getVectorVT(Context, BoolVT, 4);
-
- SDValue Scalar0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
- Register::index2VirtReg(1), Int32VT);
- SDValue Vector0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
- Register::index2VirtReg(2), VInt32VT);
- SDValue Mask0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
- Register::index2VirtReg(3), MaskVT);
-
- SDValue VPAdd = DAG->getNode(ISD::VP_ADD, DL, VInt32VT,
- {Vector0, Vector0, Mask0, Scalar0});
- SDValue VPReduceAdd = DAG->getNode(ISD::VP_REDUCE_ADD, DL, Int32VT,
- {Scalar0, VPAdd, Mask0, Scalar0});
- SDValue Add = DAG->getNode(ISD::ADD, DL, VInt32VT, {Vector0, Vector0});
-
- using namespace SDPatternMatch;
- VPMatchContext VPCtx(DAG.get());
- EXPECT_TRUE(sd_context_match(VPAdd, VPCtx, m_SpecificOpc(ISD::ADD)));
- EXPECT_TRUE(
- sd_context_match(VPAdd, VPCtx, m_Node(ISD::ADD, m_Value(), m_Value())));
- // VPMatchContext can't match pattern using explicit VP Opcode
- EXPECT_FALSE(sd_context_match(VPAdd, VPCtx,
- m_Node(ISD::VP_ADD, m_Value(), m_Value())));
- EXPECT_FALSE(sd_context_match(
- VPAdd, VPCtx,
- m_Node(ISD::VP_ADD, m_Value(), m_Value(), m_Value(), m_Value())));
- // Check Binary Op Pattern
- EXPECT_TRUE(sd_context_match(VPAdd, VPCtx, m_Add(m_Value(), m_Value())));
- // VP_REDUCE_ADD doesn't have a based opcode, so we use a normal
- // sd_match before switching to VPMatchContext when checking VPAdd.
- EXPECT_TRUE(
- sd_match(VPReduceAdd, m_Node(ISD::VP_REDUCE_ADD, m_Value(),
- m_Context(VPCtx, m_SpecificOpc(ISD::ADD)),
- m_Value(), m_Value())));
- // non-vector predicated should match too
- EXPECT_TRUE(sd_context_match(Add, VPCtx, m_SpecificOpc(ISD::ADD)));
- EXPECT_TRUE(
- sd_context_match(Add, VPCtx, m_Node(ISD::ADD, m_Value(), m_Value())));
- EXPECT_FALSE(sd_context_match(
- Add, VPCtx,
- m_Node(ISD::ADD, m_Value(), m_Value(), m_Value(), m_Value())));
- EXPECT_TRUE(sd_context_match(Add, VPCtx, m_Add(m_Value(), m_Value())));
-}
-
-TEST_F(SelectionDAGPatternMatchTest, matchVPWithBasicContext) {
- SDLoc DL;
- auto BoolVT = EVT::getIntegerVT(Context, 1);
- auto Int32VT = EVT::getIntegerVT(Context, 32);
- auto VInt32VT = EVT::getVectorVT(Context, Int32VT, 4);
- auto MaskVT = EVT::getVectorVT(Context, BoolVT, 4);
-
- SDValue Vector0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
- Register::index2VirtReg(1), VInt32VT);
- SDValue Mask = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
- Register::index2VirtReg(2), MaskVT);
- SDValue EL = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
- Register::index2VirtReg(3), Int32VT);
-
- SDValue VPAdd =
- DAG->getNode(ISD::VP_ADD, DL, VInt32VT, Vector0, Vector0, Mask, EL);
-
- using namespace SDPatternMatch;
- EXPECT_FALSE(sd_match(VPAdd, m_Node(ISD::VP_ADD, m_Value(), m_Value())));
- EXPECT_TRUE(sd_match(
- VPAdd, m_Node(ISD::VP_ADD, m_Value(), m_Value(), m_Value(), m_Value())));
-}
-
TEST_F(SelectionDAGPatternMatchTest, matchAdvancedProperties) {
SDLoc DL;
auto Int16VT = EVT::getIntegerVT(Context, 16);
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