[llvm-branch-commits] [llvm] [CodeGen] Give NewPM SplitCriticalEdge default values (PR #217504)
Aiden Grossman via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Aug 20 06:14:16 PDT 2026
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/217504
>From 72988defb62e8c873d2513e63f4d5ccbb0c38a84 Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Thu, 20 Aug 2026 02:12:20 +0000
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change?=
=?UTF-8?q?s=20to=20main=20this=20commit=20is=20based=20on?=
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Created using spr 1.3.7
[skip ci]
---
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp | 2 +-
.../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 2 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 34 +++++++++----------
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 2 +-
.../lib/Target/AMDGPU/AMDGPURegBankSelect.cpp | 2 +-
.../GlobalISel/arm64-regbankselect.mir | 4 +--
.../GlobalISel/arm64-saddlp1d-uaddlp1d.mir | 2 +-
.../GlobalISel/implicit_def_rbs_crash.mir | 2 +-
.../rbs-matrixindex-regclass-crash.mir | 2 +-
.../AArch64/GlobalISel/reg-bank-128bit.mir | 2 +-
.../GlobalISel/regbank-assert-align.mir | 2 +-
.../GlobalISel/regbank-assert-sext.mir | 2 +-
.../GlobalISel/regbank-assert-zext.mir | 2 +-
.../AArch64/GlobalISel/regbank-ceil.mir | 2 +-
.../AArch64/GlobalISel/regbank-dup.mir | 2 +-
.../GlobalISel/regbank-extract-vector-elt.mir | 2 +-
.../AArch64/GlobalISel/regbank-extract.mir | 2 +-
.../AArch64/GlobalISel/regbank-fcmp.mir | 2 +-
.../AArch64/GlobalISel/regbank-fma.mir | 2 +-
.../AArch64/GlobalISel/regbank-fmaximum.mir | 2 +-
.../AArch64/GlobalISel/regbank-fminimum.mir | 2 +-
.../AArch64/GlobalISel/regbank-fp-use-def.mir | 2 +-
.../AArch64/GlobalISel/regbank-inlineasm.mir | 2 +-
.../GlobalISel/regbank-insert-vector-elt.mir | 2 +-
.../GlobalISel/regbank-intrinsic-round.mir | 2 +-
.../GlobalISel/regbank-intrinsic-trunc.mir | 2 +-
.../AArch64/GlobalISel/regbank-intrinsic.mir | 2 +-
.../AArch64/GlobalISel/regbank-llround.mir | 2 +-
.../AArch64/GlobalISel/regbank-lround.mir | 2 +-
.../AArch64/GlobalISel/regbank-maxnum.mir | 2 +-
.../AArch64/GlobalISel/regbank-minnum.mir | 2 +-
.../AArch64/GlobalISel/regbank-nearbyint.mir | 2 +-
.../AArch64/GlobalISel/regbank-select.mir | 2 +-
.../GlobalISel/regbank-shift-imm-64.mir | 2 +-
.../AArch64/GlobalISel/regbank-trunc-s128.mir | 2 +-
.../GlobalISel/regbankselect-build-vector.mir | 2 +-
.../GlobalISel/regbankselect-dbg-value.mir | 2 +-
.../GlobalISel/regbankselect-default.mir | 2 +-
.../GlobalISel/regbankselect-fp-loads.mir | 2 +-
.../GlobalISel/regbankselect-reductions.mir | 2 +-
.../GlobalISel/regbankselect-reg_sequence.mir | 2 +-
.../GlobalISel/regbankselect-unmerge-vec.mir | 2 +-
.../AArch64/GlobalISel/select-constant.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/select-dup.mir | 2 +-
.../GlobalISel/readanylane-combines.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-abs.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-add.mir | 2 +-
.../GlobalISel/regbankselect-add.s16.mir | 2 +-
.../GlobalISel/regbankselect-add.s32.mir | 2 +-
.../GlobalISel/regbankselect-add.v2s16.mir | 2 +-
.../regbankselect-amdgcn-exp-compr.mir | 2 +-
.../GlobalISel/regbankselect-amdgcn-exp.mir | 2 +-
.../regbankselect-amdgcn-s-buffer-load.mir | 2 +-
.../regbankselect-amdgcn.ballot.i64.mir | 2 +-
.../GlobalISel/regbankselect-amdgcn.class.mir | 2 +-
.../regbankselect-amdgcn.cvt.pkrtz.mir | 2 +-
.../regbankselect-amdgcn.div.fmas.mir | 2 +-
.../regbankselect-amdgcn.div.scale.mir | 2 +-
.../regbankselect-amdgcn.ds.append.mir | 2 +-
.../regbankselect-amdgcn.ds.bpermute.mir | 2 +-
.../regbankselect-amdgcn.ds.consume.mir | 2 +-
.../regbankselect-amdgcn.ds.gws.init.mir | 2 +-
.../regbankselect-amdgcn.ds.gws.sema.v.mir | 2 +-
.../regbankselect-amdgcn.ds.ordered.add.mir | 2 +-
.../regbankselect-amdgcn.ds.ordered.swap.mir | 2 +-
.../regbankselect-amdgcn.ds.permute.mir | 2 +-
.../regbankselect-amdgcn.ds.swizzle.mir | 2 +-
.../regbankselect-amdgcn.else.32.mir | 8 ++---
.../regbankselect-amdgcn.else.64.mir | 4 +--
.../GlobalISel/regbankselect-amdgcn.fcmp.mir | 2 +-
.../regbankselect-amdgcn.fmul.legacy.mir | 2 +-
.../regbankselect-amdgcn.groupstaticsize.mir | 2 +-
.../GlobalISel/regbankselect-amdgcn.icmp.mir | 2 +-
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.../regbankselect-amdgcn.image.sample.1d.ll | 4 +--
.../regbankselect-amdgcn.interp.mov.mir | 2 +-
.../regbankselect-amdgcn.interp.p1.f16.mir | 2 +-
.../regbankselect-amdgcn.interp.p1.mir | 2 +-
.../regbankselect-amdgcn.interp.p2.f16.mir | 2 +-
.../regbankselect-amdgcn.interp.p2.mir | 2 +-
.../GlobalISel/regbankselect-amdgcn.kill.mir | 2 +-
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.../regbankselect-amdgcn.lds.param.load.mir | 2 +-
.../regbankselect-amdgcn.live.mask.mir | 2 +-
.../regbankselect-amdgcn.mfma.gfx90a.mir | 2 +-
.../regbankselect-amdgcn.mfma.gfx942.mir | 2 +-
.../GlobalISel/regbankselect-amdgcn.mfma.mir | 2 +-
.../regbankselect-amdgcn.ps.live.mir | 2 +-
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.../regbankselect-amdgcn.raw.buffer.load.ll | 4 +--
...egbankselect-amdgcn.raw.ptr.buffer.load.ll | 2 +-
.../regbankselect-amdgcn.readfirstlane.mir | 2 +-
.../regbankselect-amdgcn.readlane.mir | 2 +-
.../regbankselect-amdgcn.s.buffer.load.ll | 6 ++--
.../regbankselect-amdgcn.s.buffer.load.mir | 4 +--
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.../regbankselect-amdgcn.s.getpc.mir | 2 +-
.../regbankselect-amdgcn.s.getreg.mir | 2 +-
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.../regbankselect-amdgcn.s.memtime.mir | 2 +-
.../regbankselect-amdgcn.s.sendmsg.mir | 2 +-
.../regbankselect-amdgcn.s.sendmsghalt.mir | 2 +-
...regbankselect-amdgcn.struct.buffer.load.ll | 4 +--
...egbankselect-amdgcn.struct.buffer.store.ll | 2 +-
...ankselect-amdgcn.struct.ptr.buffer.load.ll | 4 +--
...nkselect-amdgcn.struct.ptr.buffer.store.ll | 2 +-
.../regbankselect-amdgcn.update.dpp.mir | 2 +-
.../regbankselect-amdgcn.wqm.demote.mir | 2 +-
.../GlobalISel/regbankselect-amdgcn.wqm.mir | 2 +-
.../regbankselect-amdgcn.wqm.vote.mir | 4 +--
.../regbankselect-amdgcn.writelane.mir | 2 +-
.../GlobalISel/regbankselect-amdgcn.wwm.mir | 2 +-
.../regbankselect-amdgpu-ffbh-u32.mir | 2 +-
.../regbankselect-amdgpu-ffbl-b32.mir | 2 +-
.../regbankselect-amdgpu-wave-address.mir | 2 +-
.../GlobalISel/regbankselect-and-s1.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-and.mir | 2 +-
.../GlobalISel/regbankselect-anyext.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-ashr.mir | 2 +-
.../GlobalISel/regbankselect-assert-align.mir | 2 +-
.../GlobalISel/regbankselect-assert-sext.mir | 2 +-
.../GlobalISel/regbankselect-assert-zext.mir | 2 +-
.../regbankselect-atomic-cmpxchg.mir | 2 +-
.../regbankselect-atomicrmw-add-sub.mir | 2 +-
.../regbankselect-atomicrmw-add.mir | 2 +-
.../regbankselect-atomicrmw-and.mir | 2 +-
.../regbankselect-atomicrmw-fadd.mir | 2 +-
.../regbankselect-atomicrmw-fadd.v2f16.mir | 2 +-
.../regbankselect-atomicrmw-max.mir | 2 +-
.../regbankselect-atomicrmw-min.mir | 2 +-
...regbankselect-atomicrmw-minmax-uminmax.mir | 2 +-
.../GlobalISel/regbankselect-atomicrmw-or.mir | 2 +-
.../regbankselect-atomicrmw-sub.mir | 2 +-
...regbankselect-atomicrmw-uinc-udec-wrap.mir | 2 +-
.../regbankselect-atomicrmw-umax.mir | 2 +-
.../regbankselect-atomicrmw-umin.mir | 2 +-
.../regbankselect-atomicrmw-xchg.mir | 2 +-
.../regbankselect-atomicrmw-xor.mir | 2 +-
.../GlobalISel/regbankselect-bitcast.mir | 2 +-
.../GlobalISel/regbankselect-bitreverse.mir | 2 +-
.../GlobalISel/regbankselect-block-addr.mir | 2 +-
.../GlobalISel/regbankselect-brcond.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-bswap.mir | 2 +-
.../GlobalISel/regbankselect-build-vector.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-call.ll | 4 +--
.../regbankselect-concat-vector.mir | 2 +-
.../GlobalISel/regbankselect-constant.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-copy.mir | 8 ++---
.../regbankselect-ctlz-zero-poison.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-ctpop.mir | 2 +-
.../regbankselect-cttz-zero-poison.mir | 2 +-
.../GlobalISel/regbankselect-default.mir | 2 +-
.../regbankselect-dyn-stackalloc.mir | 4 +--
.../regbankselect-extract-vector-elt.mir | 4 +--
.../AMDGPU/GlobalISel/regbankselect-fabs.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-fadd.mir | 2 +-
.../regbankselect-fcanonicalize.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-fceil.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-fcmp.mir | 4 +--
.../AMDGPU/GlobalISel/regbankselect-fexp2.mir | 6 ++--
.../GlobalISel/regbankselect-ffloor.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-flog2.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-fma.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-fmul.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-fneg.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-fpext.mir | 4 +--
.../GlobalISel/regbankselect-fptosi-sat.mir | 2 +-
.../GlobalISel/regbankselect-fptosi.mir | 2 +-
.../GlobalISel/regbankselect-fptoui-sat.mir | 2 +-
.../GlobalISel/regbankselect-fptoui.mir | 2 +-
.../GlobalISel/regbankselect-fptrunc.mir | 4 +--
.../GlobalISel/regbankselect-frame-index.mir | 2 +-
.../GlobalISel/regbankselect-freeze.mir | 6 ++--
.../AMDGPU/GlobalISel/regbankselect-fshr.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-fsqrt.mir | 4 +--
.../AMDGPU/GlobalISel/regbankselect-fsub.mir | 4 +--
.../AMDGPU/GlobalISel/regbankselect-icmp.mir | 8 ++---
.../GlobalISel/regbankselect-icmp.s16.mir | 2 +-
.../GlobalISel/regbankselect-illegal-copy.mir | 4 +--
.../GlobalISel/regbankselect-implicit-def.mir | 4 +--
.../regbankselect-insert-vector-elt.mir | 4 +--
.../regbankselect-intrinsic-roundeven.mir | 2 +-
.../regbankselect-intrinsic-trunc.mir | 2 +-
.../GlobalISel/regbankselect-inttoptr.mir | 6 ++--
.../AMDGPU/GlobalISel/regbankselect-load.mir | 6 ++--
.../AMDGPU/GlobalISel/regbankselect-lshr.mir | 2 +-
.../GlobalISel/regbankselect-mad_64_32.mir | 6 ++--
.../GlobalISel/regbankselect-merge-values.mir | 2 +-
.../regbankselect-mui-regbanklegalize.mir | 2 +-
.../regbankselect-mui-regbankselect.mir | 2 +-
.../regbankselect-mui-salu-float.mir | 8 ++---
.../AMDGPU/GlobalISel/regbankselect-mui.mir | 4 +--
.../AMDGPU/GlobalISel/regbankselect-mul.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-or.mir | 2 +-
.../GlobalISel/regbankselect-phi-s1.mir | 4 +--
.../AMDGPU/GlobalISel/regbankselect-phi.mir | 4 +--
...ankselect-pseudo-scalar-transcendental.mir | 4 +--
.../GlobalISel/regbankselect-ptr-add.mir | 2 +-
.../GlobalISel/regbankselect-ptrmask.mir | 2 +-
.../GlobalISel/regbankselect-ptrtoint.mir | 6 ++--
.../GlobalISel/regbankselect-reg-sequence.mir | 4 +--
.../AMDGPU/GlobalISel/regbankselect-sadde.mir | 2 +-
.../GlobalISel/regbankselect-salu-float.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-sbfx.mir | 2 +-
.../GlobalISel/regbankselect-select.mir | 2 +-
.../GlobalISel/regbankselect-sext-inreg.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-sext.mir | 2 +-
.../GlobalISel/regbankselect-sextload.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-shl.mir | 2 +-
.../GlobalISel/regbankselect-sitofp.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-smax.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-smin.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-smulh.mir | 4 +--
...gbankselect-split-scalar-load-metadata.mir | 6 ++--
.../AMDGPU/GlobalISel/regbankselect-ssube.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-sub.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-trunc.mir | 4 +--
.../AMDGPU/GlobalISel/regbankselect-uadde.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-uaddo.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-ubfx.mir | 2 +-
.../GlobalISel/regbankselect-uitofp.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-umax.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-umin.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-umulh.mir | 4 +--
.../regbankselect-uniform-load-noclobber.mir | 4 +--
.../regbankselect-unmerge-values.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-usube.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-usubo.mir | 2 +-
.../regbankselect-waterfall-agpr.mir | 2 +-
.../regbankselect-waterfall-call.mir | 2 +-
.../regbankselect-whole-wave-functions.mir | 6 ++--
.../regbankselect-widen-scalar-loads.mir | 6 ++--
.../AMDGPU/GlobalISel/regbankselect-xor.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-zext.mir | 2 +-
.../GlobalISel/regbankselect-zextload.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect.mir | 2 +-
.../AMDGPU/GlobalISel/unmerge-sgpr-s16.mir | 2 +-
.../ARM/GlobalISel/arm-regbankselect.mir | 4 +--
...print-parse-verify-failedISel-property.mir | 2 +-
.../TypeInfoforMF_skipCopies.mir | 2 +-
.../Mips/GlobalISel/regbankselect/add.mir | 2 +-
.../Mips/GlobalISel/regbankselect/add_vec.mir | 2 +-
.../Mips/GlobalISel/regbankselect/bitwise.mir | 2 +-
.../Mips/GlobalISel/regbankselect/branch.mir | 2 +-
.../GlobalISel/regbankselect/brindirect.mir | 2 +-
.../Mips/GlobalISel/regbankselect/bswap.mir | 2 +-
.../Mips/GlobalISel/regbankselect/ctlz.mir | 2 +-
.../Mips/GlobalISel/regbankselect/fabs.mir | 4 +--
.../GlobalISel/regbankselect/fabs_vec.mir | 2 +-
.../Mips/GlobalISel/regbankselect/fcmp.mir | 4 +--
.../Mips/GlobalISel/regbankselect/fence.mir | 2 +-
.../GlobalISel/regbankselect/float_args.mir | 4 +--
.../float_arithmetic_operations.mir | 4 +--
.../regbankselect/float_constants.mir | 4 +--
...oating_point_vec_arithmetic_operations.mir | 2 +-
.../regbankselect/fpext_and_fptrunc.mir | 4 +--
.../regbankselect/fptosi_and_fptoui.mir | 4 +--
.../Mips/GlobalISel/regbankselect/fsqrt.mir | 4 +--
.../GlobalISel/regbankselect/fsqrt_vec.mir | 2 +-
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.../GlobalISel/regbankselect/store-rv64.mir | 2 +-
.../GlobalISel/regbankselect/vec-args-ret.mir | 4 +--
.../GlobalISel/instructions/anyext.mir | 2 +-
.../GlobalISel/instructions/ashr.mir | 2 +-
.../GlobalISel/instructions/copy.mir | 2 +-
.../GlobalISel/instructions/ctlz.mir | 2 +-
.../GlobalISel/instructions/ctpop.mir | 2 +-
.../GlobalISel/instructions/cttz.mir | 2 +-
.../GlobalISel/instructions/fcopysign.mir | 2 +-
.../GlobalISel/instructions/fneg.mir | 2 +-
.../GlobalISel/instructions/fshl.mir | 2 +-
.../GlobalISel/instructions/fshr.mir | 2 +-
.../GlobalISel/instructions/implicit_def.mir | 2 +-
.../GlobalISel/instructions/lshr.mir | 2 +-
.../GlobalISel/instructions/rotl.mir | 2 +-
.../GlobalISel/instructions/rotr.mir | 2 +-
.../GlobalISel/instructions/shl.mir | 2 +-
.../CodeGen/X86/GlobalISel/isel-fcmp-i686.mir | 2 +-
.../test/CodeGen/X86/GlobalISel/isel-fneg.mir | 2 +-
.../X86/GlobalISel/isel-fp64-to-sint-x86.mir | 2 +-
.../X86/GlobalISel/isel-sint-to-fp64-x86.mir | 2 +-
.../CodeGen/X86/GlobalISel/llvm.sincos.mir | 2 +-
.../X86/GlobalISel/regbankselect-AVX2.mir | 4 +--
.../X86/GlobalISel/regbankselect-AVX512.mir | 4 +--
.../X86/GlobalISel/regbankselect-X32.mir | 4 +--
.../X86/GlobalISel/regbankselect-X86_64.mir | 4 +--
.../regbankselect-dbg-value-physreg-crash.mir | 4 +--
.../regbankselect-sse-intrinsics.ll | 2 +-
.../X86/GlobalISel/regbankselect-x87.ll | 4 +--
llvm/test/CodeGen/X86/GlobalISel/sqrt.mir | 2 +-
381 files changed, 495 insertions(+), 495 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index bc6b5df99d2e7..be5d2fa7d4df7 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -48,7 +48,7 @@
#include <optional>
#include <utility>
-#define DEBUG_TYPE "regbankselect"
+#define DEBUG_TYPE "reg-bank-select"
using namespace llvm;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index d28d5c8c556a7..19ba2f5ca6fb5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -32,7 +32,7 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"
-#define DEBUG_TYPE "amdgpu-regbanklegalize"
+#define DEBUG_TYPE "amdgpu-reg-bank-legalize"
using namespace llvm;
using namespace AMDGPU;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index d7815341805bb..a9252cbd82722 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -28,7 +28,7 @@
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
-#define DEBUG_TYPE "amdgpu-regbanklegalize"
+#define DEBUG_TYPE "amdgpu-reg-bank-legalize"
using namespace llvm;
using namespace AMDGPU;
@@ -49,7 +49,7 @@ RegBankLegalizeHelper::RegBankLegalizeHelper(
bool RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
const SetOfRulesForOpcode *RuleSet = RBLRules.getRulesForOpc(MI);
if (!RuleSet) {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"No AMDGPU RegBankLegalize rules defined for opcode",
MI);
return false;
@@ -57,7 +57,7 @@ bool RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
const RegBankLLTMapping *Mapping = RuleSet->findMappingForMI(MI, MRI, MUI);
if (!Mapping) {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: none of the rules defined with "
"'Any' for MI's opcode matched MI",
MI);
@@ -502,7 +502,7 @@ bool RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
break;
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: lowerVccExtToSel, Opcode not supported", MI);
return false;
}
@@ -510,7 +510,7 @@ bool RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
B.buildMergeValues(Dst, {Lo.getReg(0), Hi.getReg(0)});
} else {
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: lowerVccExtToSel, Type not supported", MI);
return false;
}
@@ -575,7 +575,7 @@ bool RegBankLegalizeHelper::lowerUnpackBitShift(MachineInstr &MI) {
}
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: lowerUnpackBitShift, case not implemented",
MI);
return false;
@@ -612,7 +612,7 @@ bool RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
}
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: lowerUnpackMinMax, case not implemented", MI);
return false;
}
@@ -1084,7 +1084,7 @@ bool RegBankLegalizeHelper::lowerExtrVecEltToSel(MachineInstr &MI) {
B.buildMergeLikeInstr(Dst, {PrevLo, PrevHi});
} else {
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: ExtrVecEltToSel unsupported element type", MI);
return false;
}
@@ -1181,7 +1181,7 @@ bool RegBankLegalizeHelper::lowerInsVecEltToSel(MachineInstr &MI) {
B.buildMergeLikeInstr(Dst, Selects);
} else {
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: InsVecEltToSel unsupported element type", MI);
return false;
}
@@ -1463,7 +1463,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
break;
}
default:
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: Ext32To64, unsuported opcode",
MI);
return false;
@@ -1568,7 +1568,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
else if (Size / 128 == 4)
splitLoad(MI, {B128, B128, B128, B128});
else {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: SplitLoad, unsuported type",
MI);
return false;
@@ -1582,7 +1582,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
else if (DstTy == V6S16)
splitLoad(MI, {V4S16, V2S16}, V2S16);
else {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: SplitLoad, unsuported type",
MI);
return false;
@@ -1653,7 +1653,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
else if (DstTy == V6S16)
widenLoad(MI, V8S16, V2S16);
else {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: WidenLoad, unsuported type",
MI);
return false;
@@ -1691,7 +1691,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
GUnmerge *Unmerge = dyn_cast<GUnmerge>(&MI);
LLT Ty = MRI.getType(Unmerge->getSourceReg());
if (Ty.getSizeInBits() % 32 != 0) {
- reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ reportGISelFailure(MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: unmerge not multiple of 32",
MI);
return false;
@@ -2283,13 +2283,13 @@ bool RegBankLegalizeHelper::applyMappingDst(
}
case InvalidMapping: {
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: missing fast rule ('Div' or 'Uni') for", MI);
return false;
}
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: applyMappingDst, ID not supported", MI);
return false;
}
@@ -2549,7 +2549,7 @@ bool RegBankLegalizeHelper::applyMappingSrc(
}
default:
reportGISelFailure(
- MF, MORE, "amdgpu-regbanklegalize",
+ MF, MORE, DEBUG_TYPE,
"AMDGPU RegBankLegalize: applyMappingSrc, ID not supported", MI);
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 437be2b429356..bd21d5ca650dc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -21,7 +21,7 @@
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Support/AMDGPUAddrSpace.h"
-#define DEBUG_TYPE "amdgpu-regbanklegalize"
+#define DEBUG_TYPE "amdgpu-reg-bank-legalize"
using namespace llvm;
using namespace AMDGPU;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
index 247522a0dd43b..f55f183b92eee 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
@@ -24,7 +24,7 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"
-#define DEBUG_TYPE "amdgpu-regbankselect"
+#define DEBUG_TYPE "amdgpu-reg-bank-select"
using namespace llvm;
using namespace AMDGPU;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index d70ed52f69511..f6cab36a2eb70 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -1,5 +1,5 @@
-# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=regbankselect %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
-# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=regbankselect %s -regbankselect-greedy -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
+# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=reg-bank-select %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
+# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=reg-bank-select %s -regbankselect-greedy -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
--- |
; ModuleID = 'generic-virtual-registers-type-error.mir'
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir
index deb3945a75bcb..b2a60e7015721 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: saddlp1d
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir
index 04aefb9207e79..5c2e39c60ce1b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
# Check we don't crash given an non-generic implicit_def. These may
# come from swifterror handling in the translator.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
index 79827da26dc31..e81b552da2bcc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
# Check we don't crash because of an unhandled new regclass GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID.
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir b/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
index 3b1b15ac4c4b0..40a3a1ba074ef 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -o - %s | FileCheck %s
---
name: test_large_merge
legalized: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-align.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-align.mir
index 618a4532b2362..145fce5ce88ce 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-align.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-align.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for G_ASSERT_ALIGN.
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
index dc7c0d41ede57..a50b8c3ec64b9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for G_ASSERT_SEXT.
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
index c4b9875a0ed78..9412e03351f99 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for G_ASSERT_ZEXT.
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
index 34fe6ad790276..1d26a9af1f72f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
index 351c4f5b1bed0..bbe3b9aaed934 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for G_DUP.
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
index 03bc74f2d5569..6cf06feba9deb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect -global-isel-abort=1 %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=reg-bank-select -global-isel-abort=1 %s -o - | FileCheck %s
name: v2s32_fpr
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir
index 688ee7bb55bcc..253ad4483cf3a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+lse -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+lse -verify-machineinstrs -O0 -run-pass=reg-bank-select %s -o - | FileCheck %s
---
name: extract_s64_s128
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir
index c7acd761b2bda..46e6b51e256e1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
index 4de22f72bb3fa..52f9208d24cea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -o - | FileCheck %s
+# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir
index de30c9138c023..67d3bbe492db1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: direct
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir
index 9a692cf61c725..09c616ff054fb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: direct
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
index 8496c0d39157e..efb80df7cb212 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select %s -o - | FileCheck %s
# Check that we correctly assign register banks based off of instructions which
# only use or only define FPRs.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
index 4053859d2ef63..6841a27c056eb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=reg-bank-select %s -o - | FileCheck %s
---
name: inlineasm_memory_clobber
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
index abf19cc44835f..aec23c9e2d094 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select %s -o - | FileCheck %s
# The following should hold here:
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
index 609e03d39cdde..6cc550652cc82 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -mattr=+fullfp16 %s -o - | FileCheck %s
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -mattr=+fullfp16 %s -o - | FileCheck %s
# CHECK-NOT: gpr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
index ce4f8cbee4017..7edf41ae76e99 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -o - | FileCheck %s
+# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
index 5a888778a2f5a..040f238cacaae 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for intrinsics with known constraints. (E.g. all
# operands must be FPRs.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
index 60200c04a20a3..91ab7cac30f7e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
index c694105ffd02e..b26baad631950 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
index 6e87604318d6c..4788ce2bdad4c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
index e04244e2d4488..7db62e0a87f3e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
index 79ac6e46bf332..5040ad341ccdb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=regbankselect -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
index dd36fe2c09466..aa410735edfae 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir
index 9bcdb3e077183..09d4a664e44a5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: shl_cimm_32
legalized: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir
index 09b4fe7ff58b8..6284f0b56c1ff 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=reg-bank-select %s -o - | FileCheck %s
---
name: trunc_s64_s128
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
index 1378c2a2e11b5..2a0ab36dbf0f9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: build_vec_f16
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
index d98daf188d795..b1a6d708b6f9f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
index 8900f0e78f833..2460e969c8889 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select %s -o - | FileCheck %s
# Check the default mappings for various instructions.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir
index 14e4abe3bd0af..230ee869b6253 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir
index c6e3a53cb71a2..968277d45a07a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=regbankselect -global-isel-abort=1 %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=reg-bank-select -global-isel-abort=1 %s -o - | FileCheck %s
---
name: fadd_v2s32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir
index 9e3273c5abd18..73931140df2ed 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -mtriple aarch64-- -o - -run-pass regbankselect | FileCheck %s
+# RUN: llc %s -mtriple aarch64-- -o - -run-pass reg-bank-select | FileCheck %s
---
# CHECK-LABEL: foo
# Check that we produce a valid mapping for REG_SEQUENCE.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
index 4bcd7155e849a..b533e9f85078b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: unmerge
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index c067696035126..ce07431ad3578 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-- -run-pass=regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-- -run-pass=reg-bank-select,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
index a10a5c80397b8..651efcbfd754f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# GPR variants should not use INSERT_SUBREG. FPR variants (DUP<ty>lane) should.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
index 69789b3bef9be..2f1f0ae285c92 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: readanylane_to_virtual_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
index 379377d8127b1..79c107bfaad05 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: abs_sgpr_s16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
index 77dffb1954a0b..77a614d89e849 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: add_s16_ss
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
index f2de7a4b57529..c6f0124ac9bbc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: add_s16_ss
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
index f6552a1ac6a18..f4232ed440e0e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: add_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
index 4dbe700d7c3d6..f153f02e2f05e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: add_v2s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
index e7b7823f10809..8dd947e4a459e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: exp_compr_v2f16_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
index 25b183be7aada..ad29404b6d1a1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
--- |
define amdgpu_ps void @exp_s(float inreg %v0, float inreg %v1, float inreg %v2, float inreg %v3) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
index 96ec9d283c03d..1efd7462f3230 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
---
name: buffer_load_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
index 6eb5c7dbfa50c..4a2d3ee405d41 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ballot_sgpr_src
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
index 559e5c11486a0..b06a6db73bf37 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: class_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
index b2858617d9a70..51b73df884e55 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: cvt_pkrtz_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
index f2b130d88c5e8..ff6ce7d2e2934 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: div_fmas_sss_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
index 36c1f8994fb8d..2539c72044d29 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: div_scale_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
index 03ef8166367a6..1be36a60a93a5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_append_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
index 96365b551647f..6f635d8e09002 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_bpermute_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
index e3ecdf63817a9..45e8d0debb86d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_consume_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
index 9bcab047006a5..5ba4faefa8092 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ds_gws_init_s_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
index d0a7f95a52c6c..01736eb7c46cd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ds_gws_init_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
index f846438b51c7c..bbcecb186c4ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ds_ordered_add_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
index 335bcc912280f..a87fc081537ae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ds_ordered_swap_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
index aacac0c7c0ba9..52cff72aa3bf1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_permute_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
index 34d37e32fe358..4ee1688ad0da9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ds_swizzle_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
index f14945ae39eab..f065b4d0e615e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgpu11.00 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgpu11.00 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: else
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
index 2058b0b1cb604..f6d116bc42e86 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: else
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
index c3c292c359bfb..376bca07c82d5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
---
name: fcmp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
index 385c96f184f8a..0756e6d6bbeee 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: fmul_legacy_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
index e9f13465a611e..80683ba20cf6b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: groupstaticsize
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
index 860dcb8632115..8f7f014e09e5a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
---
name: icmp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
index d1006c18bd1a8..4e5abfdca0050 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
-; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
; Natural mapping
define amdgpu_ps void @load_1d_vgpr_vaddr__sgpr_srsrc(<8 x i32> inreg %rsrc, i32 %s) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
index 4ad8eb432c676..548824b05c507 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
; Natural mapping
define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
index 9c028c16b8dc3..d60f122545431 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_mov_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
index 76286b091f887..2c920f75e289e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_p1_f16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
index 3b43ea9f79f01..08ea7aba39698 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_p1_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
index 941a97094753b..3f22072d64827 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_p2_f16_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
index 2a76661850df0..8a2f5920c485a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: interp_p2_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
index db2fccd04b74b..94ecc203e7931 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s| FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s| FileCheck %s
---
name: kill_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
index f5666a1acd0f5..f5e1ea5886989 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: lds_direct_load_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
index bcef6b6e27847..7ad25941c6952 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: lds_param_load_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
index 7db93700d394c..efd9b02760d11 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: live_mask
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
index b86969cc49f6c..45b17afa852ae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
---
name: mfma_f32_32x32x4bf16_1k_vva
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
index deae2d6b836f4..3ba277f8671ba 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.42 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
---
name: mfma_i32_16x16x32_i8_vva
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
index 6d1f2b98b7644..1ac907dd220c0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -verify-machineinstrs %s -o - | FileCheck %s
---
name: mfma_f32_32x32x1f32_vva
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
index 338266407c236..4051cda04c92d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: ps_live
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
index 9a7f82c02c52b..37060571106b3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefix=GFX7
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefix=GFX7
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250
; Natural mapping
define amdgpu_ps i32 @ptr_s_buffer_load_i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
index 5468f2462876b..2480b1b1ff167 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
index 77f6b1e90c590..4ae5d545e9bfd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps float @raw_ptr_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
index 7645cb187841a..623311c0fb3ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: readfirstlane_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
index e915de241996e..02c8f4564e13b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: readlane_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
index 8e985b16d322f..ace9eb5bee30b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.01-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefix=GFX7
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200
-; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.01-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefix=GFX7
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200
+; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250
; Natural mapping
define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
index ca9b6ea03b538..9aff4a6f4b08d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=regbankselect -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
-# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=regbankselect -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
+# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=reg-bank-select -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=reg-bank-select -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
# We see the offset is a VGPR, but this is due to a constant for some
# reason ending up in a VGPR. This shouldn't really ever happen, but
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
index 371e70d4f58ce..995486d6deb42 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: s_get_waveid_in_workgroup
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
index 0742f25f01251..257a7297659b1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: getpc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
index 078b49c1a2149..d9335084ba9f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: getreg
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
index cc368accdc889..fa5950bd276de 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: memrealtime
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
index 9dcdc87189969..f4b16267b05e9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: memtime
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
index 26c4713df1b8d..d445d4012d9bb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: sendmsg_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
index 27e92f7a0a9b9..c02e09fa3057f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: sendmsghalt_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
index d327372fc7c86..6f2c21fcfd4b7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
index 8ca6f705fac04..fcdf5421f666d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
index 195fd39eebf19..01f8b628125bf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps float @struct_ptr_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
index 39ae330f17582..7b1270c9517aa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s
; Natural mapping
define amdgpu_ps void @struct_ptr_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
index 6a1b93c4a7b7d..b3de77b8b43ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: update_dpp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
index 300c26d4aa942..067c27c082144 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: wqm_demote_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
index 841c2ed5d1f40..5e0e43e7a087e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: wqm_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
index 0fb152ee6661b..c139129243772 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: wqm_vote_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
index 30d6d249a69f5..e7ad79a42e595 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: writelane_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
index 7d9ee916ea297..cd3e2acf887bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: strict_wwm_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
index 8152ac7738841..e511bd46a90d2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ffbh_u32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
index c03dbc6e78225..6738775796f97 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ffbl_b32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
index a8ca04bfcbf2f..ee8c929731229 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
# TODO: We could use scalar
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
index c9c7956081d2f..dc0876f9aca41 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: and_s1_sgpr_sgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
index a63c9cfc80c92..6e2b54e84422b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: and_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
index e93a86cf81a5a..72e9d29bed4bb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: anyext_s32_to_s64_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
index 65a9a84750975..10be7671cdbe1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: ashr_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
index b8caeb60ebefc..8e4cc927c3154 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -o - | FileCheck %s
---
name: assert_align_vgpr_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
index 9d7f866581e1e..7e4064c1ee164 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: assert_sext_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
index 01b6d97237557..b9e74e3477d32 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: assert_zext_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
index 8e807200f692c..09c05ec1c5dab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: amdgpu_atomic_cmpxchg_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
index 5c11018753bb9..24ca47fef2fe0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
# Test G_ATOMICRMW_ADD and G_ATOMICRMW_SUB register bank selection and legalization
# for different address spaces (flat P0, global P1, local P3) and data sizes (S32, S64)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
index 42672c114b0ac..c3b8f0b2192d2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_add_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
index 53a35114495ea..2047834023ff1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_and_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
index 835e33fafdbfe..144157b8ea406 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_fadd_global_f32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
index d31d037f6f8d1..0fd72e1b041d3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.42 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
# Test G_ATOMICRMW_FADD with V2F16 (V2S16) type - register bank selection and
# legalization for flat, global, and local address spaces.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
index 5b6754b0d9b44..ecd079e8f9655 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_max_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
index 4c318b2433d5a..1f315a9d6c050 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_min_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
index b4cce7cf68793..ba7423e471444 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
# Test G_ATOMICRMW_MIN, G_ATOMICRMW_MAX, G_ATOMICRMW_UMIN, G_ATOMICRMW_UMAX
# register bank selection and legalization for flat, global, and local address spaces.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
index d7360f991dcce..c63966961ceda 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_or_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
index cefb2884d6eb7..f7db0780bd1c0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_sub_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
index ed7037c4a9a6c..b21819dd24e9c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
# Test G_ATOMICRMW_UINC_WRAP and G_ATOMICRMW_UDEC_WRAP
# register bank selection and legalization for flat, global, and local address spaces.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
index 15e644a06329b..3a2f5a7239379 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_umax_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
index ac1b131e408e1..4f9459b0bfc1b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_umin_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
index d7f4e495aafef..9aa17d395970b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_xchg_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
index f449d18aa25bb..3528cb1cbacda 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: atomicrmw_xor_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
index 6b740b0718764..0e0c027b84870 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: bitcast_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
index fa052aa43f409..4fa8b386febf1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: bitreverse_i32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
index d8041de8f3211..db3e68d8be193 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
index 7e84b13e860f5..68e24f8e0185c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: brcond_vcc_cond
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
index 22ff82ab96851..4bf9d6e13f053 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: bswap_i32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
index 5cff5f840d271..4767301be5590 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: build_vector_v2s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
index b9afd0dbdb7d7..1c4bab48d2bbd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -stop-after=amdgpu-reg-bank-legalize -regbankselect-fast -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -stop-after=amdgpu-reg-bank-legalize -regbankselect-greedy -o - %s | FileCheck %s
define amdgpu_ps void @test_uniform_indirect_call_p0(ptr inreg %fptr) {
; CHECK-LABEL: name: test_uniform_indirect_call_p0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
index 062d2ecf3ab1e..cf2b7558a0af7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -verify-machineinstrs -o - %s | FileCheck %s
---
name: concat_vectors_v4s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
index b1b21f0affd0d..f4e1464a6409e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: test_constant_s32_vgpr_use
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
index 6dee24326021f..089c41fb7c10f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck --check-prefix=WAVE32 %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck --check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck --check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck --check-prefix=WAVE32 %s
---
name: copy_s32_vgpr_to_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
index 73dfc76460456..29fb7b7491a4b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: ctlz_zero_poison_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
index b472f8f41f2bf..7d1cc74b7edbc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: ctpop_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
index 6da1b43e4356a..ec3f5e0148cc1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: cttz_zero_poison_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
index 5596f232535eb..deeb4469409bf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
# Check the default mappings for various instructions.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
index 472d6e9af0833..40b969b7adf3a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE64 %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE32 %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
index d3e9ed16af3d3..621a1fe635755 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefix=WAVE64 %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck -check-prefix=WAVE32 %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
index d4dd6647d6647..128a52568c859 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: fabs_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
index ca79422c5e059..f87e14855ff2c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: fadd_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
index 8a09c002c5e7e..432e93057846e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: fcanonicalize_s16_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
index 74c2bc0c03b77..ce0b8bdcabe02 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: fceil_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
index 68c292ecb94bf..92c4a655b453e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX803 %s
-# RUN: llc -mtriple=amdgpu11.50 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX1150 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX803 %s
+# RUN: llc -mtriple=amdgpu11.50 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX1150 %s
---
name: fcmp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
index 32fb11be5fcdc..e6f1c253c66e2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX8 %s
-# RUN: llc -mtriple=amdgpu11.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX11 %s
-# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX12 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX8 %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX11 %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX12 %s
---
name: fexp2_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
index cefb21f186f32..1495c447f1305 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: ffloor_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
index e4800ce6f0add..a1d1355cf54cf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: flog2_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
index 323eac10576e5..8cb44a7f5ff54 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: fma_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
index 50ed86bd79e3f..c7aaf8241cc93 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: fmul_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
index 2fce2409e38b0..fd4cdc5a59fdd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: fneg_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
index 9c621513365ad..ebe97ae369cd2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fpext_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
index 086b7d81132e8..7f4abf3135c1f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize -o - %s | FileCheck %s
---
name: fptosi_sat_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
index 9dadcbc9cd525..b4b290b22cd58 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: fptosi_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
index 26fcaa76cb721..4fa8c71fc3547 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize -o - %s | FileCheck %s
---
name: fptoui_sat_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
index b72a3df834b0b..f9d5d8107aa4d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: fptoui_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
index 511cf9338be25..8f35440ccd774 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fptrunc_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
index d4a5500f5ce16..a337166f9aca0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: test_frame_index_p5
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
index e4dd859b0cb2f..7569b9d93ab71 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: test_freeze_s1_vgpr_to_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
index 49bf19b061cc9..0d7a557b8963d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -verify-machineinstrs -o - %s | FileCheck %s
---
name: fshr_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
index 06ea3c1d0db3c..b2fb47c86de98 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
-# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefixes=GCN,GFX12 %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck -check-prefixes=GCN,GFX12 %s
---
name: fsqrt_s16_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
index f64a47863188f..f6baa9911d983 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fsub_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
index 7bd6c1b8f9cc9..7baf9c5d535ae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
-# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
---
name: icmp_eq_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
index 5d4fab4a4bd24..7e196b78aef69 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
---
name: icmp_eq_s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
index 512eeeb65eb0f..4a03cf68dd2ea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
@@ -1,5 +1,5 @@
-# RUN: not llc -mtriple=amdgpu6.00 -run-pass=regbankselect -regbankselect-fast -filetype=null %s 2>&1 | FileCheck %s
-# RUN: not llc -mtriple=amdgpu6.00 -run-pass=regbankselect -regbankselect-greedy -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select -regbankselect-fast -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select -regbankselect-greedy -filetype=null %s 2>&1 | FileCheck %s
# Check behavior for illegal copies.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
index 0e629d608ef5b..694d4d6110f7e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s
-# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s
---
name: test_implicit_def_s32_vgpr_use
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
index 384df19a942f6..b6e2e1b1c74fa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: insert_vector_elt_v4i32_s_s_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
index 95fb62e125564..cc32020b8324d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: intrinsic_roundeven_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
index 9c2527ccdafaf..d5b26f1ebb847 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: intrinsic_trunc_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
index a788e7b5e65bc..cea46cfc9e496 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: inttoptr_s_p0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
index e017b62c85dd7..e5b81a7d12ba4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu7.01-amd-amdhsa -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX7
-# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.00-amd-amdhsa -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX12
-# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.50-amd-amdhsa -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s -check-prefixes=GCN,GFX12
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu7.01-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX7
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.00-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX12
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.50-amd-amdhsa -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s -check-prefixes=GCN,GFX12
--- |
define amdgpu_kernel void @load_global_v8i32_non_uniform(ptr addrspace(1) %in) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
index 0538f6ee760c3..73d35645974f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: lshr_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
index 78aea1e6474a0..bde91128cd981 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX8 %s
-# RUN: llc -mtriple=amdgpu9.0a -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX9MI %s
-# RUN: llc -mtriple=amdgpu10.30 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX10 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX8 %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX9MI %s
+# RUN: llc -mtriple=amdgpu10.30 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX10 %s
---
name: mad_u64_u32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
index cb8aec728d984..e0ed06d3cfa54 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: merge_s64_s32_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
index b62b53ea13aa2..3ef155ff6ff46 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: uniform_in_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
index b7387c6d32507..6cbae4620913a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s
---
name: uniform_in_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
index 27d5ccbe29ece..a53a428278f95 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX10
-# RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX12
-# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX10
-# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX12
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX10
+# RUN: llc -mtriple=amdgpu12.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX12
+# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX10
+# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX12
---
name: salu_float
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
index d7fdf3be05c80..42427e9e38a83 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS
-# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS
+# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS
---
name: uniform_in_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
index 5de0179eb503b..29c70223d70dc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: mul_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
index 9747902237533..bec296743a084 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: or_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
index c477c8c41a703..f983ba491bd9f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
---
name: phi_s1_scc_scc_sbranch
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
index 4b7b7c29c2d02..4ef2ade9d2ad3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
-# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
---
name: phi_s32_ss_sbranch
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
index 8ba950e16fb62..36242dbcb1529 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: v_s_exp_f32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
index a8c134f213988..795639267a30b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
---
name: gep_p0_s_k
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
index f64b16b53ffd0..41f7a939f09ae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ptrmask_p1_s_k
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
index 8541e284c8ddb..edddc69f4023b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: ptrtoint_s_p0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
index 9de1a0820935d..4eb7ba24af649 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: reg_sequence_ss_vreg
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
index 96ab2d06f3584..81d7223c7c8c4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: sadde_s32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
index 2ccb566fd85f6..a43e5d69205f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu11.50 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX1150 %s
+# RUN: llc -mtriple=amdgpu11.50 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX1150 %s
---
name: fadd_f32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
index c77bdc4cb1b1a..61d1d746f9c85 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
index 6c4f87a6ec0c3..e03e3440847c3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: select_s32_scc_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
index fdb63e5440ab0..cd8f9d9c9f9b7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: sext_inreg_s_s32_1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
index 7e8e0ff2228e2..3db0910882ef1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: sext_s32_to_s64_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
index 9d8759eefa5dd..0e81717e4a027 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: sextload_constant_i8_to_i32_uniform
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
index 85a093b04cdcc..15b550aaabc79 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -o - %s | FileCheck %s
---
name: shl_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
index 91a29a0b12743..4f7f66ddf66e4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: sitofp_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
index 7c67d955e6205..86e507a80e203 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: smax_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
index db21e4fdeb936..aa466c699f9f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: smin_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
index 68057f031eccc..cf537e8fb1075 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX6 %s
-# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck -check-prefix=GFX9 %s
---
name: smulh_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
index 87c9d5eb1a60a..0bbafccef1fd8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01-mesa-mesa3d -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX7 %s
-# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX12 %s
-# RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgpu7.01-mesa-mesa3d -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck -check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck -check-prefix=GFX12 %s
--- |
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
index 2faca040ab1d1..e809d5fb8449a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -o - | FileCheck %s
---
name: ssube_s32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
index 0b6964129a732..8f48bdccfb7ca 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: sub_s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
index 2774db98136ab..d9748f938e9a1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX6 %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX8 %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX6 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX8 %s
---
name: trunc_i64_to_i32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
index 46ff97b0a0d94..c1631a9831d4c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: uadde_s32_sss
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
index 0cd95240909b1..fc48a4989190a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: uaddo_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
index 8571a3df50aff..73b59bb86c1f0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
index bf3c5a2cd2bbc..9603a79a3ae63 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: uitofp_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
index 485658e94ce2e..aeb808f433f9b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: umax_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
index 46021b59175fb..df02a8fd88b83 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck %s
---
name: umin_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
index 6bd70bd80cd01..2fa6163d53497 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX6 %s
-# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' -o - %s | FileCheck -check-prefix=GFX9 %s
---
name: umulh_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
index b39fd4b068486..40ee28a8178bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.00-amd-amdpal -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX7 %s
-# RUN: llc -mtriple=amdgpu10.10-amd-amdpal -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX1010 %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdpal -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX7 %s
+# RUN: llc -mtriple=amdgpu10.10-amd-amdpal -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX1010 %s
# FixMe: need merge/unmerge artifact combine
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
index 4af8881a3e894..8b6a948569ce0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: test_unmerge_s64_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
index 195d5588b44d1..331731d5d15ea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize %s -verify-machineinstrs -o - | FileCheck %s
---
name: usube_s32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
index 5f145cee4d11b..3e5bb73529480 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-reg-bank-select,amdgpu-reg-bank-legalize' %s -verify-machineinstrs -o - | FileCheck %s
---
name: usubo_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
index 2a4c79d1f9954..bb7279f9cc559 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -verify-machineinstrs -run-pass=regbankselect -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -verify-machineinstrs -run-pass=reg-bank-select -o - %s | FileCheck %s
# Make sure that an arbitrary AGPR is treated as a divergent value
# that needs to be copied to VGPR, and then waterfalled
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
index 135fb6e444c33..1227176114e8f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -run-pass=amdgpu-reg-bank-select,amdgpu-reg-bank-legalize -o - %s | FileCheck %s
---
name: waterfall_divergent_call_p0_no_args
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
index 74e62e4e5b8a9..aae10cb7aa55a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu12.00--amdpal -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu12.00--amdpal -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
-# RUN: llc -mtriple=amdgpu12.00--amdpal -mattr=+wavefrontsize64 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00--amdpal -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00--amdpal -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00--amdpal -mattr=+wavefrontsize64 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: basic_test
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
index 329b205419c62..4ea502dd94c7e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
-# RUN: llc -mtriple=amdgpu9.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
---
name: constant_load_i8_align8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
index 4cac975636740..311ff66bc3563 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: xor_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
index 6c6f41293f4ab..3dd82d58284b2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: zext_s32_to_s64_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
index 52b434b76ba6b..7ec038b3ecdc9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" -verify-machineinstrs -o - %s | FileCheck %s
---
name: zextload_constant_i8_to_i32_uniform
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
index f976217350185..8623911456922 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01 -mattr=+flat-for-global -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.01 -mattr=+flat-for-global -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -o - | FileCheck %s
--- |
define amdgpu_kernel void @load_constant(ptr addrspace(4) %ptr0) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
index ed9ee19acbe29..149ebee8c6c2c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgpu11.00 -run-pass=amdgpu-regbanklegalize -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass=amdgpu-reg-bank-legalize -verify-machineinstrs %s -o - | FileCheck %s
---
name: unmerge_sgprS16_from_V2S16
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index 7b530cef67ebc..951d7eb1cfa68 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -1,5 +1,5 @@
-# RUN: llc -debugify-and-strip-all-safe=0 -mtriple arm-- -run-pass=regbankselect %s -o - | FileCheck %s
-# RUN: llc -debugify-and-strip-all-safe=0 -mtriple thumbv7-- -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe=0 -mtriple arm-- -run-pass=reg-bank-select %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe=0 -mtriple thumbv7-- -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
define void @test_add_s32() { ret void }
define void @test_sub_s32() { ret void }
diff --git a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
index a4a5533ff2c2b..c53a0ce405785 100644
--- a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
@@ -2,7 +2,7 @@
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
#
# RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \
-# RUN: -start-after=regbankselect -stop-before=finalize-isel \
+# RUN: -start-after=reg-bank-select -stop-before=finalize-isel \
# RUN: -simplify-mir -verify-machineinstrs %s -o - 2>&1 \
# RUN: | FileCheck %s --check-prefix=FALLBACK
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
index 011a05e133759..c2c6c84c0c821 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @skipCopiesOutgoing(ptr %ptr_a, ptr %ptr_b, ptr %ptr_c) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
index a1c41fad4250f..0160440a47181 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @add_i32(i32 %x, i32 %y) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
index a963d2dc500e5..ad01a4d916f0c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @add_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
index e5cc1d9eb7dcb..78145c8eff966 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
index 28416f116d0b7..6c9a2410a0e4a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @Unconditional_branch(i32 %a, i32 %b) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
index 918cf4ee236b1..d42da94c798ac 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @indirectbr(ptr %addr) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
index c50e81eae0c93..902537a4c4534 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
+# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
--- |
define void @bswap_i32() { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
index 93896f6ea01ba..6a9853c6bc6fb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
---
name: ctlz_i32
alignment: 4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir
index f7fe5a0a7c0a3..ccaa6a6b5b034 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fabs_f32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
index 2b0476f3efcb3..3bdf9b86e4260 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @fabs_v4f32(ptr %a, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir
index 6673980b4b101..96192b7e55a78 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @oeq_s() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
index 9c7ec54d97435..dbd9b315c201b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @atomic_load_i32(ptr %ptr) { ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
index 7886a9dfa2233..5ad6d4863fbf7 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir
index 49bd7702af848..cee5c4cef7d45 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir
index 1eca0d3b96ac4..94b7329dcdc2a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
index b696be65dee6d..e1ffcb87e777f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @fadd_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir
index 52c751e8c477d..d14499510f998 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fpext() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir
index 74c1a7dcc7fe3..e5c6dfd3b26bb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @f32toi32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir
index a9ca2f2515ddc..b9aab7e884900 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @sqrt_f32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
index a918bae094b17..f152949e22d85 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sqrt_v4f32(ptr %a, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
index 0e20bc7cb95db..e5a311e86556c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
@.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00"
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
index d53b1575ca7f8..8359af16044bb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -relocation-model=pic -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -relocation-model=pic -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
declare i32 @f(i32, i32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
index 611ba0718c199..a40d89eaf72bb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @ne_i32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir
index dc88bb817f76c..639a723b3d416 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
declare void @f_i32(i32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
index b7eda46de75db..a289c2e8f4d76 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @inttoptr() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
index 56c629a292ce8..b1e63839aba2f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @mod4_0_to_11(i32 %a) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
index 3f0b20cd422c3..25a4d2a107acc 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @load_i32(ptr %ptr) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
index 142d7ea31e5cb..5da84fc790d72 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
index 64117a2d82635..76dba09573596 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @load_store_v16i8(ptr %a, ptr %b) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
index 319bb2bf446ff..a2cef932b0f08 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
index 319bb2bf446ff..a2cef932b0f08 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
index b0fc873c6d063..6decdd9cb32e3 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
index 4d6bce2063d49..2292396bd4844 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @mul_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
index dc758986e9fb4..5b7ba0922c72e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
index 044ab1320816e..1080d4364399a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @ptr_arg_in_regs(ptr %p) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
index b9b725e8e138c..238a2843627ae 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @sdiv_i32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
index cef6101e2038d..68e1cdb90b3e9 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sdiv_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
index 20f18fe704d56..1bdebc897ae86 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @select_i32(i32, i32) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
index fa893a2332e02..047ab470cff94 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @i32tof32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
index be2284f3df752..7e94793bc4d3b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
declare i32 @f(i32, i32, i32, i32, i32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
index 874056e8e88a3..a688060f7ed66 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @store_i32(ptr %ptr) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
index 3f705ebea309f..9e0b3608ba3d6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
index dcee70ce4b01e..d3350cffc385f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @sub_i32(i32 %x, i32 %y) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
index b2114a9fb3a1c..bc8153b342fc0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sub_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
index 0d81e0129def9..a73026f9af44b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @outgoing_gpr(ptr %i32_ptr) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
index 5ed6dc4fc55fb..0a5d01e806eb5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @load_store_i8(ptr %px, ptr %py) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
index 861f94bb0829c..60ec003b46d33 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
@.str = private unnamed_addr constant [11 x i8] c"string %s\0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
index 1ffed379a4ffc..0078fca55d88c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
index 187b3e68b1b7a..6074a9d6fda9b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @zext() {entry: ret void}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
index 1b6684dc42397..8384c1a812b84 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
index cef929f1e05be..37caf893f487d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
index 1296d5f3cbfa1..ebbf138764e04 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
index 98c0707128a41..7a54917ae50af 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
index 9cc0b579ed48e..b4b2bac3e2087 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir
index 2a3f8bdc4d3e0..9963ffdf48502 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir
index 518ef4488aa44..3e4433527c969 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir
index 7020a0ba8709d..50caa81a5b0e5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir
index 48f7c4fda396a..ea253cd75758c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
index 1ef5c48f0b5b6..d3fd2b108f812 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
index 2801faf76820b..8d53f205b4c2c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir
index 7758a640ac860..95e3dd1b51e4f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d,zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d,zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+d,zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d,zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir
index 1ed7ceea2f650..aa7fdc4579601 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
index f74362298a6cb..a0eb1e0626f25 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s --check-prefixes=CHECK
-# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s --check-prefixes=CHECK
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
index 7dee1370f283d..a1221a2f2374e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
index e7f9500373721..d4fdfdb8afd35 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
index 346dd28eb3778..c9d9704c2b5ad 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
index d63803f8f5bdf..10cb8c7802574 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir
index 10fb4f6ba4596..7463ab51a952d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
index d5c2875d316cb..49f898ff9dc34 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
index f701ef6169625..aa2b12764232f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select %s -o - \
# RUN: | FileCheck %s
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select %s -o - \
# RUN: | FileCheck %s
--- |
define ptr @frame_index() {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
index b43371ad40d72..f04f4dc82d400 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
index c4196b06e3319..245d8f9cec361 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
index f084af59fdf4d..e356e66b9c93b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=reg-bank-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32F %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir
index caece8b68ce0b..8c7eaa457ee26 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64D %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir
index 9224579d6bd78..434fa91112740 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=reg-bank-select -verify-machineinstrs %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir
index 9bf796d1f55e9..3da5e647ed425 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=reg-bank-select -verify-machineinstrs %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir
index ad0b73e6bef92..7703cdf31f757 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select -verify-machineinstrs %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir
index 9e602b3ed94c3..2e966a492077f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select -verify-machineinstrs %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
index 02e5a9a982ed0..86ecb3abb6811 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
index 5b48a7e947ae6..d7a0ec6b187e4 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir
index e4e9af7a0f6d8..910d9c8812f9c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
index 6cb38cf38a6a5..26b75f7c6887f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
index b7fd2a3ce01aa..867126456bccf 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
index 56cac99a2b411..c39379a343c36 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
index 45e96b152f875..4dfcdb1db8344 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
index 77fb05edd7ec3..ecc7c623a379d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir
index 4785b86a8a786..069362c1a8a46 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
index 715ba22dc99bc..d1ed3e8b4e459 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
index 2fb680fd15d8f..97204599b6eb2 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
index 8feeebf37107e..402ea3fdbac23 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
index a1537ac0173e4..f0f0063f322e9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
index 089dd7ada0a9b..95da8318832df 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: ptrmask_p0_s32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
index e0e765e368d1d..25034f5f915e9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: ptrmask_p0_s64
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
index ab3d777856d6e..ccd88be116233 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
index 4d1b11b6921dd..2ebb4aeb2bb92 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
index 8447b3602165a..0783ecdfa6073 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir
index 017da0d536af7..687358c8ca99f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir
index b58e87c128218..7e7c67ba6702e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir
index 7e2badbc5cda9..4781d4c3fd041 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
index efd7f13e376a5..77a9b100edeba 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir
index 38d3e83c6dbc4..085a0805a631b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir
index efd5237253449..abd743ca3663e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir
index 3a6a2389d1db0..7dc7dcd9b2e82 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
index c18423cbe3758..4c6c5a46be3ee 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir
index abab3ccbbdfe1..4eaf1d7e5600e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir
index d4d7012567401..9c40d6a86f8ca 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
index 1d8e676b7c94b..1f846d01d195d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
index 47117dc0009b9..0fb4ff0c5420b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
index 5070c583c5f6b..b8a6f61450c21 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
index 5252b25b6f3b6..a8588a5c936a8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
index 47d396f4eb381..ed3b1370996f3 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
index 544c3bb06a106..ed9b5f8211a1e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
index c3475dd64789a..4d85f5ade8b02 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
index 9ed3b678e9711..bfa1b90cb5aec 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefixes=RV32 %s
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefixes=RV64 %s
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir
index 4ce64cc824a82..ef664dcce989f 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: aext_i8_i32
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
index c81eba50ead57..5ee6c10a1f1ba 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: ashr_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/copy.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/copy.mir
index a692af7437071..d7ccd022b5d70 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/copy.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/copy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: copy_i32
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
index 4a5238cc535d5..d6e7b0f3203e3 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: ctlz_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
index 97c9ffb90a7cb..8e2d13a9d8950 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: ctpop_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
index cb4e099c66d60..268b9c0a48584 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: cttz_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fcopysign.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fcopysign.mir
index 9f7b0df4d9bba..1c91972074549 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fcopysign.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fcopysign.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: fcopysign_f32_from_f64
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir
index 82e959b0fcaf6..7686ea18881b6 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: fneg_f32
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
index d7e4daef5dc61..265694ce8e681 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: fshl_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
index c95466a33e311..d544220f8bee5 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: fshr_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
index 3498ff229ca81..7c9b8f91b1ecf 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: implicit_def_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
index 53805d9fae2cc..19d8cc82c8a81 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: lshr_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
index f977a269c8a34..ca20808769135 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
index 12fd666d7128a..1c3014b689125 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
index 296be9adeb440..ddbcdac0b6af6 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: shl_i32_i8
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
index 8273677592607..fc9792824a360 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# NOTE: This MIR test is required because the support for 64 bit memory ops is missing in i686 mode, Due to distinction between float/int types, support is expected in near future and there is this RFC in place https://discourse.llvm.org/t/rfc-globalisel-adding-fp-type-information-to-llt/83349. Once this support is introduced this test must be dropped and integrated into the LLVM IR tests.
-# RUN: llc -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=regbankselect,instruction-select -disable-gisel-legality-check -global-isel %s -o - | FileCheck %s --check-prefixes GISEL-X86
+# RUN: llc -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=reg-bank-select,instruction-select -disable-gisel-legality-check -global-isel %s -o - | FileCheck %s --check-prefixes GISEL-X86
---
name: fcmp_double_oeq
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir
index 7aa5478dcdd95..02b1fcd9acda1 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=i686-linux-gnu -run-pass=regbankselect,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
+# RUN: llc -mtriple=i686-linux-gnu -run-pass=reg-bank-select,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
---
name: fneg_f64
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir
index 3e1af9d836aec..0c98fc1c437e1 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# NOTE: This MIR test is required because the support for 64 bit memory ops is missing in X86 mode, Due to distinction between float/int types, support is expected in near future and there is this RFC in place https://discourse.llvm.org/t/rfc-globalisel-adding-fp-type-information-to-llt/83349. Once this support is introduced this test must be dropped and integrated into the LLVM IR tests.
-# RUN: llc -O2 -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=regbankselect,instruction-select -disable-gisel-legality-check -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes GISEL-X86
+# RUN: llc -O2 -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=reg-bank-select,instruction-select -disable-gisel-legality-check -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes GISEL-X86
---
name: test_double_to_int16
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir
index b6b2bd610fa3b..c4c03c4f55c92 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# NOTE: This MIR test is required because the support for 64 bit memory ops is missing in X86 mode, Due to distinction between float/int types, support is expected in near future and there is this RFC in place https://discourse.llvm.org/t/rfc-globalisel-adding-fp-type-information-to-llt/83349. Once this support is introduced this test must be dropped and integrated into the LLVM IR tests.
-# RUN: llc -O2 -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=regbankselect,instruction-select -disable-gisel-legality-check -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes GISEL-X86
+# RUN: llc -O2 -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=reg-bank-select,instruction-select -disable-gisel-legality-check -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes GISEL-X86
---
name: test_si8tofp64
diff --git a/llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir b/llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir
index f8ce9ea8be650..2fa047afdc242 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=i686-linux-gnu -run-pass=regbankselect,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
+# RUN: llc -mtriple=i686-linux-gnu -run-pass=reg-bank-select,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
---
name: test_sincos_f32
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
index 28c4eaea38841..d6b53ce6b9820 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -run-pass=regbankselect %s -o - | FileCheck %s
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -run-pass=reg-bank-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -regbankselect-greedy -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
define void @test_mul_vec256() {
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
index 4a19a040b0ce8..de3bb9d350eeb 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=regbankselect %s -o - | FileCheck %s
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=reg-bank-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
index 76680ac750625..3684f557e445d 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=i386-linux-gnu -run-pass=regbankselect %s -o - | FileCheck %s
-# RUN: llc -mtriple=i386-linux-gnu -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=i386-linux-gnu -run-pass=reg-bank-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=i386-linux-gnu -regbankselect-greedy -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
define void @test_uadde_i32() {
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
index 03d4c7dd3281d..97b12799bd65b 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=FAST
-# RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=GREEDY
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=reg-bank-select %s -o - | FileCheck %s --check-prefix=FAST
+# RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -run-pass=reg-bank-select %s -o - | FileCheck %s --check-prefix=GREEDY
--- |
define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-dbg-value-physreg-crash.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-dbg-value-physreg-crash.mir
index 085fa2c55b645..599a5354ef5c6 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-dbg-value-physreg-crash.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-dbg-value-physreg-crash.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
# This reproduces a pre-regbankselect GMIR where DBG_VALUE already carries a
# physical register. Regressions here used to crash when X86RegisterBankInfo
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-sse-intrinsics.ll b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-sse-intrinsics.ll
index 3388af605d969..03624667451d1 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-sse-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-sse-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -mtriple=i686-- -mattr=+sse -global-isel -stop-after=regbankselect | FileCheck %s
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse -global-isel -stop-after=reg-bank-select | FileCheck %s
define void @test_x86_sse_max_ps(ptr %p1, ptr %p2) {
; CHECK-LABEL: name: test_x86_sse_max_ps
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
index 449c6e365bb5c..602313cd671ec 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse,-sse2 -global-isel -stop-after=regbankselect | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse,-sse2 -global-isel -stop-after=regbankselect | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse,-sse2 -global-isel -stop-after=reg-bank-select | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse,-sse2 -global-isel -stop-after=reg-bank-select | FileCheck %s --check-prefix=X64
define x86_fp80 @f0(x86_fp80 noundef %a) {
; X86-LABEL: name: f0
diff --git a/llvm/test/CodeGen/X86/GlobalISel/sqrt.mir b/llvm/test/CodeGen/X86/GlobalISel/sqrt.mir
index 5af5120af51be..4c166c887a5be 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/sqrt.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/sqrt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=i686-linux-gnu -run-pass=regbankselect,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
+# RUN: llc -mtriple=i686-linux-gnu -run-pass=reg-bank-select,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
---
name: test_sqrt_f32
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