[llvm-branch-commits] [llvm] [AMDGPU][GISel] Rename amdgpu-regbankselect amdgpu-reg-bank-select (PR #217487)
Aiden Grossman via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Aug 20 06:11:52 PDT 2026
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/217487
>From 18f48d7f893a487a3a4b88525b2b7ce7e864b7d4 Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Wed, 19 Aug 2026 23:24:33 +0000
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change?=
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Created using spr 1.3.7
[skip ci]
---
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp | 2 +-
.../CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir | 4 ++--
.../AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir | 2 +-
.../AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/regbank-assert-align.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir | 2 +-
.../AArch64/GlobalISel/regbank-extract-vector-elt.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir | 2 +-
.../test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir | 2 +-
.../AArch64/GlobalISel/regbank-insert-vector-elt.mir | 2 +-
.../AArch64/GlobalISel/regbank-intrinsic-round.mir | 2 +-
.../AArch64/GlobalISel/regbank-intrinsic-trunc.mir | 2 +-
.../test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir | 2 +-
.../test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir | 2 +-
.../AArch64/GlobalISel/regbankselect-build-vector.mir | 2 +-
.../AArch64/GlobalISel/regbankselect-dbg-value.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/regbankselect-default.mir | 2 +-
.../CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir | 2 +-
.../AArch64/GlobalISel/regbankselect-reductions.mir | 2 +-
.../AArch64/GlobalISel/regbankselect-reg_sequence.mir | 2 +-
.../AArch64/GlobalISel/regbankselect-unmerge-vec.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir | 2 +-
.../AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir | 8 ++++----
.../AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir | 4 ++--
.../GlobalISel/regbankselect-amdgcn.s.buffer.load.mir | 4 ++--
.../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir | 4 ++--
.../test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir | 8 ++++----
.../test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir | 8 ++++----
.../AMDGPU/GlobalISel/regbankselect-illegal-copy.mir | 4 ++--
.../AMDGPU/GlobalISel/regbankselect-implicit-def.mir | 4 ++--
.../AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir | 4 ++--
.../CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir | 4 ++--
.../CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir | 6 +++---
.../AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir | 4 ++--
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir | 2 +-
.../CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 4 ++--
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir | 4 ++--
.../regbankselect-pseudo-scalar-transcendental.mir | 4 ++--
.../CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir | 4 ++--
.../AMDGPU/GlobalISel/regbankselect-reg-sequence.mir | 4 ++--
.../AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir | 2 +-
.../GlobalISel/regbankselect-whole-wave-functions.mir | 6 +++---
llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 4 ++--
.../AArch64/print-parse-verify-failedISel-property.mir | 2 +-
.../GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir | 2 +-
.../CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir | 2 +-
.../CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir | 2 +-
.../test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir | 2 +-
.../CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir | 4 ++--
.../CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir | 4 ++--
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir | 2 +-
.../CodeGen/Mips/GlobalISel/regbankselect/float_args.mir | 4 ++--
.../regbankselect/float_arithmetic_operations.mir | 4 ++--
.../Mips/GlobalISel/regbankselect/float_constants.mir | 4 ++--
.../floating_point_vec_arithmetic_operations.mir | 2 +-
.../Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir | 4 ++--
.../Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir | 4 ++--
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir | 4 ++--
.../CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir | 2 +-
.../Mips/GlobalISel/regbankselect/global_address.mir | 2 +-
.../Mips/GlobalISel/regbankselect/global_address_pic.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir | 2 +-
.../Mips/GlobalISel/regbankselect/implicit_def.mir | 2 +-
.../GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir | 2 +-
.../Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir | 2 +-
.../Mips/GlobalISel/regbankselect/load_4_unaligned.mir | 4 ++--
.../Mips/GlobalISel/regbankselect/load_store_vec.mir | 2 +-
.../GlobalISel/regbankselect/long_ambiguous_chain_s32.mir | 2 +-
.../GlobalISel/regbankselect/long_ambiguous_chain_s64.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir | 2 +-
.../CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir | 2 +-
.../CodeGen/Mips/GlobalISel/regbankselect/pointers.mir | 2 +-
.../CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir | 2 +-
.../Mips/GlobalISel/regbankselect/rem_and_div_vec.mir | 2 +-
.../test/CodeGen/Mips/GlobalISel/regbankselect/select.mir | 2 +-
.../Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir | 4 ++--
.../CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir | 2 +-
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir | 2 +-
.../Mips/GlobalISel/regbankselect/store_4_unaligned.mir | 4 ++--
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir | 2 +-
.../CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir | 2 +-
.../Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir | 2 +-
.../GlobalISel/regbankselect/truncStore_and_aExtLoad.mir | 2 +-
.../CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir | 2 +-
.../GlobalISel/regbankselect/zextLoad_and_sextLoad.mir | 2 +-
.../Mips/GlobalISel/regbankselect/zext_and_sext.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/fp-arith-f16.mir | 4 ++--
.../CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir | 4 ++--
.../RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir | 4 ++--
.../RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir | 4 ++--
.../RISCV/GlobalISel/regbankselect/fp-load-store.mir | 4 ++--
.../RISCV/GlobalISel/regbankselect/fp-select-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/fp-select-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/frame-index.mir | 4 ++--
.../RISCV/GlobalISel/regbankselect/global-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/global-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir | 2 +-
.../GlobalISel/regbankselect/is-fpclass-f16-rv32.mir | 2 +-
.../GlobalISel/regbankselect/is-fpclass-f16-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir | 2 +-
.../GlobalISel/regbankselect/jump-table-brjt-rv32.mir | 2 +-
.../GlobalISel/regbankselect/jump-table-brjt-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/minmax-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/minmax-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir | 4 ++--
.../CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir | 4 ++--
.../CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir | 4 ++--
.../RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir | 4 ++--
.../CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir | 4 ++--
.../CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir | 4 ++--
.../CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir | 4 ++--
.../GlobalISel/regbankselect/rvv/splatvector-rv32.mir | 2 +-
.../GlobalISel/regbankselect/rvv/splatvector-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir | 4 ++--
.../CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir | 4 ++--
.../RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir | 4 ++--
.../RISCV/GlobalISel/regbankselect/select-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/select-rv64.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir | 2 +-
.../CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/vec-args-ret.mir | 4 ++--
.../WebAssembly/GlobalISel/instructions/anyext.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/copy.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir | 2 +-
.../WebAssembly/GlobalISel/instructions/fcopysign.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir | 2 +-
.../WebAssembly/GlobalISel/instructions/implicit_def.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir | 2 +-
.../CodeGen/WebAssembly/GlobalISel/instructions/shl.mir | 2 +-
llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir | 2 +-
llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir | 2 +-
.../test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir | 2 +-
.../test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir | 2 +-
llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir | 2 +-
llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir | 4 ++--
llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir | 4 ++--
llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir | 4 ++--
llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir | 4 ++--
.../GlobalISel/regbankselect-dbg-value-physreg-crash.mir | 4 ++--
.../X86/GlobalISel/regbankselect-sse-intrinsics.ll | 2 +-
llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll | 4 ++--
llvm/test/CodeGen/X86/GlobalISel/sqrt.mir | 2 +-
204 files changed, 266 insertions(+), 266 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index bc6b5df99d2e7..be5d2fa7d4df7 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -48,7 +48,7 @@
#include <optional>
#include <utility>
-#define DEBUG_TYPE "regbankselect"
+#define DEBUG_TYPE "reg-bank-select"
using namespace llvm;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index d70ed52f69511..f6cab36a2eb70 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -1,5 +1,5 @@
-# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=regbankselect %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
-# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=regbankselect %s -regbankselect-greedy -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
+# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=reg-bank-select %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
+# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=reg-bank-select %s -regbankselect-greedy -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
--- |
; ModuleID = 'generic-virtual-registers-type-error.mir'
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir
index deb3945a75bcb..b2a60e7015721 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: saddlp1d
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir
index 04aefb9207e79..5c2e39c60ce1b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
# Check we don't crash given an non-generic implicit_def. These may
# come from swifterror handling in the translator.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
index 79827da26dc31..e81b552da2bcc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
# Check we don't crash because of an unhandled new regclass GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID.
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir b/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
index 3b1b15ac4c4b0..40a3a1ba074ef 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -o - %s | FileCheck %s
---
name: test_large_merge
legalized: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-align.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-align.mir
index 618a4532b2362..145fce5ce88ce 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-align.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-align.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for G_ASSERT_ALIGN.
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
index dc7c0d41ede57..a50b8c3ec64b9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for G_ASSERT_SEXT.
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
index c4b9875a0ed78..9412e03351f99 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for G_ASSERT_ZEXT.
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
index 34fe6ad790276..1d26a9af1f72f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
index 351c4f5b1bed0..bbe3b9aaed934 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for G_DUP.
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
index 03bc74f2d5569..6cf06feba9deb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect -global-isel-abort=1 %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=reg-bank-select -global-isel-abort=1 %s -o - | FileCheck %s
name: v2s32_fpr
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir
index 688ee7bb55bcc..253ad4483cf3a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+lse -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+lse -verify-machineinstrs -O0 -run-pass=reg-bank-select %s -o - | FileCheck %s
---
name: extract_s64_s128
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir
index c7acd761b2bda..46e6b51e256e1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
index 4de22f72bb3fa..52f9208d24cea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -o - | FileCheck %s
+# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir
index de30c9138c023..67d3bbe492db1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: direct
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir
index 9a692cf61c725..09c616ff054fb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: direct
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
index 8496c0d39157e..efb80df7cb212 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select %s -o - | FileCheck %s
# Check that we correctly assign register banks based off of instructions which
# only use or only define FPRs.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
index 4053859d2ef63..6841a27c056eb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=reg-bank-select %s -o - | FileCheck %s
---
name: inlineasm_memory_clobber
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
index abf19cc44835f..aec23c9e2d094 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select %s -o - | FileCheck %s
# The following should hold here:
#
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
index 609e03d39cdde..6cc550652cc82 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -mattr=+fullfp16 %s -o - | FileCheck %s
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -mattr=+fullfp16 %s -o - | FileCheck %s
# CHECK-NOT: gpr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
index ce4f8cbee4017..7edf41ae76e99 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -o - | FileCheck %s
+# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
index 5a888778a2f5a..040f238cacaae 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for intrinsics with known constraints. (E.g. all
# operands must be FPRs.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
index 60200c04a20a3..91ab7cac30f7e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
index c694105ffd02e..b26baad631950 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
index 6e87604318d6c..4788ce2bdad4c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
index e04244e2d4488..7db62e0a87f3e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
index 79ac6e46bf332..5040ad341ccdb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=regbankselect -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
index dd36fe2c09466..aa410735edfae 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir
index 9bcdb3e077183..09d4a664e44a5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: shl_cimm_32
legalized: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir
index 09b4fe7ff58b8..6284f0b56c1ff 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=reg-bank-select %s -o - | FileCheck %s
---
name: trunc_s64_s128
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
index 1378c2a2e11b5..2a0ab36dbf0f9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: build_vec_f16
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
index d98daf188d795..b1a6d708b6f9f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
index 8900f0e78f833..2460e969c8889 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select %s -o - | FileCheck %s
# Check the default mappings for various instructions.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir
index 14e4abe3bd0af..230ee869b6253 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir
index c6e3a53cb71a2..968277d45a07a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=regbankselect -global-isel-abort=1 %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=reg-bank-select -global-isel-abort=1 %s -o - | FileCheck %s
---
name: fadd_v2s32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir
index 9e3273c5abd18..73931140df2ed 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -mtriple aarch64-- -o - -run-pass regbankselect | FileCheck %s
+# RUN: llc %s -mtriple aarch64-- -o - -run-pass reg-bank-select | FileCheck %s
---
# CHECK-LABEL: foo
# Check that we produce a valid mapping for REG_SEQUENCE.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
index 4bcd7155e849a..b533e9f85078b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: unmerge
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index c067696035126..ce07431ad3578 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-- -run-pass=regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-- -run-pass=reg-bank-select,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
index a10a5c80397b8..651efcbfd754f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64 -run-pass=regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=reg-bank-select,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# GPR variants should not use INSERT_SUBREG. FPR variants (DUP<ty>lane) should.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
index f14945ae39eab..f065b4d0e615e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgpu11.00 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgpu11.00 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: else
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
index 2058b0b1cb604..f6d116bc42e86 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: else
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
index ca9b6ea03b538..9aff4a6f4b08d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=regbankselect -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
-# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=regbankselect -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
+# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=reg-bank-select -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=reg-bank-select -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
# We see the offset is a VGPR, but this is due to a constant for some
# reason ending up in a VGPR. This shouldn't really ever happen, but
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
index 0fb152ee6661b..c139129243772 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: wqm_vote_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
index 6dee24326021f..089c41fb7c10f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck --check-prefix=WAVE32 %s
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck --check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck --check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck --check-prefix=WAVE32 %s
---
name: copy_s32_vgpr_to_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
index 7bd6c1b8f9cc9..7baf9c5d535ae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
-# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
---
name: icmp_eq_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
index 512eeeb65eb0f..4a03cf68dd2ea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
@@ -1,5 +1,5 @@
-# RUN: not llc -mtriple=amdgpu6.00 -run-pass=regbankselect -regbankselect-fast -filetype=null %s 2>&1 | FileCheck %s
-# RUN: not llc -mtriple=amdgpu6.00 -run-pass=regbankselect -regbankselect-greedy -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select -regbankselect-fast -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select -regbankselect-greedy -filetype=null %s 2>&1 | FileCheck %s
# Check behavior for illegal copies.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
index 0e629d608ef5b..694d4d6110f7e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s
-# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s
+# RUN: llc -mtriple=amdgpu7.01 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s
---
name: test_implicit_def_s32_vgpr_use
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
index 384df19a942f6..b6e2e1b1c74fa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: insert_vector_elt_v4i32_s_s_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
index a788e7b5e65bc..b2c77f6e06f38 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
index 78aea1e6474a0..bde91128cd981 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX8 %s
-# RUN: llc -mtriple=amdgpu9.0a -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX9MI %s
-# RUN: llc -mtriple=amdgpu10.30 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX10 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX8 %s
+# RUN: llc -mtriple=amdgpu9.0a -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX9MI %s
+# RUN: llc -mtriple=amdgpu10.30 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX10 %s
---
name: mad_u64_u32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
index 27d5ccbe29ece..3d9dc32a6873d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX10
-# RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX12
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX10
+# RUN: llc -mtriple=amdgpu12.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX12
# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX10
# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX12
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
index d7fdf3be05c80..1edf0ec2356d5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS
+# RUN: llc -mtriple=amdgpu10.10 -run-pass=reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS
# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
index c477c8c41a703..f983ba491bd9f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
---
name: phi_s1_scc_scc_sbranch
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
index 4b7b7c29c2d02..4ef2ade9d2ad3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
-# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass=reg-bank-select -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -mtriple=amdgpu9.08 -run-pass=reg-bank-select -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
---
name: phi_s32_ss_sbranch
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
index 8ba950e16fb62..36242dbcb1529 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: v_s_exp_f32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
index 8541e284c8ddb..c167fa1de3ac7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
index 9de1a0820935d..4eb7ba24af649 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: reg_sequence_ss_vreg
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
index 2a4c79d1f9954..bb7279f9cc559 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -verify-machineinstrs -run-pass=regbankselect -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -verify-machineinstrs -run-pass=reg-bank-select -o - %s | FileCheck %s
# Make sure that an arbitrary AGPR is treated as a divergent value
# that needs to be copied to VGPR, and then waterfalled
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
index 74e62e4e5b8a9..aae10cb7aa55a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu12.00--amdpal -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgpu12.00--amdpal -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
-# RUN: llc -mtriple=amdgpu12.00--amdpal -mattr=+wavefrontsize64 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00--amdpal -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00--amdpal -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00--amdpal -mattr=+wavefrontsize64 -run-pass=reg-bank-select %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: basic_test
legalized: true
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index 7b530cef67ebc..951d7eb1cfa68 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -1,5 +1,5 @@
-# RUN: llc -debugify-and-strip-all-safe=0 -mtriple arm-- -run-pass=regbankselect %s -o - | FileCheck %s
-# RUN: llc -debugify-and-strip-all-safe=0 -mtriple thumbv7-- -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe=0 -mtriple arm-- -run-pass=reg-bank-select %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe=0 -mtriple thumbv7-- -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
define void @test_add_s32() { ret void }
define void @test_sub_s32() { ret void }
diff --git a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
index a4a5533ff2c2b..c53a0ce405785 100644
--- a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
@@ -2,7 +2,7 @@
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
#
# RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \
-# RUN: -start-after=regbankselect -stop-before=finalize-isel \
+# RUN: -start-after=reg-bank-select -stop-before=finalize-isel \
# RUN: -simplify-mir -verify-machineinstrs %s -o - 2>&1 \
# RUN: | FileCheck %s --check-prefix=FALLBACK
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
index 011a05e133759..c2c6c84c0c821 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @skipCopiesOutgoing(ptr %ptr_a, ptr %ptr_b, ptr %ptr_c) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
index a1c41fad4250f..0160440a47181 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @add_i32(i32 %x, i32 %y) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
index a963d2dc500e5..ad01a4d916f0c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @add_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
index e5cc1d9eb7dcb..78145c8eff966 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
index 28416f116d0b7..6c9a2410a0e4a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @Unconditional_branch(i32 %a, i32 %b) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
index 918cf4ee236b1..d42da94c798ac 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @indirectbr(ptr %addr) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
index c50e81eae0c93..902537a4c4534 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
+# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
--- |
define void @bswap_i32() { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
index 93896f6ea01ba..6a9853c6bc6fb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
---
name: ctlz_i32
alignment: 4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir
index f7fe5a0a7c0a3..ccaa6a6b5b034 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fabs_f32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
index 2b0476f3efcb3..3bdf9b86e4260 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @fabs_v4f32(ptr %a, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir
index 6673980b4b101..96192b7e55a78 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @oeq_s() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
index 9c7ec54d97435..dbd9b315c201b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @atomic_load_i32(ptr %ptr) { ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
index 7886a9dfa2233..5ad6d4863fbf7 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir
index 49bd7702af848..cee5c4cef7d45 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir
index 1eca0d3b96ac4..94b7329dcdc2a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
index b696be65dee6d..e1ffcb87e777f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @fadd_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir
index 52c751e8c477d..d14499510f998 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fpext() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir
index 74c1a7dcc7fe3..e5c6dfd3b26bb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @f32toi32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir
index a9ca2f2515ddc..b9aab7e884900 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @sqrt_f32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
index a918bae094b17..f152949e22d85 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sqrt_v4f32(ptr %a, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
index 0e20bc7cb95db..e5a311e86556c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
@.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00"
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
index d53b1575ca7f8..8359af16044bb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -relocation-model=pic -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -relocation-model=pic -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
declare i32 @f(i32, i32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
index 611ba0718c199..a40d89eaf72bb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @ne_i32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir
index dc88bb817f76c..639a723b3d416 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
declare void @f_i32(i32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
index b7eda46de75db..a289c2e8f4d76 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @inttoptr() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
index 56c629a292ce8..b1e63839aba2f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @mod4_0_to_11(i32 %a) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
index 3f0b20cd422c3..25a4d2a107acc 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @load_i32(ptr %ptr) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
index 142d7ea31e5cb..5da84fc790d72 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
index 64117a2d82635..76dba09573596 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @load_store_v16i8(ptr %a, ptr %b) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
index 319bb2bf446ff..a2cef932b0f08 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
index 319bb2bf446ff..a2cef932b0f08 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
index b0fc873c6d063..6decdd9cb32e3 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
index 4d6bce2063d49..2292396bd4844 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @mul_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
index dc758986e9fb4..5b7ba0922c72e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
index 044ab1320816e..1080d4364399a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @ptr_arg_in_regs(ptr %p) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
index b9b725e8e138c..238a2843627ae 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @sdiv_i32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
index cef6101e2038d..68e1cdb90b3e9 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sdiv_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
index 20f18fe704d56..1bdebc897ae86 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @select_i32(i32, i32) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
index fa893a2332e02..047ab470cff94 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @i32tof32() {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
index be2284f3df752..7e94793bc4d3b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
declare i32 @f(i32, i32, i32, i32, i32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
index 874056e8e88a3..a688060f7ed66 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @store_i32(ptr %ptr) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
index 3f705ebea309f..9e0b3608ba3d6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
index dcee70ce4b01e..d3350cffc385f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @sub_i32(i32 %x, i32 %y) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
index b2114a9fb3a1c..bc8153b342fc0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sub_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
index 0d81e0129def9..a73026f9af44b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @outgoing_gpr(ptr %i32_ptr) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
index 5ed6dc4fc55fb..0a5d01e806eb5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @load_store_i8(ptr %px, ptr %py) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
index 861f94bb0829c..60ec003b46d33 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
@.str = private unnamed_addr constant [11 x i8] c"string %s\0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
index 1ffed379a4ffc..0078fca55d88c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
index 187b3e68b1b7a..6074a9d6fda9b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @zext() {entry: ret void}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
index 1b6684dc42397..8384c1a812b84 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
index cef929f1e05be..37caf893f487d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
index 1296d5f3cbfa1..ebbf138764e04 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
index 98c0707128a41..7a54917ae50af 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
index 9cc0b579ed48e..b4b2bac3e2087 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir
index 2a3f8bdc4d3e0..9963ffdf48502 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir
index 518ef4488aa44..3e4433527c969 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir
index 7020a0ba8709d..50caa81a5b0e5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir
index 48f7c4fda396a..ea253cd75758c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
index 1ef5c48f0b5b6..d3fd2b108f812 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
index 2801faf76820b..8d53f205b4c2c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir
index 7758a640ac860..95e3dd1b51e4f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d,zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d,zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+d,zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d,zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir
index 1ed7ceea2f650..aa7fdc4579601 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
index f74362298a6cb..a0eb1e0626f25 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s --check-prefixes=CHECK
-# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s --check-prefixes=CHECK
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
index 7dee1370f283d..a1221a2f2374e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
index e7f9500373721..d4fdfdb8afd35 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
index 346dd28eb3778..c9d9704c2b5ad 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
index d63803f8f5bdf..10cb8c7802574 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir
index 10fb4f6ba4596..7463ab51a952d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
index d5c2875d316cb..49f898ff9dc34 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
index f701ef6169625..aa2b12764232f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select %s -o - \
# RUN: | FileCheck %s
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select %s -o - \
# RUN: | FileCheck %s
--- |
define ptr @frame_index() {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
index b43371ad40d72..f04f4dc82d400 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
index c4196b06e3319..245d8f9cec361 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
index f084af59fdf4d..e356e66b9c93b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=reg-bank-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32F %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir
index caece8b68ce0b..8c7eaa457ee26 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64D %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir
index 9224579d6bd78..434fa91112740 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=reg-bank-select -verify-machineinstrs %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir
index 9bf796d1f55e9..3da5e647ed425 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=reg-bank-select -verify-machineinstrs %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir
index ad0b73e6bef92..7703cdf31f757 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select -verify-machineinstrs %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir
index 9e602b3ed94c3..2e966a492077f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select -verify-machineinstrs %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
index 02e5a9a982ed0..86ecb3abb6811 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
index 5b48a7e947ae6..d7a0ec6b187e4 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir
index e4e9af7a0f6d8..910d9c8812f9c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
index 6cb38cf38a6a5..26b75f7c6887f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
index b7fd2a3ce01aa..867126456bccf 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
index 56cac99a2b411..c39379a343c36 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
index 45e96b152f875..4dfcdb1db8344 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
index 77fb05edd7ec3..ecc7c623a379d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir
index 4785b86a8a786..069362c1a8a46 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=reg-bank-select %s -o - \
# RUN: | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
index 715ba22dc99bc..d1ed3e8b4e459 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
index 2fb680fd15d8f..97204599b6eb2 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
index 8feeebf37107e..402ea3fdbac23 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
index a1537ac0173e4..f0f0063f322e9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
index 089dd7ada0a9b..95da8318832df 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: ptrmask_p0_s32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
index e0e765e368d1d..25034f5f915e9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: ptrmask_p0_s64
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
index ab3d777856d6e..ccd88be116233 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
index 4d1b11b6921dd..2ebb4aeb2bb92 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
index 8447b3602165a..0783ecdfa6073 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir
index 017da0d536af7..687358c8ca99f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir
index b58e87c128218..7e7c67ba6702e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir
index 7e2badbc5cda9..4781d4c3fd041 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
index efd7f13e376a5..77a9b100edeba 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir
index 38d3e83c6dbc4..085a0805a631b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir
index efd5237253449..abd743ca3663e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir
index 3a6a2389d1db0..7dc7dcd9b2e82 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
index c18423cbe3758..4c6c5a46be3ee 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir
index abab3ccbbdfe1..4eaf1d7e5600e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir
index d4d7012567401..9c40d6a86f8ca 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
index 1d8e676b7c94b..1f846d01d195d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
index 47117dc0009b9..0fb4ff0c5420b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
index 5070c583c5f6b..b8a6f61450c21 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
index 5252b25b6f3b6..a8588a5c936a8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
index 47d396f4eb381..ed3b1370996f3 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
index 544c3bb06a106..ed9b5f8211a1e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
index c3475dd64789a..4d85f5ade8b02 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
index 9ed3b678e9711..bfa1b90cb5aec 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefixes=RV32 %s
-# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=reg-bank-select \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefixes=RV64 %s
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir
index 4ce64cc824a82..ef664dcce989f 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: aext_i8_i32
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
index c81eba50ead57..5ee6c10a1f1ba 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: ashr_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/copy.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/copy.mir
index a692af7437071..d7ccd022b5d70 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/copy.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/copy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: copy_i32
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
index 4a5238cc535d5..d6e7b0f3203e3 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: ctlz_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
index 97c9ffb90a7cb..8e2d13a9d8950 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: ctpop_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
index cb4e099c66d60..268b9c0a48584 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: cttz_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fcopysign.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fcopysign.mir
index 9f7b0df4d9bba..1c91972074549 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fcopysign.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fcopysign.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: fcopysign_f32_from_f64
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir
index 82e959b0fcaf6..7686ea18881b6 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: fneg_f32
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
index d7e4daef5dc61..265694ce8e681 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: fshl_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
index c95466a33e311..d544220f8bee5 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: fshr_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
index 3498ff229ca81..7c9b8f91b1ecf 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: implicit_def_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
index 53805d9fae2cc..19d8cc82c8a81 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: lshr_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
index f977a269c8a34..ca20808769135 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
index 12fd666d7128a..1c3014b689125 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
index 296be9adeb440..ddbcdac0b6af6 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,reg-bank-select,instruction-select %s -o - | FileCheck %s
---
name: shl_i32_i8
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
index 8273677592607..fc9792824a360 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# NOTE: This MIR test is required because the support for 64 bit memory ops is missing in i686 mode, Due to distinction between float/int types, support is expected in near future and there is this RFC in place https://discourse.llvm.org/t/rfc-globalisel-adding-fp-type-information-to-llt/83349. Once this support is introduced this test must be dropped and integrated into the LLVM IR tests.
-# RUN: llc -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=regbankselect,instruction-select -disable-gisel-legality-check -global-isel %s -o - | FileCheck %s --check-prefixes GISEL-X86
+# RUN: llc -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=reg-bank-select,instruction-select -disable-gisel-legality-check -global-isel %s -o - | FileCheck %s --check-prefixes GISEL-X86
---
name: fcmp_double_oeq
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir
index 7aa5478dcdd95..02b1fcd9acda1 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=i686-linux-gnu -run-pass=regbankselect,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
+# RUN: llc -mtriple=i686-linux-gnu -run-pass=reg-bank-select,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
---
name: fneg_f64
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir
index 3e1af9d836aec..0c98fc1c437e1 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# NOTE: This MIR test is required because the support for 64 bit memory ops is missing in X86 mode, Due to distinction between float/int types, support is expected in near future and there is this RFC in place https://discourse.llvm.org/t/rfc-globalisel-adding-fp-type-information-to-llt/83349. Once this support is introduced this test must be dropped and integrated into the LLVM IR tests.
-# RUN: llc -O2 -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=regbankselect,instruction-select -disable-gisel-legality-check -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes GISEL-X86
+# RUN: llc -O2 -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=reg-bank-select,instruction-select -disable-gisel-legality-check -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes GISEL-X86
---
name: test_double_to_int16
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir
index b6b2bd610fa3b..c4c03c4f55c92 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# NOTE: This MIR test is required because the support for 64 bit memory ops is missing in X86 mode, Due to distinction between float/int types, support is expected in near future and there is this RFC in place https://discourse.llvm.org/t/rfc-globalisel-adding-fp-type-information-to-llt/83349. Once this support is introduced this test must be dropped and integrated into the LLVM IR tests.
-# RUN: llc -O2 -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=regbankselect,instruction-select -disable-gisel-legality-check -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes GISEL-X86
+# RUN: llc -O2 -mtriple=i686-linux-gnu -mattr=+x87,-sse,-sse2 -run-pass=reg-bank-select,instruction-select -disable-gisel-legality-check -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes GISEL-X86
---
name: test_si8tofp64
diff --git a/llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir b/llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir
index f8ce9ea8be650..2fa047afdc242 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=i686-linux-gnu -run-pass=regbankselect,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
+# RUN: llc -mtriple=i686-linux-gnu -run-pass=reg-bank-select,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
---
name: test_sincos_f32
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
index 28c4eaea38841..d6b53ce6b9820 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -run-pass=regbankselect %s -o - | FileCheck %s
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -run-pass=reg-bank-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -regbankselect-greedy -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
define void @test_mul_vec256() {
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
index 4a19a040b0ce8..de3bb9d350eeb 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=regbankselect %s -o - | FileCheck %s
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=reg-bank-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
index 76680ac750625..3684f557e445d 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=i386-linux-gnu -run-pass=regbankselect %s -o - | FileCheck %s
-# RUN: llc -mtriple=i386-linux-gnu -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=i386-linux-gnu -run-pass=reg-bank-select %s -o - | FileCheck %s
+# RUN: llc -mtriple=i386-linux-gnu -regbankselect-greedy -run-pass=reg-bank-select %s -o - | FileCheck %s
--- |
define void @test_uadde_i32() {
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
index 03d4c7dd3281d..97b12799bd65b 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=FAST
-# RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=GREEDY
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=reg-bank-select %s -o - | FileCheck %s --check-prefix=FAST
+# RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -run-pass=reg-bank-select %s -o - | FileCheck %s --check-prefix=GREEDY
--- |
define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-dbg-value-physreg-crash.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-dbg-value-physreg-crash.mir
index 085fa2c55b645..599a5354ef5c6 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-dbg-value-physreg-crash.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-dbg-value-physreg-crash.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -run-pass=reg-bank-select -verify-machineinstrs %s -o - | FileCheck %s
# This reproduces a pre-regbankselect GMIR where DBG_VALUE already carries a
# physical register. Regressions here used to crash when X86RegisterBankInfo
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-sse-intrinsics.ll b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-sse-intrinsics.ll
index 3388af605d969..03624667451d1 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-sse-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-sse-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -mtriple=i686-- -mattr=+sse -global-isel -stop-after=regbankselect | FileCheck %s
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse -global-isel -stop-after=reg-bank-select | FileCheck %s
define void @test_x86_sse_max_ps(ptr %p1, ptr %p2) {
; CHECK-LABEL: name: test_x86_sse_max_ps
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
index 449c6e365bb5c..602313cd671ec 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse,-sse2 -global-isel -stop-after=regbankselect | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse,-sse2 -global-isel -stop-after=regbankselect | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse,-sse2 -global-isel -stop-after=reg-bank-select | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse,-sse2 -global-isel -stop-after=reg-bank-select | FileCheck %s --check-prefix=X64
define x86_fp80 @f0(x86_fp80 noundef %a) {
; X86-LABEL: name: f0
diff --git a/llvm/test/CodeGen/X86/GlobalISel/sqrt.mir b/llvm/test/CodeGen/X86/GlobalISel/sqrt.mir
index 5af5120af51be..4c166c887a5be 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/sqrt.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/sqrt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=i686-linux-gnu -run-pass=regbankselect,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
+# RUN: llc -mtriple=i686-linux-gnu -run-pass=reg-bank-select,instruction-select %s -o - | FileCheck %s --check-prefixes GISEL-I686
---
name: test_sqrt_f32
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