[llvm-branch-commits] [llvm] [AMDGPU][GIsel][NPM] Port "AMDGPURegBankLegalize" to NPM (PR #217322)

Wed Aug 19 05:20:54 PDT 2026

https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/217322

None

>From cda4849c019aa4bbad2e4767a3a56655a3e8eb82 Mon Sep 17 00:00:00 2001
From: vikhegde <vikram.hegde at amd.com>
Date: Wed, 19 Aug 2026 17:06:49 +0530
Subject: [PATCH] [AMDGPU][GIsel][NPM] Port "AMDGPURegBankLegalize" to NPM

---
 llvm/lib/Target/AMDGPU/AMDGPU.h               | 24 ++++++-
 llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def |  2 +-
 .../Target/AMDGPU/AMDGPURegBankLegalize.cpp   | 68 +++++++++++++------
 .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp |  4 +-
 .../AMDGPU/GlobalISel/regbankselect-abs.mir   |  1 +
 .../AMDGPU/GlobalISel/regbankselect-add.mir   |  1 +
 .../GlobalISel/regbankselect-add.s16.mir      |  1 +
 .../GlobalISel/regbankselect-add.s32.mir      |  1 +
 .../GlobalISel/regbankselect-add.v2s16.mir    |  1 +
 .../regbankselect-amdgcn-exp-compr.mir        |  1 +
 .../GlobalISel/regbankselect-amdgcn-exp.mir   |  1 +
 .../regbankselect-amdgcn-s-buffer-load.mir    |  1 +
 .../regbankselect-amdgcn.ballot.i64.mir       |  1 +
 .../GlobalISel/regbankselect-amdgcn.class.mir |  1 +
 .../regbankselect-amdgcn.cvt.pkrtz.mir        |  1 +
 .../regbankselect-amdgcn.div.fmas.mir         |  1 +
 .../regbankselect-amdgcn.div.scale.mir        |  1 +
 .../regbankselect-amdgcn.ds.append.mir        |  1 +
 .../regbankselect-amdgcn.ds.bpermute.mir      |  1 +
 .../regbankselect-amdgcn.ds.consume.mir       |  1 +
 .../regbankselect-amdgcn.ds.gws.init.mir      |  1 +
 .../regbankselect-amdgcn.ds.gws.sema.v.mir    |  1 +
 .../regbankselect-amdgcn.ds.ordered.add.mir   |  1 +
 .../regbankselect-amdgcn.ds.ordered.swap.mir  |  1 +
 .../regbankselect-amdgcn.ds.permute.mir       |  1 +
 .../regbankselect-amdgcn.ds.swizzle.mir       |  1 +
 .../GlobalISel/regbankselect-amdgcn.fcmp.mir  |  1 +
 .../regbankselect-amdgcn.fmul.legacy.mir      |  1 +
 .../regbankselect-amdgcn.groupstaticsize.mir  |  1 +
 .../GlobalISel/regbankselect-amdgcn.icmp.mir  |  1 +
 .../regbankselect-amdgcn.interp.mov.mir       |  1 +
 .../regbankselect-amdgcn.interp.p1.f16.mir    |  1 +
 .../regbankselect-amdgcn.interp.p1.mir        |  1 +
 .../regbankselect-amdgcn.interp.p2.f16.mir    |  1 +
 .../regbankselect-amdgcn.interp.p2.mir        |  1 +
 .../GlobalISel/regbankselect-amdgcn.kill.mir  |  1 +
 .../regbankselect-amdgcn.lds.direct.load.mir  |  1 +
 .../regbankselect-amdgcn.lds.param.load.mir   |  1 +
 .../regbankselect-amdgcn.live.mask.mir        |  1 +
 .../regbankselect-amdgcn.mfma.gfx90a.mir      |  1 +
 .../regbankselect-amdgcn.mfma.gfx942.mir      |  1 +
 .../GlobalISel/regbankselect-amdgcn.mfma.mir  |  1 +
 .../regbankselect-amdgcn.ps.live.mir          |  1 +
 .../regbankselect-amdgcn.readfirstlane.mir    |  1 +
 .../regbankselect-amdgcn.readlane.mir         |  1 +
 ...elect-amdgcn.s.get.waveid.in.workgroup.mir |  1 +
 .../regbankselect-amdgcn.s.getpc.mir          |  1 +
 .../regbankselect-amdgcn.s.getreg.mir         |  1 +
 .../regbankselect-amdgcn.s.memrealtime.mir    |  1 +
 .../regbankselect-amdgcn.s.memtime.mir        |  1 +
 .../regbankselect-amdgcn.s.sendmsg.mir        |  1 +
 .../regbankselect-amdgcn.s.sendmsghalt.mir    |  1 +
 .../regbankselect-amdgcn.update.dpp.mir       |  1 +
 .../regbankselect-amdgcn.wqm.demote.mir       |  1 +
 .../GlobalISel/regbankselect-amdgcn.wqm.mir   |  1 +
 .../regbankselect-amdgcn.writelane.mir        |  1 +
 .../GlobalISel/regbankselect-amdgcn.wwm.mir   |  1 +
 .../regbankselect-amdgpu-ffbh-u32.mir         |  1 +
 .../regbankselect-amdgpu-ffbl-b32.mir         |  1 +
 .../regbankselect-amdgpu-wave-address.mir     |  1 +
 .../GlobalISel/regbankselect-and-s1.mir       |  1 +
 .../AMDGPU/GlobalISel/regbankselect-and.mir   |  1 +
 .../GlobalISel/regbankselect-anyext.mir       |  1 +
 .../AMDGPU/GlobalISel/regbankselect-ashr.mir  |  1 +
 .../GlobalISel/regbankselect-assert-align.mir |  1 +
 .../GlobalISel/regbankselect-assert-sext.mir  |  1 +
 .../GlobalISel/regbankselect-assert-zext.mir  |  1 +
 .../regbankselect-atomic-cmpxchg.mir          |  1 +
 .../regbankselect-atomicrmw-add-sub.mir       |  1 +
 .../regbankselect-atomicrmw-add.mir           |  1 +
 .../regbankselect-atomicrmw-and.mir           |  1 +
 .../regbankselect-atomicrmw-fadd.mir          |  1 +
 .../regbankselect-atomicrmw-fadd.v2f16.mir    |  1 +
 .../regbankselect-atomicrmw-max.mir           |  1 +
 .../regbankselect-atomicrmw-min.mir           |  1 +
 ...regbankselect-atomicrmw-minmax-uminmax.mir |  1 +
 .../GlobalISel/regbankselect-atomicrmw-or.mir |  1 +
 .../regbankselect-atomicrmw-sub.mir           |  1 +
 ...regbankselect-atomicrmw-uinc-udec-wrap.mir |  1 +
 .../regbankselect-atomicrmw-umax.mir          |  1 +
 .../regbankselect-atomicrmw-umin.mir          |  1 +
 .../regbankselect-atomicrmw-xchg.mir          |  1 +
 .../regbankselect-atomicrmw-xor.mir           |  1 +
 .../GlobalISel/regbankselect-bitcast.mir      |  1 +
 .../GlobalISel/regbankselect-bitreverse.mir   |  1 +
 .../GlobalISel/regbankselect-block-addr.mir   |  1 +
 .../GlobalISel/regbankselect-brcond.mir       |  1 +
 .../AMDGPU/GlobalISel/regbankselect-bswap.mir |  1 +
 .../GlobalISel/regbankselect-build-vector.mir |  1 +
 .../regbankselect-concat-vector.mir           |  1 +
 .../GlobalISel/regbankselect-constant.mir     |  1 +
 .../regbankselect-ctlz-zero-poison.mir        |  1 +
 .../AMDGPU/GlobalISel/regbankselect-ctpop.mir |  1 +
 .../regbankselect-cttz-zero-poison.mir        |  1 +
 .../GlobalISel/regbankselect-default.mir      |  1 +
 .../regbankselect-dyn-stackalloc.mir          |  2 +
 .../regbankselect-extract-vector-elt.mir      |  2 +
 .../AMDGPU/GlobalISel/regbankselect-fabs.mir  |  1 +
 .../AMDGPU/GlobalISel/regbankselect-fadd.mir  |  1 +
 .../regbankselect-fcanonicalize.mir           |  1 +
 .../AMDGPU/GlobalISel/regbankselect-fceil.mir |  1 +
 .../AMDGPU/GlobalISel/regbankselect-fcmp.mir  |  2 +
 .../AMDGPU/GlobalISel/regbankselect-fexp2.mir |  3 +
 .../GlobalISel/regbankselect-ffloor.mir       |  1 +
 .../AMDGPU/GlobalISel/regbankselect-flog2.mir |  1 +
 .../AMDGPU/GlobalISel/regbankselect-fma.mir   |  1 +
 .../AMDGPU/GlobalISel/regbankselect-fmul.mir  |  1 +
 .../AMDGPU/GlobalISel/regbankselect-fneg.mir  |  1 +
 .../AMDGPU/GlobalISel/regbankselect-fpext.mir |  2 +
 .../GlobalISel/regbankselect-fptosi-sat.mir   |  1 +
 .../GlobalISel/regbankselect-fptosi.mir       |  1 +
 .../GlobalISel/regbankselect-fptoui-sat.mir   |  1 +
 .../GlobalISel/regbankselect-fptoui.mir       |  1 +
 .../GlobalISel/regbankselect-fptrunc.mir      |  2 +
 .../GlobalISel/regbankselect-frame-index.mir  |  1 +
 .../GlobalISel/regbankselect-freeze.mir       |  3 +
 .../AMDGPU/GlobalISel/regbankselect-fshr.mir  |  1 +
 .../AMDGPU/GlobalISel/regbankselect-fsqrt.mir |  2 +
 .../AMDGPU/GlobalISel/regbankselect-fsub.mir  |  2 +
 .../GlobalISel/regbankselect-icmp.s16.mir     |  1 +
 .../regbankselect-intrinsic-roundeven.mir     |  1 +
 .../regbankselect-intrinsic-trunc.mir         |  1 +
 .../GlobalISel/regbankselect-inttoptr.mir     |  1 +
 .../AMDGPU/GlobalISel/regbankselect-load.mir  |  3 +
 .../AMDGPU/GlobalISel/regbankselect-lshr.mir  |  1 +
 .../GlobalISel/regbankselect-merge-values.mir |  1 +
 .../regbankselect-mui-salu-float.mir          |  2 +
 .../AMDGPU/GlobalISel/regbankselect-mui.mir   |  1 +
 .../AMDGPU/GlobalISel/regbankselect-mul.mir   |  1 +
 .../AMDGPU/GlobalISel/regbankselect-or.mir    |  1 +
 .../GlobalISel/regbankselect-ptr-add.mir      |  1 +
 .../GlobalISel/regbankselect-ptrmask.mir      |  1 +
 .../GlobalISel/regbankselect-ptrtoint.mir     |  1 +
 .../AMDGPU/GlobalISel/regbankselect-sadde.mir |  1 +
 .../GlobalISel/regbankselect-salu-float.mir   |  1 +
 .../AMDGPU/GlobalISel/regbankselect-sbfx.mir  |  1 +
 .../GlobalISel/regbankselect-select.mir       |  1 +
 .../GlobalISel/regbankselect-sext-inreg.mir   |  1 +
 .../AMDGPU/GlobalISel/regbankselect-sext.mir  |  1 +
 .../GlobalISel/regbankselect-sextload.mir     |  1 +
 .../AMDGPU/GlobalISel/regbankselect-shl.mir   |  1 +
 .../GlobalISel/regbankselect-sitofp.mir       |  1 +
 .../AMDGPU/GlobalISel/regbankselect-smax.mir  |  1 +
 .../AMDGPU/GlobalISel/regbankselect-smin.mir  |  1 +
 .../AMDGPU/GlobalISel/regbankselect-smulh.mir |  2 +
 ...gbankselect-split-scalar-load-metadata.mir |  3 +
 .../AMDGPU/GlobalISel/regbankselect-ssube.mir |  1 +
 .../AMDGPU/GlobalISel/regbankselect-sub.mir   |  1 +
 .../AMDGPU/GlobalISel/regbankselect-trunc.mir |  2 +
 .../AMDGPU/GlobalISel/regbankselect-uadde.mir |  1 +
 .../AMDGPU/GlobalISel/regbankselect-uaddo.mir |  1 +
 .../AMDGPU/GlobalISel/regbankselect-ubfx.mir  |  1 +
 .../GlobalISel/regbankselect-uitofp.mir       |  1 +
 .../AMDGPU/GlobalISel/regbankselect-umax.mir  |  1 +
 .../AMDGPU/GlobalISel/regbankselect-umin.mir  |  1 +
 .../AMDGPU/GlobalISel/regbankselect-umulh.mir |  2 +
 .../regbankselect-uniform-load-noclobber.mir  |  2 +
 .../regbankselect-unmerge-values.mir          |  1 +
 .../AMDGPU/GlobalISel/regbankselect-usube.mir |  1 +
 .../AMDGPU/GlobalISel/regbankselect-usubo.mir |  1 +
 .../regbankselect-waterfall-call.mir          |  1 +
 .../regbankselect-widen-scalar-loads.mir      |  3 +
 .../AMDGPU/GlobalISel/regbankselect-xor.mir   |  1 +
 .../AMDGPU/GlobalISel/regbankselect-zext.mir  |  1 +
 .../GlobalISel/regbankselect-zextload.mir     |  1 +
 .../AMDGPU/GlobalISel/regbankselect.mir       |  1 +
 166 files changed, 256 insertions(+), 26 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 10e35050c2464..ec510fa2ba67e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -62,7 +62,25 @@ class AMDGPURegBankSelectPass
     return MachineFunctionProperties().setRegBankSelected();
   }
 };
-FunctionPass *createAMDGPURegBankLegalizePass();
+FunctionPass *createAMDGPURegBankLegalizeLegacyPass();
+
+class AMDGPURegBankLegalizePass
+    : public RequiredPassInfoMixin<AMDGPURegBankLegalizePass> {
+public:
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+
+  MachineFunctionProperties getRequiredProperties() const {
+    return MachineFunctionProperties()
+        .setIsSSA()
+        .setLegalized()
+        .setRegBankSelected();
+  }
+
+  MachineFunctionProperties getClearedProperties() const {
+    return MachineFunctionProperties().setNoPHIs();
+  }
+};
 
 // SI Passes
 FunctionPass *createGCNDPPCombinePass();
@@ -246,8 +264,8 @@ extern char &AMDGPUGlobalISelDivergenceLoweringLegacyID;
 void initializeAMDGPURegBankSelectLegacyPass(PassRegistry &);
 extern char &AMDGPURegBankSelectLegacyID;
 
-void initializeAMDGPURegBankLegalizePass(PassRegistry &);
-extern char &AMDGPURegBankLegalizeID;
+void initializeAMDGPURegBankLegalizeLegacyPass(PassRegistry &);
+extern char &AMDGPURegBankLegalizeLegacyID;
 
 void initializeAMDGPUMarkLastScratchLoadLegacyPass(PassRegistry &);
 extern char &AMDGPUMarkLastScratchLoadID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index bbbb71006402c..32cb229d0b975 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -131,6 +131,7 @@ MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass()
 MACHINE_FUNCTION_PASS("amdgpu-prelegalizer-combiner",
                       AMDGPUPreLegalizerCombinerPass())
 MACHINE_FUNCTION_PASS("amdgpu-regbankselect", AMDGPURegBankSelectPass())
+MACHINE_FUNCTION_PASS("amdgpu-regbanklegalize", AMDGPURegBankLegalizePass())
 MACHINE_FUNCTION_PASS("amdgpu-preload-kern-arg-prolog", AMDGPUPreloadKernArgPrologPass())
 MACHINE_FUNCTION_PASS("amdgpu-prepare-agpr-alloc", AMDGPUPrepareAGPRAllocPass())
 MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass())
@@ -167,7 +168,6 @@ MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass())
 // Global ISel passes
 DUMMY_MACHINE_FUNCTION_PASS("amdgpu-postlegalizer-combiner",
                             AMDGPUPostLegalizerCombinerPass())
-DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbanklegalize", AMDGPURegBankLegalizePass())
 DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbank-combiner", AMDGPURegBankCombinerPass())
 
 #undef DUMMY_MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index d28d5c8c556a7..baa89fcc7ad26 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -27,7 +27,9 @@
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
 #include "llvm/CodeGen/MachineUniformityAnalysis.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/InitializePasses.h"
@@ -47,12 +49,12 @@ m_GAMDGPUReadAnyLane(const SrcTy &Src) {
   return UnaryOp_match<SrcTy, AMDGPU::G_AMDGPU_READANYLANE>(Src);
 }
 
-class AMDGPURegBankLegalize : public MachineFunctionPass {
+class AMDGPURegBankLegalizeLegacy : public MachineFunctionPass {
 public:
   static char ID;
 
 public:
-  AMDGPURegBankLegalize() : MachineFunctionPass(ID) {}
+  AMDGPURegBankLegalizeLegacy() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
@@ -77,21 +79,21 @@ class AMDGPURegBankLegalize : public MachineFunctionPass {
 
 } // End anonymous namespace.
 
-INITIALIZE_PASS_BEGIN(AMDGPURegBankLegalize, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(AMDGPURegBankLegalizeLegacy, DEBUG_TYPE,
                       "AMDGPU Register Bank Legalize", false, false)
 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
 INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(MachineUniformityAnalysisPass)
 INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
-INITIALIZE_PASS_END(AMDGPURegBankLegalize, DEBUG_TYPE,
+INITIALIZE_PASS_END(AMDGPURegBankLegalizeLegacy, DEBUG_TYPE,
                     "AMDGPU Register Bank Legalize", false, false)
 
-char AMDGPURegBankLegalize::ID = 0;
+char AMDGPURegBankLegalizeLegacy::ID = 0;
 
-char &llvm::AMDGPURegBankLegalizeID = AMDGPURegBankLegalize::ID;
+char &llvm::AMDGPURegBankLegalizeLegacyID = AMDGPURegBankLegalizeLegacy::ID;
 
-FunctionPass *llvm::createAMDGPURegBankLegalizePass() {
-  return new AMDGPURegBankLegalize();
+FunctionPass *llvm::createAMDGPURegBankLegalizeLegacyPass() {
+  return new AMDGPURegBankLegalizeLegacy();
 }
 
 const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
@@ -416,15 +418,10 @@ void AMDGPURegBankLegalizeCombiner::tryCombineS1AnyExt(MachineInstr &MI) {
   return {};
 }
 
-bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasFailedISel())
-    return false;
-
+static bool runRegBankLegalize(MachineFunction &MF, GISelCSEInfo &CSEInfo,
+                               const MachineUniformityInfo &MUI,
+                               GISelValueTracking &VT) {
   // Setup the instruction builder with CSE.
-  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
-  GISelCSEAnalysisWrapper &Wrapper =
-      getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
-  GISelCSEInfo &CSEInfo = Wrapper.get(TPC.getCSEConfig());
   GISelObserverWrapper Observer;
   Observer.addObserver(&CSEInfo);
 
@@ -438,10 +435,6 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const RegisterBankInfo &RBI = *ST.getRegBankInfo();
-  const MachineUniformityInfo &MUI =
-      getAnalysis<MachineUniformityAnalysisPass>().getUniformityInfo();
-  GISelValueTracking &VT =
-      getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
 
   // RegBankLegalizeRules is initialized with assigning sets of IDs to opcodes.
   const RegBankLegalizeRules &RBLRules = getRules(ST, MRI);
@@ -509,3 +502,38 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
 
   return true;
 }
+
+bool AMDGPURegBankLegalizeLegacy::runOnMachineFunction(MachineFunction &MF) {
+  if (MF.getProperties().hasFailedISel())
+    return false;
+
+  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
+  GISelCSEAnalysisWrapper &Wrapper =
+      getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
+  GISelCSEInfo &CSEInfo = Wrapper.get(TPC.getCSEConfig());
+  const MachineUniformityInfo &MUI =
+      getAnalysis<MachineUniformityAnalysisPass>().getUniformityInfo();
+  GISelValueTracking &VT =
+      getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
+
+  return runRegBankLegalize(MF, CSEInfo, MUI, VT);
+}
+
+PreservedAnalyses
+AMDGPURegBankLegalizePass::run(MachineFunction &MF,
+                               MachineFunctionAnalysisManager &MFAM) {
+  MFPropsModifier _(*this, MF);
+
+  if (MF.getProperties().hasFailedISel())
+    return PreservedAnalyses::all();
+
+  GISelCSEInfo *CSEInfo = MFAM.getResult<GISelCSEAnalysis>(MF).get();
+  const MachineUniformityInfo &MUI =
+      MFAM.getResult<MachineUniformityAnalysis>(MF);
+  GISelValueTracking &VT = MFAM.getResult<GISelValueTrackingAnalysis>(MF);
+
+  if (!runRegBankLegalize(MF, *CSEInfo, MUI, VT))
+    return PreservedAnalyses::all();
+
+  return getMachineFunctionPassPreservedAnalyses();
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 917e4af4cd8cd..7397e8c7f8a30 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -675,7 +675,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   initializeSILowerI1CopiesLegacyPass(*PR);
   initializeAMDGPUGlobalISelDivergenceLoweringLegacyPass(*PR);
   initializeAMDGPURegBankSelectLegacyPass(*PR);
-  initializeAMDGPURegBankLegalizePass(*PR);
+  initializeAMDGPURegBankLegalizeLegacyPass(*PR);
   initializeSILowerWWMCopiesLegacyPass(*PR);
   initializeAMDGPUMarkLastScratchLoadLegacyPass(*PR);
   initializeSILowerSGPRSpillsLegacyPass(*PR);
@@ -1791,7 +1791,7 @@ void GCNPassConfig::addPreRegBankSelect() {
 
 bool GCNPassConfig::addRegBankSelect() {
   addPass(createAMDGPURegBankSelectLegacyPass());
-  addPass(createAMDGPURegBankLegalizePass());
+  addPass(createAMDGPURegBankLegalizeLegacyPass());
   return false;
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
index 379377d8127b1..743502034d7d2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: abs_sgpr_s16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
index 77dffb1954a0b..7ff3e3999101c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 ---
 name: add_s16_ss
 legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
index f2de7a4b57529..53811ce53db74 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 ---
 name: add_s16_ss
 legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
index f6552a1ac6a18..71da99776b4b3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: add_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
index 4dbe700d7c3d6..b263054f72cd1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: add_v2s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
index e7b7823f10809..ca9a17d854268 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: exp_compr_v2f16_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
index 25b183be7aada..fe2630624e0d0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 --- |
   define amdgpu_ps void @exp_s(float inreg %v0, float inreg %v1, float inreg %v2, float inreg %v3) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
index 96ec9d283c03d..912961accd192 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck %s
 
 ---
 name: buffer_load_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
index 6eb5c7dbfa50c..e8e466be81ad7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o -  %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o -  -verify-each %s | FileCheck %s
 
 ---
 name:            ballot_sgpr_src
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
index 559e5c11486a0..22d36270cff75 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: class_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
index b2858617d9a70..b4fa33a59de02 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: cvt_pkrtz_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
index f2b130d88c5e8..8d5513c2b24a4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: div_fmas_sss_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
index 36c1f8994fb8d..803e00f62842c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: div_scale_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
index 03ef8166367a6..f966875385565 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: ds_append_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
index 96365b551647f..cbb52eb54424c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: ds_bpermute_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
index e3ecdf63817a9..b1a5992af098b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: ds_consume_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
index 9bcab047006a5..7ed11b606e1da 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: ds_gws_init_s_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
index d0a7f95a52c6c..67f1218675903 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: ds_gws_init_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
index f846438b51c7c..34a33699fbc5e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: ds_ordered_add_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
index 335bcc912280f..017815ef613f7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: ds_ordered_swap_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
index aacac0c7c0ba9..688f04a282986 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: ds_permute_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
index 34d37e32fe358..cbb66fbe5f98f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: ds_swizzle_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
index c3c292c359bfb..d94bc95c474bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck %s
 
 ---
 name: fcmp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
index 385c96f184f8a..b1390b2ea4fc9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: fmul_legacy_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
index e9f13465a611e..81b7e01bc0647 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: groupstaticsize
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
index 860dcb8632115..6969228d20c79 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck %s
 
 ---
 name: icmp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
index 9c028c16b8dc3..f7243e56428bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: interp_mov_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
index 76286b091f887..ff6bd96d15342 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: interp_p1_f16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
index 3b43ea9f79f01..57bbcffcfa6cc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: interp_p1_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
index 941a97094753b..920114bebf625 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: interp_p2_f16_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
index 2a76661850df0..262a06eaeaf6b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: interp_p2_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
index db2fccd04b74b..3699c13eb3772 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o -  %s| FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o -  %s| FileCheck %s
 
 ---
 name: kill_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
index f5666a1acd0f5..6dbcf251a9518 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: lds_direct_load_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
index bcef6b6e27847..d4805a07a52fd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu11.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: lds_param_load_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
index 7db93700d394c..b63aadcc0c6f8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: live_mask
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
index b86969cc49f6c..8a1472bd68c1c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.0a -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -amdgpu-mfma-vgpr-form=0 -verify-each %s -o - | FileCheck %s
 
 ---
 name: mfma_f32_32x32x4bf16_1k_vva
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
index deae2d6b836f4..7a711182e8a40 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.42 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -amdgpu-mfma-vgpr-form=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -amdgpu-mfma-vgpr-form=0 -verify-each %s -o - | FileCheck %s
 
 ---
 name: mfma_i32_16x16x32_i8_vva
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
index 6d1f2b98b7644..f707d4dfd72b8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: mfma_f32_32x32x1f32_vva
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
index 338266407c236..b08e8ea4c667b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: ps_live
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
index 7645cb187841a..9016b15e96493 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: readfirstlane_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
index e915de241996e..cadcb4f374099 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: readlane_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
index 371e70d4f58ce..26b43ccb1cd93 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: s_get_waveid_in_workgroup
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
index 0742f25f01251..53bf8efb34caa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o -  %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o -  -verify-each %s | FileCheck %s
 
 ---
 name: getpc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
index 078b49c1a2149..d2e7ad6a108c7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: getreg
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
index cc368accdc889..69432d7638d4a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: memrealtime
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
index 9dcdc87189969..897e3a1ada97a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: memtime
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
index 26c4713df1b8d..d27ba6bfe9ad6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: sendmsg_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
index 27e92f7a0a9b9..477e152733835 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: sendmsghalt_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
index 6a1b93c4a7b7d..d9a4eb446d356 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: update_dpp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
index 300c26d4aa942..a037baa1d3afd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: wqm_demote_scc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
index 841c2ed5d1f40..71f641b4b1e7d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: wqm_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
index 30d6d249a69f5..babbc74c096f4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: writelane_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
index 7d9ee916ea297..a4a820b6baa43 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: strict_wwm_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
index 8152ac7738841..590cb07949008 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: ffbh_u32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
index c03dbc6e78225..7538d2cb87afa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: ffbl_b32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
index a8ca04bfcbf2f..f4c104a830f0f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 # TODO: We could use scalar
 ---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
index c9c7956081d2f..a6b90ed2a108f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: and_s1_sgpr_sgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
index a63c9cfc80c92..ed7a5251e8dd1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: and_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
index e93a86cf81a5a..d1754a9612fda 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: anyext_s32_to_s64_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
index 65a9a84750975..579e9154fa5f4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o -  %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -verify-each -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o -  %s | FileCheck %s
 
 ---
 name: ashr_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
index b8caeb60ebefc..5e40cb9e10f9f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name:            assert_align_vgpr_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
index 9d7f866581e1e..acefe12a8b7c9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name:            assert_sext_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
index 01b6d97237557..4bf4177c35454 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.0a -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name:            assert_zext_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
index 8e807200f692c..d68de54fb8f84 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: amdgpu_atomic_cmpxchg_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
index 5c11018753bb9..e267384d1549b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 # Test G_ATOMICRMW_ADD and G_ATOMICRMW_SUB register bank selection and legalization
 # for different address spaces (flat P0, global P1, local P3) and data sizes (S32, S64)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
index 42672c114b0ac..0a4f30c5fc927 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_add_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
index 53a35114495ea..92384f608fd81 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_and_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
index 835e33fafdbfe..4027f5db68667 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_fadd_global_f32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
index d31d037f6f8d1..b830dfdc763e9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.42 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 # Test G_ATOMICRMW_FADD with V2F16 (V2S16) type - register bank selection and
 # legalization for flat, global, and local address spaces.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
index 5b6754b0d9b44..43c8898657373 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_max_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
index 4c318b2433d5a..a746eb4d89e3c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_min_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
index b4cce7cf68793..ca072516fd6d5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 # Test G_ATOMICRMW_MIN, G_ATOMICRMW_MAX, G_ATOMICRMW_UMIN, G_ATOMICRMW_UMAX
 # register bank selection and legalization for flat, global, and local address spaces.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
index d7360f991dcce..bac9369729177 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_or_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
index cefb2884d6eb7..09ec1479e4437 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_sub_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
index ed7037c4a9a6c..4b0ad9f4e8509 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 # Test G_ATOMICRMW_UINC_WRAP and G_ATOMICRMW_UDEC_WRAP
 # register bank selection and legalization for flat, global, and local address spaces.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
index 15e644a06329b..bb5366e1e278e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_umax_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
index ac1b131e408e1..e52856bb1cfce 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_umin_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
index d7f4e495aafef..fa2def03b2dcc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_xchg_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
index f449d18aa25bb..0b9134065fb1a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu12.01 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.01 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: atomicrmw_xor_global_i32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
index 6b740b0718764..54d29887f3864 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: bitcast_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
index fa052aa43f409..d6d1652f56389 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: bitreverse_i32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
index d8041de8f3211..811e5fee85dae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 --- |
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
index 7e84b13e860f5..f8aeb8ee1e091 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: brcond_vcc_cond
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
index 22ff82ab96851..6e2e25e957cfd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: bswap_i32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
index 5cff5f840d271..ec8aacc6d6f85 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.08 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: build_vector_v2s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
index 062d2ecf3ab1e..5e1b41fbb05bf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck %s
 
 ---
 name: concat_vectors_v4s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
index b1b21f0affd0d..9ab2c59bb76e4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu7.01 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.01 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: test_constant_s32_vgpr_use
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
index 73dfc76460456..9354e2a44c4fb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: ctlz_zero_poison_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
index b472f8f41f2bf..5026ca4deacc1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: ctpop_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
index 6da1b43e4356a..97276164b2d15 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: cttz_zero_poison_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
index 5596f232535eb..6f2629ae00064 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 # Check the default mappings for various instructions.
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
index 472d6e9af0833..b123347394d65 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck -check-prefix=WAVE64 %s
 # RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu10.10 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck -check-prefix=WAVE32 %s
 
 
 ---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
index d3e9ed16af3d3..15bb37bbb247c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck -check-prefix=WAVE64 %s
 # RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgpu10.10 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck -check-prefix=WAVE32 %s
 
 
 ---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
index d4dd6647d6647..9f9a426906a34 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: fabs_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
index ca79422c5e059..4599008a44e5d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: fadd_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
index 8a09c002c5e7e..5701062141c4f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: fcanonicalize_s16_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
index 74c2bc0c03b77..1992734efc360 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: fceil_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
index 68c292ecb94bf..1bbdf07800d07 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX803 %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck --check-prefixes=GCN,GFX803 %s
 # RUN: llc -mtriple=amdgpu11.50 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN,GFX1150 %s
+# RUN: llc -mtriple=amdgpu11.50 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck --check-prefixes=GCN,GFX1150 %s
 
 ---
 name: fcmp_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
index 32fb11be5fcdc..e446229b407c4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
@@ -1,7 +1,10 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX8 %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck -check-prefixes=CHECK,GFX8 %s
 # RUN: llc -mtriple=amdgpu11.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX11 %s
+# RUN: llc -mtriple=amdgpu11.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck -check-prefixes=CHECK,GFX11 %s
 # RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX12 %s
+# RUN: llc -mtriple=amdgpu12.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck -check-prefixes=CHECK,GFX12 %s
 
 ---
 name: fexp2_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
index cefb21f186f32..4d2707faf1c2c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: ffloor_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
index e4800ce6f0add..1cbe8714f3658 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: flog2_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
index 323eac10576e5..e1219c9ec3db6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: fma_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
index 50ed86bd79e3f..144f87750c2fa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: fmul_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
index 2fce2409e38b0..9732a961447ab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: fneg_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
index 9c621513365ad..eed0dc301c96d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - -regbankselect-fast | FileCheck %s
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - -regbankselect-greedy | FileCheck %s
 
 ---
 name: fpext_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
index 086b7d81132e8..b903c4a95002f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: fptosi_sat_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
index 9dadcbc9cd525..ae0c17053d3f6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: fptosi_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
index 26fcaa76cb721..4913821abde71 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: fptoui_sat_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
index b72a3df834b0b..d4d9bbc163fbd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: fptoui_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
index 511cf9338be25..6f41558328490 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - -regbankselect-fast | FileCheck %s
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - -regbankselect-greedy | FileCheck %s
 
 ---
 name: fptrunc_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
index d4a5500f5ce16..ab21368e2d1f8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: test_frame_index_p5
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
index e4dd859b0cb2f..9598cf387082d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
@@ -1,7 +1,10 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 # RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 # RUN: llc -mtriple=amdgpu10.10 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: test_freeze_s1_vgpr_to_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
index 49bf19b061cc9..3c29e6f1bd2ac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck %s
 
 ---
 name: fshr_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
index 06ea3c1d0db3c..4e2b01624c662 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
 # RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck -check-prefixes=GCN,GFX12 %s
+# RUN: llc -mtriple=amdgpu12.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck -check-prefixes=GCN,GFX12 %s
 
 ---
 name: fsqrt_s16_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
index f64a47863188f..b2ae9e09db1c8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - -regbankselect-fast | FileCheck %s
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - -regbankselect-greedy | FileCheck %s
 
 ---
 name: fsub_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
index 5d4fab4a4bd24..c0a3a82739149 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck -check-prefix=GFX8 %s
 
 ---
 name: icmp_eq_s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
index 95fb62e125564..b605d4770aa28 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: intrinsic_roundeven_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
index 9c2527ccdafaf..4a121ab8e7740 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: intrinsic_trunc_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
index a788e7b5e65bc..210884d60ecd2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
@@ -2,6 +2,7 @@
 # RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
 # RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: inttoptr_s_p0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
index e017b62c85dd7..4a9a83e41df3e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
@@ -1,7 +1,10 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu7.01-amd-amdhsa -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX7
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu7.01-amd-amdhsa -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s -check-prefixes=GCN,GFX7
 # RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.00-amd-amdhsa -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX12
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.00-amd-amdhsa -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s -check-prefixes=GCN,GFX12
 # RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.50-amd-amdhsa -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s -check-prefixes=GCN,GFX12
+# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.50-amd-amdhsa -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s -check-prefixes=GCN,GFX12
 
 --- |
   define amdgpu_kernel void @load_global_v8i32_non_uniform(ptr addrspace(1) %in) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
index 0538f6ee760c3..741d26b7ec4e8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -verify-each -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
 
 ---
 name: lshr_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
index cb8aec728d984..1b08d6ee09fd5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: merge_s64_s32_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
index 27d5ccbe29ece..9fb8aec81bf07 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
@@ -2,7 +2,9 @@
 # RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX10
 # RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX12
 # RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX10
+# RUN: llc -mtriple=amdgpu10.10 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX10
 # RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX12
+# RUN: llc -mtriple=amdgpu12.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX12
 
 ---
 name: salu_float
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
index d7fdf3be05c80..12a22e6928a42 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
@@ -1,6 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS
 # RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS
+# RUN: llc -mtriple=amdgpu10.10 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s -check-prefixes=NEW_RBS
 
 ---
 name: uniform_in_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
index 5de0179eb503b..1e6fdfd226005 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: mul_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
index 9747902237533..38f2934fa0c59 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: or_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
index a8c134f213988..9111b050c1e44 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: gep_p0_s_k
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
index f64b16b53ffd0..e20ca5c2f5b98 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu12.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: ptrmask_p1_s_k
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
index 8541e284c8ddb..52be5a6930efb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
@@ -2,6 +2,7 @@
 # RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
 # RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: ptrtoint_s_p0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
index 96ab2d06f3584..9069125827371 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: sadde_s32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
index 2ccb566fd85f6..96e56407750f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu11.50 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX1150 %s
+# RUN: llc -mtriple=amdgpu11.50 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck --check-prefixes=GFX1150 %s
 
 ---
 name:            fadd_f32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
index c77bdc4cb1b1a..565e8ac2bc458 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck %s
 
 ...
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
index 6c4f87a6ec0c3..d875cad109757 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: select_s32_scc_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
index fdb63e5440ab0..fddeab85bd2c9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: sext_inreg_s_s32_1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
index 7e8e0ff2228e2..55c79ec9a90ff 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: sext_s32_to_s64_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
index 9d8759eefa5dd..ca901db65c5cd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: sextload_constant_i8_to_i32_uniform
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
index 85a093b04cdcc..cbaa8d007c3b7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -verify-each -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
 
 ---
 name: shl_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
index 91a29a0b12743..354b5788a4975 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: sitofp_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
index 7c67d955e6205..6ae29fd474b03 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: smax_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
index db21e4fdeb936..fdad9aa760b97 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: smin_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
index 68057f031eccc..adc2ba8a93cb7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: smulh_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
index 87c9d5eb1a60a..0d55d87045d3e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
@@ -1,7 +1,10 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu7.01-mesa-mesa3d -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgpu7.01-mesa-mesa3d -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck -check-prefix=GFX7 %s
 # RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck -check-prefix=GFX12 %s
 # RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck -check-prefix=GFX12 %s
 
 --- |
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
index 2faca040ab1d1..4a06dbe8bb286 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 ---
 name: ssube_s32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
index 0b6964129a732..ea007463b385d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: sub_s16_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
index 2774db98136ab..dbc5b1d196d9c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX6 %s
+# RUN: llc -mtriple=amdgpu6.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck -check-prefixes=GFX,GFX6 %s
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX8 %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck -check-prefixes=GFX,GFX8 %s
 
 ---
 name: trunc_i64_to_i32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
index 46ff97b0a0d94..d6485f18cb0ce 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 ---
 name: uadde_s32_sss
 legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
index 0cd95240909b1..58baeb44b6ad2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: uaddo_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
index 8571a3df50aff..1bdcd3e88b34d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck %s
 
 ...
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
index bf3c5a2cd2bbc..bb0f67a2688db 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: uitofp_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
index 485658e94ce2e..01d7871d3ad22 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: umax_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
index 46021b59175fb..f4579925394b4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name: umin_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
index 6bd70bd80cd01..5c1b2434e7998 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu6.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgpu6.00-amd-amdpal -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgpu9.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu9.00-amd-amdpal -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: umulh_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
index b39fd4b068486..9c39001d016d7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu7.00-amd-amdpal -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX7 %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdpal -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -mattr=+unaligned-access-mode %s -verify-each -o - | FileCheck -check-prefixes=GFX7 %s
 # RUN: llc -mtriple=amdgpu10.10-amd-amdpal -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX1010 %s
+# RUN: llc -mtriple=amdgpu10.10-amd-amdpal -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -mattr=+unaligned-access-mode %s -verify-each -o - | FileCheck -check-prefixes=GFX1010 %s
 
 # FixMe: need merge/unmerge artifact combine
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
index 4af8881a3e894..6cd44d0e04074 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: test_unmerge_s64_s32_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
index 195d5588b44d1..0f8834d8412a1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
@@ -1,6 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: usube_s32_sss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
index 5f145cee4d11b..5e270b7d47a24 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: usubo_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
index 135fb6e444c33..074831197752f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - -verify-each %s | FileCheck %s
 
 ---
 name:            waterfall_divergent_call_p0_no_args
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
index 329b205419c62..9d7a939eaf325 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
@@ -1,7 +1,10 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck -check-prefix=GFX8 %s
 # RUN: llc -mtriple=amdgpu9.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck -check-prefix=GFX9 %s
 # RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgpu10.10 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck -check-prefix=GFX10 %s
 
 ---
 name: constant_load_i8_align8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
index 4cac975636740..b50abc3871da3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: xor_s32_ss
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
index 6c6f41293f4ab..5cf94e9484efe 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-each -o - | FileCheck %s
 
 ---
 name: zext_s32_to_s64_s
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
index 52b434b76ba6b..b12e63b5df0c7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03 -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each -o - %s | FileCheck %s
 
 ---
 name: zextload_constant_i8_to_i32_uniform
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
index f976217350185..c3893c9593d12 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgpu7.01 -mattr=+flat-for-global -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.01 -mattr=+flat-for-global -passes='amdgpu-regbankselect,amdgpu-regbanklegalize' -verify-each %s -o - | FileCheck %s
 
 --- |
   define amdgpu_kernel void @load_constant(ptr addrspace(4) %ptr0) {

