[llvm-branch-commits] [llvm] [RISCV] Support i64 accumulator for Zvdot4a8i partial reductions (PR #215517)

[Craig Topper via llvm-branch-commits]

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@@ -9921,7 +9921,7 @@ SDValue RISCVTargetLowering::lowerPARTIAL_REDUCE_MLA(SDValue Op,
 
     MVT NarrowVT = VT.changeVectorElementType(MVT::i32);
     if (VT.isScalableVector() &&
-        RISCVTargetLowering::getLMUL(NarrowVT) == RISCVVType::LMUL_1) {
+        RISCVTargetLowering::getLMUL(NarrowVT) > RISCVVType::LMUL_RESERVED) {
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topperc wrote:

We should not be using LMUL_RESERVED like this. I had to look up what value it is. Is this trying to exclude fractional LMULs? Use decodeVLMUL and check the fractional flag?

https://github.com/llvm/llvm-project/pull/215517