[llvm-branch-commits] [llvm] [AMDGPU] start using new pass manager for backend codegen (PR #210251)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Aug 18 02:22:45 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Vikram Hegde (vikramRH)
<details>
<summary>Changes</summary>
NPM is still disabled for GISel path until ready.
Next steps would be to port all AMDGPU tests to new pass manager.
Few comments on codegen diffs seen.
1. few tests show outputs printed in different order as compared to legacy mainly due to NPM using LazyCallGraph. (such as llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll)
2. pipeline differs particulary for loop passes due to Loop canonicalization mandates. (eg: llvm/test/CodeGen/AMDGPU/memmove-var-size.ll)
---
Patch is 367.35 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210251.diff
120 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h (+7)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx1250.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll (+11-11)
- (added) llvm/test/CodeGen/AMDGPU/call-constexpr-gisel.ll (+243)
- (added) llvm/test/CodeGen/AMDGPU/call-constexpr-sdag.ll (+238)
- (removed) llvm/test/CodeGen/AMDGPU/call-constexpr.ll (-388)
- (modified) llvm/test/CodeGen/AMDGPU/convergence-laneops.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/dead_bundle.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/dummy-regalloc-priority-advisor.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-direct-chain.ll (+21-21)
- (modified) llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-indirect.ll (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation.ll (+25-25)
- (modified) llvm/test/CodeGen/AMDGPU/emit-high-vgprs.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fastregalloc-sgpr-only.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/function-resource-usage.ll (+46-46)
- (modified) llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll (+36-37)
- (modified) llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/issue48473.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/large-avgpr-assign-last.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llc-pipeline.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll (+72-72)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll (+306-306)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll (+230-230)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll (+230-226)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll (+310-310)
- (modified) llvm/test/CodeGen/AMDGPU/lo16-hi16-illegal-copy.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/lo16-hi16-physreg-copy.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-sgpr.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/lto-lower-module-lds.ll (+14-12)
- (modified) llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll (+5-7)
- (modified) llvm/test/CodeGen/AMDGPU/memmove-var-size.ll (+115-115)
- (modified) llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll (+24-34)
- (modified) llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/pr51516.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll (+67-64)
- (modified) llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/remat-smrd.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/remat-sop.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/remat-vop.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll (+2-1)
- (modified) llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/shift-select.ll (+5-4)
- (modified) llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/stress-regalloc-limits-regalloc.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/threeaddr-wmma.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/vopc-remat.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/wave32.ll (+8-6)
- (modified) llvm/test/CodeGen/AMDGPU/wwm-regalloc-partial-pool.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/wwm-spill-superclass-pseudo.mir (+2-2)
- (modified) llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll (+3-3)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index 189b6399dbf7b..7b57b9f684f0e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -99,6 +99,13 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
bool useIPRA() const override { return true; }
+ // TODO: just return true when GIsel passes are ported to NPM.
+ bool shouldDefaultToNewPM() const override {
+ return !Options.EnableGlobalISel &&
+ (getCGPassBuilderOption().EnableGlobalISelOption !=
+ cl::boolOrDefault::BOU_TRUE);
+ }
+
Error buildCodeGenPipeline(ModulePassManager &MPM, ModuleAnalysisManager &MAM,
raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
CodeGenFileType FileType,
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
index d35f04c64ac89..f3b0a315d6166 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
@@ -1,5 +1,5 @@
; RUN: not llc -mtriple=amdgpu9.0a-amd-amdhsa -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
-; RUN: not llc -mtriple=amdgpu9.0a-amd-amdhsa -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: not llc -enable-new-pm=0 -mtriple=amdgpu9.0a-amd-amdhsa -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
; ERR: error: <unknown>:0:0: no registers from class available to allocate in function 'no_free_vgprs_at_agpr_to_agpr_copy'
diff --git a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx1250.mir
index 9b4e364063f36..3eb221620587f 100644
--- a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx1250.mir
+++ b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx1250.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgpu12.50 -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX1250 %s
+# RUN: llc -mtriple=amdgpu12.50 -start-before=greedy,1 -stop-after=virt-reg-rewriter,3 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX1250 %s
# Using the unaligned vector tuples are OK as long as they aren't used
# in a real instruction.
diff --git a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
index cb042fa6bc261..76c807aaeb0da 100644
--- a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
+++ b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgpu9.08 -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX908 %s
+# RUN: llc -mtriple=amdgpu9.08 -start-before=greedy,1 -stop-after=virt-reg-rewriter,3 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX908 %s
---
# GCN-LABEL: name: alloc_vgpr_64
diff --git a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
index c6593c0dbeb45..6bebdb59a1548 100644
--- a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
+++ b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgpu9.0a -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
+# RUN: llc -mtriple=amdgpu9.0a -start-before=greedy,1 -stop-after=virt-reg-rewriter,3 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
# RUN: llc -enable-new-pm -mtriple=amdgpu9.0a -passes='greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>,stack-slot-coloring,si-lower-sgpr-spills,si-pre-allocate-wwm-regs,greedy<wwm>,si-lower-wwm-copies,virt-reg-rewriter<no-clear-vregs>,amdgpu-reserve-wwm-regs,greedy<vgpr>,amdgpu-nsa-reassign,virt-reg-rewriter' -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
# Using the unaligned vector tuples are OK as long as they aren't used
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
index 412933f78660b..332f237d8d43e 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
@@ -1,15 +1,15 @@
; -enable-misched=false makes the register usage more predictable
; -regalloc=fast just makes the test run faster
-; RUN: llc -mtriple=amdgpu9.00 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX9
-; RUN: llc -mtriple=amdgpu9.0a -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX90A
-; RUN: llc -mtriple=amdgpu10.10 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX10WGP-WAVE32
-; RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize64 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX10WGP-WAVE64
-; RUN: llc -mtriple=amdgpu10.10 -mattr=+cumode -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX10CU-WAVE32
-; RUN: llc -mtriple=amdgpu10.10 -mattr=+cumode,+wavefrontsize64 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX10CU-WAVE64
-; RUN: llc -mtriple=amdgpu11.00 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX11WGP-WAVE32
-; RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize64 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX11WGP-WAVE64
-; RUN: llc -mtriple=amdgpu11.00 -mattr=+cumode -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX11CU-WAVE32
-; RUN: llc -mtriple=amdgpu11.00 -mattr=+cumode,+wavefrontsize64 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX11CU-WAVE64
+; RUN: llc -mtriple=amdgpu9.00 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX9
+; RUN: llc -mtriple=amdgpu9.0a -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX90A
+; RUN: llc -mtriple=amdgpu10.10 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX10WGP-WAVE32
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize64 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX10WGP-WAVE64
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+cumode -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX10CU-WAVE32
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+cumode,+wavefrontsize64 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX10CU-WAVE64
+; RUN: llc -mtriple=amdgpu11.00 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX11WGP-WAVE32
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize64 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX11WGP-WAVE64
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+cumode -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX11CU-WAVE32
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+cumode,+wavefrontsize64 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc-npm=fast -vgpr-regalloc-npm=fast -wwm-regalloc-npm=fast < %s | FileCheck %s --check-prefixes=GCN,GFX11CU-WAVE64
define internal void @use256vgprs() {
%v0 = call i32 asm sideeffect "; def $0", "=v"()
diff --git a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
index 11b009307ce1e..6eb7181d99c53 100644
--- a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
+++ b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -start-before=greedy,1 -stop-after=prolog-epilog -verify-machineinstrs -verify-regalloc -o - %s | FileCheck --check-prefixes=GCN %s
+# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -start-before=greedy,2 -stop-after=prolog-epilog -verify-machineinstrs -verify-regalloc -o - %s | FileCheck --check-prefixes=GCN %s
# The VGPR pair spilled and restored around the callsite is used in the next basic block.
#
diff --git a/llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir b/llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
index a2763a1a1ccfd..7d0ced376f1cb 100644
--- a/llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
+++ b/llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -start-before=greedy,2 -stop-after=virtregrewriter,2 -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -start-before=greedy,3 -stop-after=virt-reg-rewriter,3 -o - %s | FileCheck %s
---
name: bad_ra
diff --git a/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll b/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
index 7694e30a612af..71134ed6b67fb 100644
--- a/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -O0 --stop-after=regallocfast,2 -o - %s | FileCheck -check-prefix=REGALLOC %s
+; RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -O0 --stop-after=regallocfast,3 -o - %s | FileCheck -check-prefix=REGALLOC %s
; Test to check if the bb prolog spills are inserted correctly during regalloc.
define i32 @prolog_spill(i32 %arg0, i32 %arg1, i32 %arg2) {
diff --git a/llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir b/llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
index 7ecb1cd7a5343..e5e436c8fc97a 100644
--- a/llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
+++ b/llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu10.31-amd-amdhsa -verify-machineinstrs -start-after=unreachable-mbb-elimination -stop-after=phi-node-elimination -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.31-amd-amdhsa -verify-machineinstrs -start-after=unreachable-mbb-elimination -stop-after=si-lower-control-flow -o - %s | FileCheck %s
# FIXME: Should be able to just use run-pass, but need to keep
# LiveVariables live after for the verifier. Also -start-before
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
index 4ee6585c0a84a..b39b6cc4712de 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
@@ -1,16 +1,25 @@
-; RUN: llc -O0 -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck -check-prefix=ALL %s
+; RUN: llc -O0 -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck -check-prefix=ALL,GFX908 %s
; RUN: llc -O0 -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck -check-prefixes=ALL,GFX90A %s
-; CallGraphAnalysis, which CodeGenSCC order depends on, does not look
-; through aliases. If GlobalOpt is never run, we do not see direct
-; calls,
-
@alias = hidden alias void (), ptr @aliasee_default
-; ALL-LABEL: {{^}}kernel:
-; ALL: .amdhsa_next_free_vgpr max(totalnumvgprs(.Lkernel.num_agpr, .Lkernel.num_vgpr), 1, 0)
-; ALL-NEXT: .amdhsa_next_free_sgpr max(.Lkernel.numbered_sgpr+extrasgprs(.Lkernel.uses_vcc, .Lkernel.uses_flat_scratch, 1), 1, 0)-extrasgprs(.Lkernel.uses_vcc, .Lkernel.uses_flat_scratch, 1)
-; GFX90A-NEXT: .amdhsa_accum_offset (((((alignto(max(1, .Lkernel.num_vgpr), 4)/4)-1)&~65536)&63)+1)*4
+define internal void @aliasee_default() #1 {
+bb:
+ call void asm sideeffect "; clobber a26 ", "~{a26}"()
+ ret void
+}
+; ALL: .set .Laliasee_default.num_vgpr, 0
+; ALL-NEXT: .set .Laliasee_default.num_agpr, 27
+; ALL-NEXT: .set .Laliasee_default.numbered_sgpr, 32
+
+; GFX908-LABEL: {{^}}kernel:
+; GFX908: .amdhsa_next_free_vgpr 41
+; GFX908-NEXT: .amdhsa_next_free_sgpr 33
+
+; GFX90A-LABEL: {{^}}kernel:
+; GFX90A: .amdhsa_next_free_vgpr 71
+; GFX90A-NEXT: .amdhsa_next_free_sgpr 33
+; GFX90A-NEXT: .amdhsa_accum_offset 44
; ALL: .set .Lkernel.num_vgpr, max(41, .Laliasee_default.num_vgpr)
; ALL-NEXT: .set .Lkernel.num_agpr, max(0, .Laliasee_default.num_agpr)
@@ -21,15 +30,6 @@ bb:
ret void
}
-define internal void @aliasee_default() #1 {
-bb:
- call void asm sideeffect "; clobber a26 ", "~{a26}"()
- ret void
-}
-; ALL: .set .Laliasee_default.num_vgpr, 0
-; ALL-NEXT: .set .Laliasee_default.num_agpr, 27
-; ALL-NEXT: .set .Laliasee_default.numbered_sgpr, 32
-
attributes #0 = { noinline norecurse nounwind optnone }
attributes #1 = { noinline norecurse nounwind readnone willreturn }
attributes #2 = { nounwind readnone willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
index 8e74dcdd9490f..296507e2c2bbf 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
@@ -6,6 +6,15 @@
@alias0 = hidden alias void (), ptr @aliasee_default_vgpr64_sgpr102
+; CHECK: .set .Laliasee_default_vgpr64_sgpr102.num_vgpr, 53
+; CHECK-NEXT: .set .Laliasee_default_vgpr64_sgpr102.num_agpr, 0
+; CHECK-NEXT: .set .Laliasee_default_vgpr64_sgpr102.numbered_sgpr, 32
+define internal void @aliasee_default_vgpr64_sgpr102() #1 {
+bb:
+ call void asm sideeffect "; clobber v52 ", "~{v52}"()
+ ret void
+}
+
; CHECK-LABEL: {{^}}kernel0:
; CHECK: .set .Lkernel0.num_vgpr, max(41, .Laliasee_default_vgpr64_sgpr102.num_vgpr)
; CHECK-NEXT: .set .Lkernel0.num_agpr, max(0, .Laliasee_default_vgpr64_sgpr102.num_agpr)
@@ -16,15 +25,6 @@ bb:
ret void
}
-; CHECK: .set .Laliasee_default_vgpr64_sgpr102.num_vgpr, 53
-; CHECK-NEXT: .set .Laliasee_default_vgpr64_sgpr102.num_agpr, 0
-; CHECK-NEXT: .set .Laliasee_default_vgpr64_sgpr102.numbered_sgpr, 32
-define internal void @aliasee_default_vgpr64_sgpr102() #1 {
-bb:
- call void asm sideeffect "; clobber v52 ", "~{v52}"()
- ret void
-}
-
attributes #0 = { noinline norecurse nounwind optnone }
attributes #1 = { noinline norecurse nounwind readnone willreturn }
attributes #2 = { nounwind readnone willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
index 05412b343ecb7..81ee5b96a297f 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
@@ -8,9 +8,18 @@
; The parent kernel has a higher VGPR usage than the possible callees.
+; CHECK: .set .Laliasee_vgpr32_sgpr76.num_vgpr, 27
+; CHECK-NEXT: .set .Laliasee_vgpr32_sgpr76.num_agpr, 0
+; CHECK-NEXT: .set .Laliasee_vgpr32_sgpr76.numbered_sgpr, 32
+define internal void @aliasee_vgpr32_sgpr76() #1 {
+bb:
+ call void asm sideeffect "; clobber v26 ", "~{v26}"()
+ ret void
+}
+
; CHECK-LABEL: {{^}}kernel1:
-; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(.Lkernel1.num_agpr, .Lkernel1.num_vgpr), 1, 0)
-; CHECK-NEXT: .amdhsa_next_free_sgpr max(.Lkernel1.numbered_sgpr+extrasgprs(.Lkernel1.uses_vcc, .Lkernel1.uses_flat_scratch, 1), 1, 0)-extrasgprs(.Lkernel1.uses_vcc, .Lkernel1.uses_flat_scratch, 1)
+; CHECK: .amdhsa_next_free_vgpr 42
+; CHECK-NEXT: .amdhsa_next_free_sgpr 33
; CHECK: .set .Lkernel1.num_vgpr, max(42, .Laliasee_vgpr32_sgpr76.num_vgpr)
; CHECK-NEXT: .set .Lkernel1.num_agpr, max(0, .Laliasee_vgpr32_sgpr76.num_agpr)
@@ -22,15 +31,6 @@ bb:
ret void
}
-; CHECK: .set .Laliasee_vgpr32_sgpr76.num_vgpr, 27
-; CHECK-NEXT: .set .Laliasee_vgpr32_sgpr76.num_agpr, 0
-; CHECK-NEXT: .set .Laliasee_vgpr32_sgpr76.numbered_sgpr, 32
-define internal void @aliasee_vgpr32_sgpr76() #1 {
-bb:
- call void asm sideeffect "; clobber v26 ", "~{v26}"()
- ret void
-}
-
attributes #0 = { noinline norecurse nounwind optnone }
attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-waves-per-eu"="8,10" }
attributes #2 = { nounwind readnone willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
index 5735ef21b084d..afcac9cb4327d 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
@@ -6,9 +6,18 @@
@alias2 = hidden alias void (), ptr @aliasee_vgpr64_sgpr102
+; CHECK: .set .Laliasee_vgpr64_sgpr102.num_vgpr, 53
+; CHECK-NEXT: .set .Laliasee_vgpr64_sgpr102.num_agpr, 0
+; CHECK-NEXT: .set .Laliasee_vgpr64_sgpr102.numbered_sgpr, 32
+define internal void @aliasee_vgpr64_sgpr102() #1 {
+bb:
+ call void asm sideeffect "; clobber v52 ", "~{v52}"()
+ ret void
+}
+
; CHECK-LABEL: {{^}}kernel2:
-; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(.Lkernel2.num_agpr, .Lkernel2.num_vgpr), 1, 0)
-; CHECK-NEXT: .amdhsa_next_free_sgpr max(.Lkernel2.numbered_sgpr+extrasgprs(.Lkernel2.uses_vcc, .Lkernel2.uses_flat_scratch, 1), 1, 0)-extrasgprs(.Lkernel2.uses_vcc, .Lkernel2.uses_flat_scratch, 1)
+; CHECK: .amdhsa_next_free_vgpr 53
+; CHECK-NEXT: .amdhsa_next_free_sgpr 33
; CHECK: .set .Lkernel2.num_vgpr, max(41, .Laliasee_vgpr64_sgpr102.num_vgpr)
; CHECK-NEXT: .set .Lkernel2.num_agpr, max(0, .Laliasee_vgpr64_sgpr102.num_agpr)
@@ -19,15 +28,6 @@ bb:
ret void
}
-; CHECK: .set .Laliasee_vgpr64_sgpr102.num_vgpr, 53
-; CHECK-NEXT: .set .Laliasee_vgpr64_sgpr102.num_agpr, 0
-; CHECK-NEXT: .set .Laliasee_vgpr64_sgpr102.numbered_sgpr, 32
-define internal void @aliasee_vgpr64_sgpr102() #1 {
-bb:
- call void asm sideeffect "; clobber v52 ", "~{v52}"()
- ret void
-}
-
attributes #0 = { noinline norecurse nounwind optnone }
attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-waves-per-eu"="4,10" }
attributes #2 = { nounwind readnone willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
index 7e6be8593e3c5..4c094d75ecd70 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
@@ -6,9 +6,18 @@
@alias3 = hidden alias void (), ptr @aliasee_vgpr256_sgpr102
+; CHECK: .set .Laliasee_vgpr256_sgpr102.num_vgpr, 253
+; CHECK-NEXT: .set .Laliasee_vgpr256_sgpr102.num_agpr, 0
+; CHECK-NEXT...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/210251
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