[llvm-branch-commits] [NewPM] Port ir-translator (PR #216915)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Aug 17 22:05:21 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
@llvm/pr-subscribers-backend-arm
Author: Aiden Grossman (boomanaiden154)
<details>
<summary>Changes</summary>
Standard NewPM pass porting.
Similar to #<!-- -->215516, but theoretically with more code sharing.
---
Patch is 65.18 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/216915.diff
18 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h (+46-13)
- (modified) llvm/include/llvm/InitializePasses.h (+1-1)
- (modified) llvm/include/llvm/Passes/MachinePassRegistry.def (+1-1)
- (modified) llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp (+1-1)
- (modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+264-206)
- (modified) llvm/lib/Passes/PassBuilder.cpp (+1)
- (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/ARMTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/BPF/BPFTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/Mips/MipsTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/X86/X86TargetMachine.cpp (+1-1)
- (modified) llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir (+3)
- (modified) llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp (+1-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
index 63758a760d5ed..0ea035e5dcd70 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
@@ -20,12 +20,21 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/BranchProbabilityInfo.h"
+#include "llvm/Analysis/OptimizationRemarkEmitter.h"
#include "llvm/CodeGen/CodeGenCommonISel.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
+#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/LibcallLoweringInfo.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/StackProtector.h"
#include "llvm/CodeGen/SwiftErrorValueTracking.h"
#include "llvm/CodeGen/SwitchLoweringUtils.h"
+#include "llvm/IR/Analysis.h"
+#include "llvm/IR/PassManager.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/CodeGen.h"
#include <memory>
@@ -48,7 +57,6 @@ class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
class MachineRegisterInfo;
-class OptimizationRemarkEmitter;
class PHINode;
class TargetLibraryInfo;
class TargetPassConfig;
@@ -63,14 +71,27 @@ class Value;
// the information from the LLVM IR.
// The idea is that ultimately we would be able to free up the memory used
// by the LLVM IR as soon as the translation is over.
-class LLVM_ABI IRTranslator : public MachineFunctionPass {
+class LLVM_ABI IRTranslatorLegacy : public MachineFunctionPass {
public:
static char ID;
+ IRTranslatorLegacy(CodeGenOptLevel OptLevel = CodeGenOptLevel::None);
+
+ StringRef getPassName() const override { return "IRTranslator"; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
private:
+ CodeGenOptLevel OptLevel;
+};
+
+class IRTranslatorImpl {
/// Interface used to lower the everything related to calls.
const CallLowering *CLI = nullptr;
+ SSPLayoutInfo *SPInfo = nullptr;
+
/// This class contains the mapping between the Values to vreg related data.
class ValueToVRegInfo {
public:
@@ -623,9 +644,6 @@ class LLVM_ABI IRTranslator : public MachineFunctionPass {
const DataLayout *DL = nullptr;
- /// Current target configuration. Controls how the pass handles errors.
- const TargetPassConfig *TPC = nullptr;
-
CodeGenOptLevel OptLevel;
/// Current optimization remark emitter. Used to report failures.
@@ -653,7 +671,7 @@ class LLVM_ABI IRTranslator : public MachineFunctionPass {
/// Switch analysis and optimization.
class GISelSwitchLowering : public SwitchCG::SwitchLowering {
public:
- GISelSwitchLowering(IRTranslator *irt, FunctionLoweringInfo &funcinfo)
+ GISelSwitchLowering(IRTranslatorImpl *irt, FunctionLoweringInfo &funcinfo)
: SwitchLowering(funcinfo), IRT(irt) {
assert(irt && "irt is null!");
}
@@ -667,7 +685,7 @@ class LLVM_ABI IRTranslator : public MachineFunctionPass {
~GISelSwitchLowering() override = default;
private:
- IRTranslator *IRT;
+ IRTranslatorImpl *IRT;
};
std::unique_ptr<GISelSwitchLowering> SL;
@@ -784,11 +802,8 @@ class LLVM_ABI IRTranslator : public MachineFunctionPass {
BranchProbability Prob = BranchProbability::getUnknown());
public:
- IRTranslator(CodeGenOptLevel OptLevel = CodeGenOptLevel::None);
-
- StringRef getPassName() const override { return "IRTranslator"; }
-
- void getAnalysisUsage(AnalysisUsage &AU) const override;
+ IRTranslatorImpl(CodeGenOptLevel OptLevel = CodeGenOptLevel::None)
+ : OptLevel(OptLevel) {}
// Algo:
// CallLowering = MF.subtarget.getCallLowering()
@@ -802,7 +817,25 @@ class LLVM_ABI IRTranslator : public MachineFunctionPass {
// if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence))
// reportFatalUsageError("Don't know how to translate input");
// finalize()
- bool runOnMachineFunction(MachineFunction &MF) override;
+ bool runOnMachineFunction(MachineFunction &MF,
+ function_ref<GISelCSEInfo *()> GetCSEInfo,
+ bool ShouldSkipOpts,
+ function_ref<AAResults *()> GetAAResults,
+ function_ref<BranchProbabilityInfo *()> GetBPI,
+ function_ref<AssumptionCache *()> GetAC,
+ TargetLibraryInfo *LibraryInfo,
+ const LibcallLoweringInfo *LibcallInfo,
+ SSPLayoutInfo *StackProtectorInfo);
+};
+
+class IRTranslatorPass : public RequiredPassInfoMixin<IRTranslatorPass> {
+ CodeGenOptLevel OptLevel;
+
+public:
+ IRTranslatorPass(CodeGenOptLevel OptLevel) : OptLevel(OptLevel) {}
+
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
};
} // end namespace llvm
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 74fe01a46b5b9..00a5b0fc086e3 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -134,7 +134,7 @@ LLVM_ABI void initializeGlobalsAAWrapperPassPass(PassRegistry &);
LLVM_ABI void initializeHardwareLoopsLegacyPass(PassRegistry &);
LLVM_ABI void initializeLibcallLoweringInfoWrapperPass(PassRegistry &);
LLVM_ABI void initializeMIRProfileLoaderPassPass(PassRegistry &);
-LLVM_ABI void initializeIRTranslatorPass(PassRegistry &);
+LLVM_ABI void initializeIRTranslatorLegacyPass(PassRegistry &);
LLVM_ABI void initializeIVUsersWrapperPassPass(PassRegistry &);
LLVM_ABI void initializeIfConverterPass(PassRegistry &);
LLVM_ABI void
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index c38507bf70254..dae1be841d3d8 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -80,6 +80,7 @@ MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
MACHINE_FUNCTION_PASS("finalizebundle-test", FinalizeBundleTestPass())
MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", FixupStatepointCallerSavedPass())
MACHINE_FUNCTION_PASS("init-undef", InitUndefPass())
+MACHINE_FUNCTION_PASS("ir-translator", IRTranslatorPass(TM->getOptLevel()))
MACHINE_FUNCTION_PASS("kcfi", MachineKCFIPass())
MACHINE_FUNCTION_PASS("gc-empty-basic-blocks", GCEmptyBasicBlocksPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
@@ -242,7 +243,6 @@ DUMMY_MACHINE_FUNCTION_PASS("fs-profile-loader", MIRProfileLoaderNewPass)
DUMMY_MACHINE_FUNCTION_PASS("funclet-layout", FuncletLayoutPass)
DUMMY_MACHINE_FUNCTION_PASS("implicit-null-checks", ImplicitNullChecksPass)
DUMMY_MACHINE_FUNCTION_PASS("instruction-select", InstructionSelectPass)
-DUMMY_MACHINE_FUNCTION_PASS("irtranslator", IRTranslatorPass)
DUMMY_MACHINE_FUNCTION_PASS("legalizer", LegalizerPass)
DUMMY_MACHINE_FUNCTION_PASS("lrshrink", LiveRangeShrinkPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass)
diff --git a/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp b/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp
index 5c0d8282a0add..8fe4ea0a80220 100644
--- a/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp
@@ -15,7 +15,7 @@
using namespace llvm;
void llvm::initializeGlobalISel(PassRegistry &Registry) {
- initializeIRTranslatorPass(Registry);
+ initializeIRTranslatorLegacyPass(Registry);
initializeLegalizerPass(Registry);
initializeLoadStoreOptPass(Registry);
initializeLocalizerPass(Registry);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index d0d973daa3cd4..a40e7f0610b40 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -32,10 +32,12 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/CodeGen/SwitchLoweringUtils.h"
@@ -47,6 +49,7 @@
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGenTypes/LowLevelType.h"
+#include "llvm/IR/Analysis.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/CFG.h"
#include "llvm/IR/Constant.h"
@@ -98,17 +101,17 @@ static cl::opt<bool>
EnableCSEInIRTranslator("enable-cse-in-irtranslator",
cl::desc("Should enable CSE in irtranslator"),
cl::Optional, cl::init(false));
-char IRTranslator::ID = 0;
+char IRTranslatorLegacy::ID = 0;
-INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
- false, false)
+INITIALIZE_PASS_BEGIN(IRTranslatorLegacy, DEBUG_TYPE,
+ "IRTranslator LLVM IR -> MI", false, false)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
INITIALIZE_PASS_DEPENDENCY(BlockFrequencyInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(StackProtector)
INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
-INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
- false, false)
+INITIALIZE_PASS_END(IRTranslatorLegacy, DEBUG_TYPE,
+ "IRTranslator LLVM IR -> MI", false, false)
static void reportTranslationError(MachineFunction &MF,
OptimizationRemarkEmitter &ORE,
@@ -128,8 +131,8 @@ static void reportTranslationError(MachineFunction &MF,
ORE.emit(R);
}
-IRTranslator::IRTranslator(CodeGenOptLevel optlevel)
- : MachineFunctionPass(ID), OptLevel(optlevel) {}
+IRTranslatorLegacy::IRTranslatorLegacy(CodeGenOptLevel OptLevel)
+ : MachineFunctionPass(ID), OptLevel(OptLevel) {}
#ifndef NDEBUG
namespace {
@@ -169,8 +172,7 @@ class DILocationVerifier : public GISelChangeObserver {
} // namespace
#endif // ifndef NDEBUG
-
-void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
+void IRTranslatorLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<StackProtector>();
AU.addRequired<TargetPassConfig>();
AU.addRequired<GISelCSEAnalysisWrapperPass>();
@@ -187,8 +189,8 @@ void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-IRTranslator::ValueToVRegInfo::VRegListT &
-IRTranslator::allocateVRegs(const Value &Val) {
+IRTranslatorImpl::ValueToVRegInfo::VRegListT &
+IRTranslatorImpl::allocateVRegs(const Value &Val) {
auto VRegsIt = VMap.findVRegs(Val);
if (VRegsIt != VMap.vregs_end())
return *VRegsIt->second;
@@ -202,7 +204,7 @@ IRTranslator::allocateVRegs(const Value &Val) {
return *Regs;
}
-ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
+ArrayRef<Register> IRTranslatorImpl::getOrCreateVRegs(const Value &Val) {
auto VRegsIt = VMap.findVRegs(Val);
if (VRegsIt != VMap.vregs_end())
return *VRegsIt->second;
@@ -258,7 +260,7 @@ ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
return *VRegs;
}
-int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
+int IRTranslatorImpl::getOrCreateFrameIndex(const AllocaInst &AI) {
auto [MapEntry, Inserted] = FrameIndices.try_emplace(&AI);
if (!Inserted)
return MapEntry->second;
@@ -284,7 +286,7 @@ int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
return FI;
}
-Align IRTranslator::getMemOpAlign(const Instruction &I) {
+Align IRTranslatorImpl::getMemOpAlign(const Instruction &I) {
if (const StoreInst *SI = dyn_cast<StoreInst>(&I))
return SI->getAlign();
if (const LoadInst *LI = dyn_cast<LoadInst>(&I))
@@ -300,19 +302,20 @@ Align IRTranslator::getMemOpAlign(const Instruction &I) {
return Align(1);
}
-MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
+MachineBasicBlock &IRTranslatorImpl::getMBB(const BasicBlock &BB) {
MachineBasicBlock *MBB = FuncInfo.getMBB(&BB);
assert(MBB && "BasicBlock was not encountered before");
return *MBB;
}
-void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
+void IRTranslatorImpl::addMachineCFGPred(CFGEdge Edge,
+ MachineBasicBlock *NewPred) {
assert(NewPred && "new predecessor must be a real MachineBasicBlock");
MachinePreds[Edge].push_back(NewPred);
}
-bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
- MachineIRBuilder &MIRBuilder) {
+bool IRTranslatorImpl::translateBinaryOp(unsigned Opcode, const User &U,
+ MachineIRBuilder &MIRBuilder) {
if (!mayTranslateUserTypes(U))
return false;
@@ -333,8 +336,8 @@ bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
return true;
}
-bool IRTranslator::translateUnaryOp(unsigned Opcode, const User &U,
- MachineIRBuilder &MIRBuilder) {
+bool IRTranslatorImpl::translateUnaryOp(unsigned Opcode, const User &U,
+ MachineIRBuilder &MIRBuilder) {
if (!mayTranslateUserTypes(U))
return false;
@@ -349,12 +352,13 @@ bool IRTranslator::translateUnaryOp(unsigned Opcode, const User &U,
return true;
}
-bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
+bool IRTranslatorImpl::translateFNeg(const User &U,
+ MachineIRBuilder &MIRBuilder) {
return translateUnaryOp(TargetOpcode::G_FNEG, U, MIRBuilder);
}
-bool IRTranslator::translateCompare(const User &U,
- MachineIRBuilder &MIRBuilder) {
+bool IRTranslatorImpl::translateCompare(const User &U,
+ MachineIRBuilder &MIRBuilder) {
if (!mayTranslateUserTypes(U))
return false;
@@ -378,7 +382,8 @@ bool IRTranslator::translateCompare(const User &U,
return true;
}
-bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
+bool IRTranslatorImpl::translateRet(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const ReturnInst &RI = cast<ReturnInst>(U);
const Value *Ret = RI.getReturnValue();
if (Ret && DL->getTypeStoreSize(Ret->getType()).isZero())
@@ -400,7 +405,7 @@ bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
return CLI->lowerReturn(MIRBuilder, Ret, VRegs, FuncInfo, SwiftErrorVReg);
}
-void IRTranslator::emitBranchForMergedCondition(
+void IRTranslatorImpl::emitBranchForMergedCondition(
const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB,
BranchProbability TProb, BranchProbability FProb, bool InvertCond) {
@@ -436,7 +441,7 @@ static bool isValInBlock(const Value *V, const BasicBlock *BB) {
return true;
}
-void IRTranslator::findMergedConditions(
+void IRTranslatorImpl::findMergedConditions(
const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB,
Instruction::BinaryOps Opc, BranchProbability TProb,
@@ -562,7 +567,7 @@ void IRTranslator::findMergedConditions(
}
}
-bool IRTranslator::shouldEmitAsBranches(
+bool IRTranslatorImpl::shouldEmitAsBranches(
const std::vector<SwitchCG::CaseBlock> &Cases) {
// For multiple cases, it's better to emit as branches.
if (Cases.size() != 2)
@@ -594,8 +599,8 @@ bool IRTranslator::shouldEmitAsBranches(
return true;
}
-bool IRTranslator::translateUncondBr(const User &U,
- MachineIRBuilder &MIRBuilder) {
+bool IRTranslatorImpl::translateUncondBr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const UncondBrInst &BrInst = cast<UncondBrInst>(U);
auto &CurMBB = MIRBuilder.getMBB();
auto *Succ0MBB = &getMBB(*BrInst.getSuccessor(0));
@@ -610,8 +615,8 @@ bool IRTranslator::translateUncondBr(const User &U,
return true;
}
-bool IRTranslator::translateCondBr(const User &U,
- MachineIRBuilder &MIRBuilder) {
+bool IRTranslatorImpl::translateCondBr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const CondBrInst &BrInst = cast<CondBrInst>(U);
auto &CurMBB = MIRBuilder.getMBB();
auto *Succ0MBB = &getMBB(*BrInst.getSuccessor(0));
@@ -687,9 +692,9 @@ bool IRTranslator::translateCondBr(const User &U,
return true;
}
-void IRTranslator::addSuccessorWithProb(MachineBasicBlock *Src,
- MachineBasicBlock *Dst,
- BranchProbability Prob) {
+void IRTranslatorImpl::addSuccessorWithProb(MachineBasicBlock *Src,
+ MachineBasicBlock *Dst,
+ BranchProbability Prob) {
if (!FuncInfo.BPI) {
Src->addSuccessorWithoutProb(Dst);
return;
@@ -700,8 +705,8 @@ void IRTranslator::addSuccessorWithProb(MachineBasicBlock *Src,
}
BranchProbability
-IRTranslator::getEdgeProbability(const MachineBasicBlock *Src,
- const MachineBasicBlock *Dst) const {
+IRTranslatorImpl::getEdgeProbability(const MachineBasicBlock *Src,
+ const MachineBasicBlock *Dst) const {
const BasicBlock *SrcBB = Src->getBasicBlock();
const BasicBlock *DstBB = Dst->getBasicBlock();
if (!FuncInfo.BPI) {
@@ -713,7 +718,7 @@ IRTranslator::getEdgeProbability(const MachineBasicBlock *Src,
return FuncInfo.BPI->getEdgeProbability(SrcBB, DstBB);
}
-bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) {
+bool IRTranslatorImpl::translateSwitch(const User &U, MachineIRBuilder &MIB) {
using namespace SwitchCG;
// Extract cases from the switch.
const SwitchInst &SI = cast<SwitchInst>(U);
@@ -793,10 +798,10 @@ bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) {
return true;
}
-void IRTranslator::splitWorkItem(SwitchCG::SwitchWorkList &WorkList,
- const SwitchCG::SwitchWorkListItem &W,
- Value *Cond, MachineBasicBlock *SwitchMBB,
- MachineIRBuilder &MIB) {
+void IRTranslatorImpl::splitWorkItem(SwitchCG::SwitchWorkList &WorkList,
+ const SwitchCG::SwitchWorkListItem &W,
+ Value *Cond, MachineBasicBlock *SwitchMBB,
+ MachineIRBuilder &MIB) {
using namespace SwitchCG;
assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
"Clusters not sorted?");
@@ -860,8 +865,8 @@ void IRTranslator::splitWorkItem(SwitchCG::SwitchWorkList &WorkList,
SL->SwitchCases.push_back(CB);
}
-void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
- MachineBasicBlock *MBB) {
+void IRTranslatorImpl::emitJumpTable(SwitchCG::JumpTable &JT,
+ MachineBasicBlock *MBB) {
// Emit the code for the jump table
assert(JT.Reg && "Should lower JT Header first!");
MachineIRBuilder MIB(*MBB->getParent());
@@ -875,9 +880,9 @@ void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
MIB.buildBrJT(Table.getReg(0), JT.JTI, JT.Reg);
}
-bool IRTranslator::emitJumpTableHeader(SwitchCG::JumpTable &JT,
- SwitchCG::JumpTableHeader &JTH,
- MachineBasicBlock *HeaderBB) {
+bool IRTranslatorImpl::emitJumpTableHeader(SwitchCG::JumpTable &JT,
+ SwitchCG::JumpTableHeader &JTH,
+ MachineBasicBlock *HeaderBB...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/216915
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