[llvm-branch-commits] [mlir] [mlir][ROCDL] Enable useStrictPropertiesInAssemblyFormat (PR #216813)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Aug 17 12:52:57 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir-gpu
Author: Krzysztof Drewniak (krzysz00)
<details>
<summary>Changes</summary>
**Migration note:** Separate out inherent and discardable attributes
on your `rocdl.*` operations and put a `<>` around the inherent ones.
This commit adds `prop-dict` clauses to all the ROCDL-dialect
operations that have inherent attributes but don't have better syntax
for them.
I looked at creating better syntaxes here, but these are fairly
low-level operations and it was hard to put together comma-separated
lists of optional arguments in tablegen. So I've gone with the rather
straightforward and consistent fix of adding in `prop-dict`s.
AI note: Claude did the changes here, I reviewed the designs.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@<!-- -->anthropic.com>
---
<sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
---
Patch is 81.78 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/216813.diff
10 Files Affected:
- (modified) mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td (+1)
- (modified) mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td (+37-37)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/dot-gfx11.mlir (+3-3)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/dot-gfx9.mlir (+3-3)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx11.mlir (+6-6)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx12.mlir (+6-6)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx1250.mlir (+1-1)
- (modified) mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir (+2-2)
- (modified) mlir/test/Dialect/LLVMIR/rocdl.mlir (+48-48)
- (modified) mlir/test/Target/LLVMIR/rocdl.mlir (+60-60)
``````````diff
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
index 0807cf8cf04a4..c4913ac62a214 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
@@ -18,6 +18,7 @@ include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
def ROCDL_Dialect : Dialect {
let name = "rocdl";
let cppNamespace = "::mlir::ROCDL";
+ let useStrictPropertiesInAssemblyFormat = 1;
let dependentDialects = ["LLVM::LLVMDialect"];
let summary = "Dialect for wrapping LLVM AMDGPU backend intrinsics and attributes";
let hasOperationAttrVerify = 1;
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index c7330dd36af94..4e17e5e229cbb 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -133,7 +133,7 @@ class ROCDL_MbcntOp<string mnemonic> :
let arguments = !con(args, baseArgs);
let results = (outs I32:$res);
let assemblyFormat = [{
- $in0 `,` $in1 attr-dict `:` `(` type($in0) `,` type($in1) `)` `->` type($res)
+ $in0 `,` $in1 prop-dict attr-dict `:` `(` type($in0) `,` type($in1) `)` `->` type($res)
}];
let description = [{
Masked bit count of threads below the current lane in a wavefront.
@@ -1060,7 +1060,7 @@ class ROCDL_WMMA_Opsel_IntrOp<string mnemonic, Type AB, Type CD> : ROCDL_IntrOp<
DefaultValuedAttr<I1Attr, "0">:$opsel)> {
let results = (outs LLVM_ScalarOrVectorOf<CD>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c attr-dict `:` functional-type(operands, $res)
+ $a `,` $b `,` $c prop-dict attr-dict `:` functional-type(operands, $res)
}];
let description = [{
Wave Matrix Multiply-Accumulate (WMMA) with output operand selection.
@@ -1068,7 +1068,7 @@ class ROCDL_WMMA_Opsel_IntrOp<string mnemonic, Type AB, Type CD> : ROCDL_IntrOp<
Example:
```mlir
// WMMA f16 with opsel control.
- %r = rocdl.wmma.f16.16x16x16.f16 %a, %b, %c {opsel = false} :
+ %r = rocdl.wmma.f16.16x16x16.f16 %a, %b, %c :
(vector<16xf16>, vector<16xf16>, vector<16xf16>) -> vector<16xf16>
```
}];
@@ -1085,7 +1085,7 @@ class ROCDL_WMMA_IU_IntrOp<string mnemonic, Type AB, Type CD> : ROCDL_IntrOp<mne
DefaultValuedAttr<I1Attr, "0">:$clamp)> {
let results = (outs LLVM_ScalarOrVectorOf<CD>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c attr-dict `:` functional-type(operands, $res)
+ $a `,` $b `,` $c prop-dict attr-dict `:` functional-type(operands, $res)
}];
let description = [{
Wave Matrix Multiply-Accumulate (WMMA) for integer types with
@@ -1115,7 +1115,7 @@ class ROCDL_WMMA_ModsAll_Reuse_IntrOp<string mnemonic, Type AB, Type CD> : ROCDL
DefaultValuedAttr<I1Attr, "0">:$reuseB)> {
let results = (outs LLVM_ScalarOrVectorOf<CD>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c `,` `modC` `=` $modC attr-dict `:`
+ $a `,` $b `,` $c `,` `modC` `=` $modC prop-dict attr-dict `:`
functional-type(operands, $res)
}];
let description = [{
@@ -1142,7 +1142,7 @@ class ROCDL_WMMA_ModsC_IntrOp<string mnemonic, Type AB, Type CD> : ROCDL_IntrOp<
DefaultValuedAttr<I1Attr, "0">:$reuseB)> {
let results = (outs LLVM_ScalarOrVectorOf<CD>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c `,` `modC` `=` $modC attr-dict `:`
+ $a `,` $b `,` $c `,` `modC` `=` $modC prop-dict attr-dict `:`
functional-type(operands, $res)
}];
let description = [{
@@ -1169,7 +1169,7 @@ class ROCDL_WMMA_ModsC_Diff_IntrOp<string mnemonic, Type AB, Type C, Type D> : R
DefaultValuedAttr<I1Attr, "0">:$reuseB)> {
let results = (outs LLVM_ScalarOrVectorOf<D>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c `,` `modC` `=` $modC attr-dict `:`
+ $a `,` $b `,` $c `,` `modC` `=` $modC prop-dict attr-dict `:`
functional-type(operands, $res)
}];
let description = [{
@@ -1197,7 +1197,7 @@ class ROCDL_WMMA_ModsABClamp_IntrOp<string mnemonic, Type AB, Type CD> : ROCDL_I
DefaultValuedAttr<I1Attr, "0">:$clamp)> {
let results = (outs LLVM_ScalarOrVectorOf<CD>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c attr-dict `:` functional-type(operands, $res)
+ $a `,` $b `,` $c prop-dict attr-dict `:` functional-type(operands, $res)
}];
let description = [{
Wave Matrix Multiply-Accumulate (WMMA) for integer types with
@@ -1248,7 +1248,7 @@ class ROCDL_WMMA_Scale_IntrOp<string mnemonic, Type AB, Type CD, Type ScaleExpTy
`modC` `=` $modC `,`
`scaleAType` `=` $scaleAType `,` `fmtScaleA` `=` $fmtScaleA `,`
`scaleBType` `=` $scaleBType `,` `fmtScaleB` `=` $fmtScaleB
- attr-dict `:` functional-type(operands, $res)
+ prop-dict attr-dict `:` functional-type(operands, $res)
}];
let description = [{
Scaled Wave Matrix Multiply-Accumulate (WMMA) with per-operand scaling.
@@ -1292,7 +1292,7 @@ class ROCDL_WMMA_Scale_F4_IntrOp<string mnemonic, Type AB, Type CD, Type ScaleEx
`modC` `=` $modC `,`
`scaleAType` `=` $scaleAType `,` `fmtScaleA` `=` $fmtScaleA `,`
`scaleBType` `=` $scaleBType `,` `fmtScaleB` `=` $fmtScaleB
- attr-dict `:` functional-type(operands, $res)
+ prop-dict attr-dict `:` functional-type(operands, $res)
}];
let description = [{
Scaled Wave Matrix Multiply-Accumulate (WMMA) for F4 format inputs.
@@ -1362,7 +1362,7 @@ class ROCDL_Dot_IntrOp<string mnemonic, ROCDL_NamedType A, ROCDL_NamedType B,
DefaultValuedAttr<I1Attr, "0">:$clamp)> {
let results = (outs C:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c attr-dict `:` functional-type(operands, $res)
+ $a `,` $b `,` $c prop-dict attr-dict `:` functional-type(operands, $res)
}];
let description = [{
Packed intra-lane dot-product with optional result clamping (`clamp`).
@@ -1412,7 +1412,7 @@ class ROCDL_Sudot_IntrOp<string mnemonic> :
DefaultValuedAttr<I1Attr, "0">:$clamp)> {
let results = (outs I32:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c attr-dict `:` functional-type(operands, $res)
+ $a `,` $b `,` $c prop-dict attr-dict `:` functional-type(operands, $res)
}];
let description = [{
Mixed-signedness packed dot-product with per-operand sign controls.
@@ -1512,7 +1512,7 @@ class ROCDL_SWMMAC_V1_Reuse_IntrOp<string mnemonic, Type A, Type B, Type CD> : R
)> {
let results = (outs LLVM_ScalarOrVectorOf<CD>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c `,` $index attr-dict `:` functional-type(operands, $res)
+ $a `,` $b `,` $c `,` $index prop-dict attr-dict `:` functional-type(operands, $res)
}];
}
@@ -1528,7 +1528,7 @@ class ROCDL_SWMMAC_IU_IntrOp<string mnemonic, Type AB, Type CD> : ROCDL_IntrOp<m
DefaultValuedAttr<I1Attr, "0">:$clamp)> {
let results = (outs LLVM_ScalarOrVectorOf<CD>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c `,` $index attr-dict `:` functional-type(operands, $res)
+ $a `,` $b `,` $c `,` $index prop-dict attr-dict `:` functional-type(operands, $res)
}];
}
@@ -1545,7 +1545,7 @@ class ROCDL_SWMMAC_ModsAB_IntrOp<string mnemonic, Type AB, Type C, Type D> : ROC
DefaultValuedAttr<I1Attr, "0">:$reuseB)> {
let results = (outs LLVM_ScalarOrVectorOf<D>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c `,` $index attr-dict `:` functional-type(operands, $res)
+ $a `,` $b `,` $c `,` $index prop-dict attr-dict `:` functional-type(operands, $res)
}];
}
@@ -1563,7 +1563,7 @@ class ROCDL_SWMMAC_ModsABClamp_IntrOp<string mnemonic, Type AB, Type C, Type D>
DefaultValuedAttr<I1Attr, "0">:$clamp)> {
let results = (outs LLVM_ScalarOrVectorOf<D>:$res);
let assemblyFormat = [{
- $a `,` $b `,` $c `,` $index attr-dict `:` functional-type(operands, $res)
+ $a `,` $b `,` $c `,` $index prop-dict attr-dict `:` functional-type(operands, $res)
}];
}
@@ -1604,7 +1604,7 @@ class ROCDL_LDS_Read_Tr_IntrOp<string mnemonic> :
ROCDL_IntrOp<mnemonic, [1], [], [], 1, 0, 1> {
dag args = (ins Arg<ROCDLBufferLDS, "", [MemRead]>:$ptr);
let arguments = !con(args, baseArgs);
- let assemblyFormat = "$ptr attr-dict `:` type($ptr) `->` type($res)";
+ let assemblyFormat = "$ptr prop-dict attr-dict `:` type($ptr) `->` type($res)";
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
return {getPtr()};
@@ -1666,7 +1666,7 @@ class ROCDL_TrLoadOp<ROCDL_TrLoadOpMeta meta> :
%3 = rocdl.ds.load.tr16.b128 %ptr : !llvm.ptr<3> -> vector<8xbf16>
```
}];
- let assemblyFormat = "$ptr attr-dict `:` qualified(type($ptr)) `->` type($res)";
+ let assemblyFormat = "$ptr prop-dict attr-dict `:` qualified(type($ptr)) `->` type($res)";
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
return {getPtr()};
@@ -1699,7 +1699,7 @@ def ROCDL_LoadToLDSOp :
let assemblyFormat = [{
$globalPtr `,` $ldsPtr `,` $size `,` $offset `,`
custom<CachePolicy>($aux)
- attr-dict `:` type($globalPtr)
+ prop-dict attr-dict `:` type($globalPtr)
}];
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
@@ -1719,7 +1719,7 @@ def ROCDL_LoadAsyncToLDSOp :
let assemblyFormat = [{
$globalPtr `,` $ldsPtr `,` $size `,` $offset `,`
custom<CachePolicy>($aux)
- attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
+ prop-dict attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
}];
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
@@ -1766,7 +1766,7 @@ def ROCDL_GlobalLoadLDSOp :
let assemblyFormat = [{
$globalPtr `,` $ldsPtr `,` $size `,` $offset `,`
custom<CachePolicy>($aux)
- attr-dict
+ prop-dict attr-dict
}];
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
@@ -1786,7 +1786,7 @@ def ROCDL_GlobalLoadAsyncLDSOp :
let assemblyFormat = [{
$globalPtr `,` $ldsPtr `,` $size `,` $offset `,`
custom<CachePolicy>($aux)
- attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
+ prop-dict attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
}];
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
@@ -1828,7 +1828,7 @@ foreach bitsVal = [8, 32, 64, 128] in {
let assemblyFormat = [{
$globalPtr `,` $ldsPtr `,` $offset `,`
custom<CachePolicy>($aux)
- attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
+ prop-dict attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
}];
let description = [{
Asynchronously loads }] # !cast<string>(bitsVal) # [{ bits of data from a global memory pointer
@@ -1867,7 +1867,7 @@ foreach bitsVal = [8, 32, 64, 128] in {
let assemblyFormat = [{
$globalPtr `,` $ldsPtr `,` $offset `,`
custom<CachePolicy>($aux)
- attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
+ prop-dict attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
}];
let description = [{
Asynchronously stores }] # !cast<string>(bitsVal) # [{ bits of data from a Local Data Share (LDS)
@@ -1903,7 +1903,7 @@ foreach bitsVal = [8, 32, 64, 128] in {
let assemblyFormat = [{
$globalPtr `,` $ldsPtr `,` $offset `,`
custom<CachePolicy>($cpol) `,` $mask
- attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
+ prop-dict attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
}];
let description = [{
Broadcasts memory load of }] # !cast<string>(bitsVal) # [{ bits of data for a cluster of workgroups.
@@ -1957,7 +1957,7 @@ class ROCDL_TensorLDSIntrOp<string mnemonic> :
}];
let assemblyFormat = [{
$dgroup0 `,` $dgroup1 `,` $dgroup2 `,` $dgroup3 `,` $dgroup4 `,`
- custom<CachePolicy>($cachePolicy) attr-dict
+ custom<CachePolicy>($cachePolicy) prop-dict attr-dict
`:` type($dgroup0) `,` type($dgroup1)
}];
let extraClassDefinition = [{
@@ -1995,7 +1995,7 @@ def ROCDL_RawPtrBufferLoadOp :
I32:$soffset,
ROCDL_DefaultCachePolicyAttr<ROCDL_NonAtomicBufferCachePolicyCompatAttr>:$aux);
let arguments = !con(args, baseArgs);
- let assemblyFormat = "$rsrc `,` $offset `,` $soffset `,` custom<CachePolicy>($aux) attr-dict `:` type($res)";
+ let assemblyFormat = "$rsrc `,` $offset `,` $soffset `,` custom<CachePolicy>($aux) prop-dict attr-dict `:` type($res)";
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
return {getRsrc()};
@@ -2009,7 +2009,7 @@ def ROCDL_PtrSBufferLoadOp :
I32:$offset,
ROCDL_DefaultCachePolicyAttr<ROCDL_NonAtomicBufferCachePolicyCompatAttr>:$aux);
let arguments = !con(args, baseArgs);
- let assemblyFormat = "$rsrc `,` $offset `,` custom<CachePolicy>($aux) attr-dict `:` type($res)";
+ let assemblyFormat = "$rsrc `,` $offset `,` custom<CachePolicy>($aux) prop-dict attr-dict `:` type($res)";
string llvmBuilder = baseLlvmBuilder # [{
llvm::MDNode *metadata = llvm::MDNode::get(inst->getContext(), {});
inst->setMetadata(llvm::LLVMContext::MD_invariant_load, metadata);
@@ -2031,7 +2031,7 @@ def ROCDL_RawPtrBufferLoadLdsOp :
I32:$offset,
ROCDL_DefaultCachePolicyAttr<ROCDL_NonAtomicBufferCachePolicyCompatAttr>:$aux);
let arguments = !con(args, baseArgs);
- let assemblyFormat = "$rsrc `,` $ldsPtr `,` $size `,` $voffset `,` $soffset `,` $offset `,` custom<CachePolicy>($aux) attr-dict";
+ let assemblyFormat = "$rsrc `,` $ldsPtr `,` $size `,` $voffset `,` $soffset `,` $offset `,` custom<CachePolicy>($aux) prop-dict attr-dict";
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
return {getRsrc(), getLdsPtr()};
@@ -2049,7 +2049,7 @@ def ROCDL_RawPtrBufferLoadAsyncLdsOp :
I32:$offset,
ROCDL_DefaultCachePolicyAttr<ROCDL_PreGfx12CachePolicyCompatAttr>:$aux);
let arguments = !con(args, baseArgs);
- let assemblyFormat = "$rsrc `,` $ldsPtr `,` $size `,` $voffset `,` $soffset `,` $offset `,` custom<CachePolicy>($aux) attr-dict";
+ let assemblyFormat = "$rsrc `,` $ldsPtr `,` $size `,` $voffset `,` $soffset `,` $offset `,` custom<CachePolicy>($aux) prop-dict attr-dict";
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
return {getRsrc(), getLdsPtr()};
@@ -2081,7 +2081,7 @@ def ROCDL_RawPtrBufferStoreOp :
I32:$soffset,
ROCDL_DefaultCachePolicyAttr<ROCDL_NonAtomicBufferCachePolicyCompatAttr>:$aux);
let arguments = !con(args, baseArgs);
- let assemblyFormat = "$vdata `,` $rsrc `,` $offset `,` $soffset `,` custom<CachePolicy>($aux) attr-dict `:` type($vdata)";
+ let assemblyFormat = "$vdata `,` $rsrc `,` $offset `,` $soffset `,` custom<CachePolicy>($aux) prop-dict attr-dict `:` type($vdata)";
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
return {getRsrc()};
@@ -2100,7 +2100,7 @@ def ROCDL_RawPtrBufferAtomicCmpSwap :
I32:$soffset,
ROCDL_DefaultCachePolicyAttr<ROCDL_AtomicBufferCachePolicyCompatAttr>:$aux);
let arguments = !con(args, baseArgs);
- let assemblyFormat = "$src `,` $cmp `,` $rsrc `,` $offset `,` $soffset `,` custom<CachePolicy>($aux) attr-dict `:` type($res)";
+ let assemblyFormat = "$src `,` $cmp `,` $rsrc `,` $offset `,` $soffset `,` custom<CachePolicy>($aux) prop-dict attr-dict `:` type($res)";
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
return {getRsrc()};
@@ -2117,7 +2117,7 @@ class ROCDL_RawPtrBufferAtomicRet<string op> :
I32:$soffset,
ROCDL_DefaultCachePolicyAttr<ROCDL_AtomicBufferCachePolicyCompatAttr>:$aux);
let arguments = !con(args, baseArgs);
- let assemblyFormat = "$vdata `,` $rsrc `,` $offset `,` $soffset `,` custom<CachePolicy>($aux) attr-dict `:` type($vdata)";
+ let assemblyFormat = "$vdata `,` $rsrc `,` $offset `,` $soffset `,` custom<CachePolicy>($aux) prop-dict attr-dict `:` type($vdata)";
let extraClassDefinition = [{
::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
return {getRsrc()};
@@ -2187,7 +2187,7 @@ def ROCDL_GlobalPrefetchOp :
```
}];
let results = (outs);
- let assemblyFormat = "$ptr `,` custom<CachePolicy>($cachePolicy) attr-dict `:` qualified(type($ptr))";
+ let assemblyFormat = "$ptr `,` custom<CachePolicy>($cachePolicy) prop-dict attr-dict `:` qualified(type($ptr))";
let extraClassDefinition = [{
SmallVector<Value> $cppClass::getAccessedOperands() {
return {getPtr()};
@@ -2211,7 +2211,7 @@ def ROCDL_FlatPrefetchOp :
```
}];
let results = (outs);
- let assemblyFormat = "$ptr `,` custom<CachePolicy>($cachePolicy) attr-dict `:` qualified(type($ptr))";
+ let assemblyFormat = "$ptr `,` custom<CachePolicy>($cachePolicy) prop-dict attr-dict `:` qualified(type($ptr))";
let extraClassDefinition = [{
SmallVector<Value> $cppClass::getAccessedOperands() {
return {getPtr()};
@@ -2241,7 +2241,7 @@ def ROCDL_DsAtomicBarrierArriveRtnOp :
```
}];
let results = (outs I64:$res);
- let assemblyFormat = "$barrierPtr `,` $val attr-dict `:` qualified(type($barrierPtr)) `,` type($val) `->` type($res)";
+ let assemblyFormat = "$barrierPtr `,` $val prop-dict attr-dict `:` qualified(type($barrierPtr)) `,` type($val) `->` type($res)";
let extraClassDefinition = [{
SmallVector<Value> $cppClass::getAccessedOperands() {
return {getBarrierPtr()};
@@ -2265,7 +2265,7 @@ def ROCDL_DsAtomicAsyncBarrierArriveOp :
```
}];
let results = (outs);
- let assemblyFormat = "$barrierPtr attr-dict `:` qualified(type($barrierPtr))";
+ let assemblyFormat = "$barrierPtr prop-dict attr-dict `:` qualified(type($barrierPtr))";
let extraClassDefinition = [{
SmallVector<Value> $cppClass::getAccessedOperands() {
return {getBarrierPtr()};
diff --git a/mlir/test/Conversion/AMDGPUToROCDL/dot-gfx11.mlir b/mlir/test/Conversion/AMDGPUToROCDL/dot-gfx11.mlir
index 9985e9cf66540..02d8525e15977 100644
--- a/mlir/test/Conversion/AMDGPUToROCDL/dot-gfx11.mlir
+++ b/mlir/test/Conversion/AMDGPUToROCDL/dot-gfx11.mlir
@@ -32,21 +32,21 @@ func.func @dot_sdot4_gfx11_uniform_sign(%a: vector<4xi8>, %b: vector<4xi8>, %c:
// CHECK-LABEL: @dot_sudot4_signA_unsignedB
func.func @dot_sudot4_signA_unsignedB(%a: vector<4xi8>, %b: vector<4xi8>, %c: i32) -> i32 {
- // CHECK: rocdl.sudot4 %{{.+}}, %{{.+}}, %{{.+}} {signA = true} : (i32, i32, i32) -> i32
+ // CHECK: rocdl.sudot4 %{{.+}}, %{{.+}}, %{{.+}} <{signA = true}> : (i32, i32, i32) -> i32
%r = amdgpu.dot %a * %b + %c unsignedB : vector<4xi8>, vector<4xi8>, i32
func.return %r : i32
}
// CHECK-LABEL: @dot_sudot4_unsignedA_signB_clamp
func.func @dot_sudot4_unsignedA_signB_clamp(%a: vector<4xi8>, %b: vector<4xi8>, %c: i32) -> i32 {
- // CHECK: rocdl.sudot4 %{{.+}}, %{{.+}}, %{{.+}} {clamp = true, signB = true} : (i32, i32, i32) -> i32
+ // CHECK: rocdl.sudot4 %{{.+}}, %{{.+}}, %{{.+}} <{clamp = true, signB = true}> : (i32, i32, i32) -> i32
%r = amdgpu.dot %a * %b + %c unsignedA clamp : vector<4xi8>, vector<4xi8>, i32
func.return %r : i32
}
// CHECK-LABEL: @dot_sudot8
func.func @dot_sudot8(%a: vector<8xi4>, %b: vector<8xi4>, %c: i32) -> i32 {
- // CHECK: rocdl.sudot8 %{{.+}}, %{{.+}}, %{{.+}} {signA = true} : (i32, i32, i32) -> i32
+ // CHECK: rocdl.sudot8 %{{.+}}, %{{.+}}, %{{.+}} <{signA = true}> : (i32, i32, i32) -> i32
%r = amdgpu.dot %a * %b + %c unsignedB : vector<8xi4>, vector<8xi4>, i32
func.return %r : i32
}
diff --git a/mlir/test/Conversion/AMDGPUToROCDL/dot-gfx9.mlir b/mlir/test/Conversion/AMDGPUToROCDL/dot-gfx9.mlir
index f0897e9423649..d2c5b26a8d50d 100644
--- a/mlir/test/Conversion/AMDGPUToROCDL/dot-gfx9.mlir
+++ b/mlir/test/Conversion/AMDGPUToROCDL/dot-gfx9.mlir
@@ -9,7 +9,7 @@ func.fu...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/216813
More information about the llvm-branch-commits
mailing list