[llvm-branch-commits] [mlir] [mlir][AMDGPU] Enable useStrictPropertiesInAssemblyFormat (PR #216812)
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llvm-branch-commits at lists.llvm.org
Mon Aug 17 12:52:28 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-mlir-gpu
Author: Krzysztof Drewniak (krzysz00)
<details>
<summary>Changes</summary>
This is part of the migration to keeping inherent and discardable
attributes separate touched.
**Migration note:** this'll change the syntax of a bunch of `amdgpu`
dialect ops to keep inherent attributes out of the `attr-dict`.
Syntax changes:
1. Operations like the dpp operations have had their inherent operands
turned into oilists that use `name(value)` syntax, such as
`bound_ctrl(false)`, which also leads to the elision of default
values.
2. Buffer operations now use `boundsCheck(true/false)` before the main
operation (keeping the visibility from the old attr-dict) and have
moved to `sgprOffset(%offset)` and `indexOffset(constant)` as optional
syntax alements after the main specification.
3. WMMA operations also now have the same `attribute[(value)]` element
lists, no it's now `subwordOffset(1) unsignedA` and not
`{subwordOffset = 1 : i32, unsignedA}`.
4. MFMAs have received a similar update, which included unifying the
syntax for `blgp` to `blgp(value)` and making it properly optional.
The one attribute that isn't part of a string of modifier keywords is
`blocks` (the number of blocks if the MFMA carries out more than 1),
which is now `blocks(2/4/8)` before the MxNxK portion of the operation.
5. `amdgpu.scaled_wmma` now has `a_first_scale_lane = L` and
`b_first_scale_lane = L` as required syntax elements (so in most
cases you just need to drop the `{}` around them).
AI disclosure: Claude made these changes, I made sure the plan was
reasonable and made the syntax choices.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@<!-- -->anthropic.com>
---
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---
Patch is 171.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/216812.diff
24 Files Affected:
- (modified) mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td (+1)
- (modified) mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td (+69-20)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir (+25-25)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/dot-gfx11.mlir (+3-3)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/dot-gfx9.mlir (+4-4)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/dot-invalid.mlir (+1-1)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/dpp.mlir (+12-12)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir (+18-18)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir (+39-39)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/permlane-var.mlir (+3-3)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/permlane.mlir (+1-1)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma-gfx950.mlir (+16-16)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma.mlir (+14-14)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/swmmac-gfx12.mlir (+14-14)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/swmmac-gfx1250.mlir (+13-13)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx11.mlir (+12-12)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx12.mlir (+6-6)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx1250.mlir (+17-17)
- (modified) mlir/test/Dialect/AMDGPU/amdgpu-emulate-atomics.mlir (+20-20)
- (modified) mlir/test/Dialect/AMDGPU/canonicalize.mlir (+12-12)
- (modified) mlir/test/Dialect/AMDGPU/invalid.mlir (+32-32)
- (modified) mlir/test/Dialect/AMDGPU/ops.mlir (+59-59)
- (modified) mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir (+16-16)
- (modified) mlir/test/Integration/GPU/ROCM/vector-transferops.mlir (+4-4)
``````````diff
diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td
index 639dbf6b4a128..8dc4b3a81c334 100644
--- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td
+++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td
@@ -14,6 +14,7 @@ include "mlir/IR/DialectBase.td"
def AMDGPU_Dialect : Dialect {
let name = "amdgpu";
let cppNamespace = "::mlir::amdgpu";
+ let useStrictPropertiesInAssemblyFormat = 1;
let description = [{
The `AMDGPU` dialect provides wrappers around AMD-specific functionality
and LLVM intrinsics. These wrappers should be used in conjunction with
diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
index 69a9adf3be8af..12868dd2fbc7f 100644
--- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
+++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
@@ -409,8 +409,10 @@ def AMDGPU_RawBufferLoadOp :
- The cache coherency bits are off
}];
let assemblyFormat = [{
+ `boundsCheck` `(` $boundsCheck `)`
attr-dict $memref `[` $indices `]`
- (`sgprOffset` $sgprOffset^)? `:`
+ (`indexOffset` `(` $indexOffset^ `)`)?
+ (`sgprOffset` `(` $sgprOffset^ `)`)? `:`
type($memref) (`,` type($indices)^)? `->` type($value)
}];
let hasCanonicalizer = 1;
@@ -448,8 +450,10 @@ def AMDGPU_RawBufferStoreOp :
instruction is constructed.
}];
let assemblyFormat = [{
+ `boundsCheck` `(` $boundsCheck `)`
attr-dict $value `->` $memref `[` $indices `]`
- (`sgprOffset` $sgprOffset^)? `:`
+ (`indexOffset` `(` $indexOffset^ `)`)?
+ (`sgprOffset` `(` $sgprOffset^ `)`)? `:`
type($value) `->` type($memref) (`,` type($indices)^)?
}];
let hasCanonicalizer = 1;
@@ -490,8 +494,10 @@ def AMDGPU_RawBufferAtomicCmpswapOp :
instruction is constructed.
}];
let assemblyFormat = [{
+ `boundsCheck` `(` $boundsCheck `)`
attr-dict $src `,` $cmp `->` $memref `[` $indices `]`
- (`sgprOffset` $sgprOffset^)? `:`
+ (`indexOffset` `(` $indexOffset^ `)`)?
+ (`sgprOffset` `(` $sgprOffset^ `)`)? `:`
type($value) `->` type($memref) `,` type($indices)
}];
let hasCanonicalizer = 1;
@@ -532,8 +538,10 @@ def AMDGPU_RawBufferAtomicFaddOp :
instruction is constructed.
}];
let assemblyFormat = [{
+ `boundsCheck` `(` $boundsCheck `)`
attr-dict $value `->` $memref `[` $indices `]`
- (`sgprOffset` $sgprOffset^)? `:`
+ (`indexOffset` `(` $indexOffset^ `)`)?
+ (`sgprOffset` `(` $sgprOffset^ `)`)? `:`
type($value) `->` type($memref) `,` type($indices)
}];
let hasCanonicalizer = 1;
@@ -574,8 +582,10 @@ def AMDGPU_RawBufferAtomicFmaxOp :
instruction is constructed.
}];
let assemblyFormat = [{
+ `boundsCheck` `(` $boundsCheck `)`
attr-dict $value `->` $memref `[` $indices `]`
- (`sgprOffset` $sgprOffset^)? `:`
+ (`indexOffset` `(` $indexOffset^ `)`)?
+ (`sgprOffset` `(` $sgprOffset^ `)`)? `:`
type($value) `->` type($memref) `,` type($indices)
}];
let hasCanonicalizer = 1;
@@ -615,8 +625,10 @@ def AMDGPU_RawBufferAtomicSmaxOp :
instruction is constructed.
}];
let assemblyFormat = [{
+ `boundsCheck` `(` $boundsCheck `)`
attr-dict $value `->` $memref `[` $indices `]`
- (`sgprOffset` $sgprOffset^)? `:`
+ (`indexOffset` `(` $indexOffset^ `)`)?
+ (`sgprOffset` `(` $sgprOffset^ `)`)? `:`
type($value) `->` type($memref) `,` type($indices)
}];
let hasCanonicalizer = 1;
@@ -656,8 +668,10 @@ def AMDGPU_RawBufferAtomicUminOp :
instruction is constructed.
}];
let assemblyFormat = [{
+ `boundsCheck` `(` $boundsCheck `)`
attr-dict $value `->` $memref `[` $indices `]`
- (`sgprOffset` $sgprOffset^)? `:`
+ (`indexOffset` `(` $indexOffset^ `)`)?
+ (`sgprOffset` `(` $sgprOffset^ `)`)? `:`
type($value) `->` type($memref) `,` type($indices)
}];
let hasCanonicalizer = 1;
@@ -770,7 +784,11 @@ def AMDGPU_DPPOp : AMDGPU_Op<"dpp",
}];
let results = (outs AnyType:$result);
let assemblyFormat = [{
- $old $src $kind (`(` $permArgument^ `)`)? attr-dict `:` type($result)
+ $old $src $kind (`(` $permArgument^ `)`)?
+ oilist (`row_mask` `(` $row_mask `)`
+ | `bank_mask` `(` $bank_mask `)`
+ | `bound_ctrl` `(` $bound_ctrl `)`)
+ attr-dict `:` type($result)
}];
let hasVerifier = 1;
}
@@ -811,7 +829,7 @@ def AMDGPU_PermlaneSwapOp : AMDGPU_Op<"permlane_swap", [Pure, AllTypesMatch<["re
Example:
```mlir
%0 = amdgpu.permlane_swap %src 16 : f16
- %1 = amdgpu.permlane_swap %src 32 { fetch_inactive = true, bound_ctrl = true } : f16
+ %1 = amdgpu.permlane_swap %src 32 fetch_inactive(true) bound_ctrl(true) : f16
```
Operands:
@@ -833,7 +851,10 @@ def AMDGPU_PermlaneSwapOp : AMDGPU_Op<"permlane_swap", [Pure, AllTypesMatch<["re
DefaultValuedAttr<BoolAttr, "false">:$bound_ctrl);
let results = (outs AnyIntegerOrFloatOr1DVector:$result);
let assemblyFormat = [{
- $src $row_length attr-dict `:` type($result)
+ $src $row_length
+ oilist (`fetch_inactive` `(` $fetch_inactive `)`
+ | `bound_ctrl` `(` $bound_ctrl `)`)
+ attr-dict `:` type($result)
}];
let hasVerifier = 1;
}
@@ -858,8 +879,8 @@ def AMDGPU_PermlaneVarOp : AMDGPU_Op<"permlane_var",
Example:
```mlir
- %0 = amdgpu.permlane_var %src, %sel { cross = false } : f16
- %1 = amdgpu.permlane_var %src, %sel { cross = true } : f32
+ %0 = amdgpu.permlane_var %src, %sel : f16
+ %1 = amdgpu.permlane_var %src, %sel cross(true) : f32
```
Note: Lowering is only supported on GFX12+.
@@ -871,7 +892,11 @@ def AMDGPU_PermlaneVarOp : AMDGPU_Op<"permlane_var",
DefaultValuedAttr<BoolAttr, "false">:$bound_ctrl);
let results = (outs AnyIntegerOrFloatOr1DVector:$result);
let assemblyFormat = [{
- $src `,` $selector attr-dict `:` type($result)
+ $src `,` $selector
+ oilist (`cross` `(` $cross `)`
+ | `fetch_inactive` `(` $fetch_inactive `)`
+ | `bound_ctrl` `(` $bound_ctrl `)`)
+ attr-dict `:` type($result)
}];
}
@@ -1067,15 +1092,22 @@ def AMDGPU_MFMAOp :
%0 = amdgpu.mfma 16x16x16 %matA * %matB + %matC
: vector<4xf16>, vector<4xf16>, vector<4xf32>
- %1 = amdgpu.mfma 32x32x1 %matD * %matE + %matF
- { abid = 1 : i32, cbsz = 1 : i32, blocks = 2 : i32 }
- blgp = bcast_second_32 : f32, f32, vector<32xf32>
+ %1 = amdgpu.mfma blocks(2) 32x32x1 %matD * %matE + %matF
+ abid(1) blgp(bcast_second_32) cbsz(1)
+ : f32, f32, vector<32xf32>
```
}];
let assemblyFormat = [{
+ (`blocks` `(` $blocks^ `)`)?
custom<MNKDimensionList>($m, $n, $k) $sourceA `*` $sourceB `+` $destC
+ oilist (`abid` `(` $abid `)`
+ | `blgp` `(` $blgp `)`
+ | `cbsz` `(` $cbsz `)`
+ | `reducePrecision` $reducePrecision
+ | `negateA` $negateA
+ | `negateB` $negateB
+ | `negateC` $negateC)
attr-dict
- `blgp` `=` $blgp
`:` type($sourceA) `,` type($sourceB) `,` type($destC)
}];
let hasVerifier = 1;
@@ -1136,6 +1168,10 @@ def AMDGPU_WMMAOp :
}];
let assemblyFormat = [{
custom<MNKDimensionList>($m, $n, $k) $sourceA `*` $sourceB `+` $destC
+ oilist (`subwordOffset` `(` $subwordOffset `)`
+ | `unsignedA` $unsignedA
+ | `unsignedB` $unsignedB
+ | `clamp` $clamp)
attr-dict
`:` type($sourceA) `,` type($sourceB) `,` type($destC)
}];
@@ -1182,9 +1218,9 @@ def AMDGPU_DotOp :
Example:
```mlir
%r0 = amdgpu.dot %a * %b + %c : vector<4xi8>, vector<4xi8>, i32
- %r1 = amdgpu.dot %a * %b + %c {unsignedA, unsignedB, clamp}
+ %r1 = amdgpu.dot %a * %b + %c unsignedA unsignedB clamp
: vector<8xi4>, vector<8xi4>, i32
- %r2 = amdgpu.dot %a * %b + %c {unsignedB}
+ %r2 = amdgpu.dot %a * %b + %c unsignedB
: vector<4xi8>, vector<4xi8>, i32
%r3 = amdgpu.dot %a * %b + %c : vector<2xf16>, vector<2xf16>, f32
%r4 = amdgpu.dot %a * %b + %c : vector<2xf16>, vector<2xf16>, f16
@@ -1193,7 +1229,11 @@ def AMDGPU_DotOp :
```
}];
let assemblyFormat = [{
- $sourceA `*` $sourceB `+` $destC attr-dict
+ $sourceA `*` $sourceB `+` $destC
+ oilist (`unsignedA` $unsignedA
+ | `unsignedB` $unsignedB
+ | `clamp` $clamp)
+ attr-dict
`:` type($sourceA) `,` type($sourceB) `,` type($destC)
}];
let hasVerifier = 1;
@@ -1266,6 +1306,7 @@ def AMDGPU_SparseMFMAOp :
let assemblyFormat = [{
custom<MNKDimensionList>($m, $n, $k) $sourceA `*` $sourceB `+` $destC
`sparse` `(` $sparseIdx `:` type($sparseIdx) `)`
+ oilist (`abid` `(` $abid `)` | `cbsz` `(` $cbsz `)`)
attr-dict
`:` type($sourceA) `,` type($sourceB) `,` type($destC)
}];
@@ -1362,6 +1403,12 @@ def AMDGPU_SparseWMMAOp :
let assemblyFormat = [{
custom<MNKDimensionList>($m, $n, $k) $sourceA `*` $sourceB `+` $destC
`sparse` `(` $sparseIdx `:` type($sparseIdx) `)`
+ oilist (`unsignedA` $unsignedA
+ | `unsignedB` $unsignedB
+ | `reuseA` $reuseA
+ | `reuseB` $reuseB
+ | `clamp` $clamp
+ | `wave64` $wave64)
attr-dict
`:` type($sourceA) `,` type($sourceB) `,` type($destC)
}];
@@ -1693,6 +1740,8 @@ def AMDGPU_ScaledWMMAOp
custom<MNKDimensionList>($m, $n, $k) ` `
`(` $scaleA `*` $sourceA `)` `*`
`(` $scaleB `*` $sourceB `)` `+` $destC
+ `a_first_scale_lane` `=` $a_first_scale_lane
+ `b_first_scale_lane` `=` $b_first_scale_lane
attr-dict
`:` type($scaleA) `,` type($sourceA) `,` type($scaleB) `,` type($sourceB) `,` type($destC)
}];
diff --git a/mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir b/mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
index 48e42088d6b67..c945bbf410c3f 100644
--- a/mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
+++ b/mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
@@ -170,7 +170,7 @@ func.func @gpu_gcn_raw_buffer_load_scalar_i32(%buf: memref<i32>) -> i32 {
// RECORDS45: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %[[stride]], %[[numRecords]], %[[flags]] : !llvm.ptr, i64 to <8>
// CHECK: %[[ret:.*]] = rocdl.raw.ptr.buffer.load %[[resource]], %{{.*}}, %{{.*}}, 0 : i32
// CHECK: return %[[ret]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[] : memref<i32> -> i32
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[] : memref<i32> -> i32
func.return %0 : i32
}
@@ -186,7 +186,7 @@ func.func @gpu_gcn_raw_buffer_load_i32(%buf: memref<64xi32>, %idx: i32) -> i32 {
// RECORDS45: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %[[stride]], %[[numRecords]], %[[flags]] : !llvm.ptr, i64 to <8>
// CHECK: %[[ret:.*]] = rocdl.raw.ptr.buffer.load %[[resource]], %{{.*}}, %{{.*}}, 0 : i32
// CHECK: return %[[ret]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[%idx] : memref<64xi32>, i32 -> i32
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[%idx] : memref<64xi32>, i32 -> i32
func.return %0 : i32
}
@@ -225,7 +225,7 @@ func.func @gpu_gcn_raw_buffer_load_i32_strided(%buf: memref<16x16xi32, strided<[
// CHECK: %[[sgpr_off:.*]] = llvm.mul %[[zero_0]], %[[elem_size]] : i32
// CHECK: %[[v:.*]] = rocdl.raw.ptr.buffer.load %[[rsrc]], %[[vgpr_off]], %[[sgpr_off]], 0 : i32
// CHECK: return %[[v]] : i32
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[%i, %j] : memref<16x16xi32, strided<[?, ?], offset: ?>>, i32, i32 -> i32
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[%i, %j] : memref<16x16xi32, strided<[?, ?], offset: ?>>, i32, i32 -> i32
func.return %0 : i32
}
@@ -241,7 +241,7 @@ func.func @gpu_gcn_raw_buffer_load_i32_oob_off(%buf: memref<64xi32>, %idx: i32)
// RECORDS45: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %{{.*}}, %[[numRecords]], %[[flags]] : !llvm.ptr, i64 to <8>
// CHECK: %[[ret:.*]] = rocdl.raw.ptr.buffer.load %[[resource]], %{{.*}}, %{{.*}}, 0 : i32
// CHECK: return %[[ret]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = false} %buf[%idx] : memref<64xi32>, i32 -> i32
+ %0 = amdgpu.raw_buffer_load boundsCheck(false) %buf[%idx] : memref<64xi32>, i32 -> i32
func.return %0 : i32
}
@@ -250,7 +250,7 @@ func.func @gpu_gcn_raw_buffer_load_1xi32(%buf: memref<64xi32>, %idx: i32) -> vec
// CHECK: %[[ret:.*]] = rocdl.raw.ptr.buffer.load %{{.*}}, %{{.*}}, %{{.*}}, 0 : i32
// CHECK: %[[cast:.*]] = llvm.bitcast %[[ret]] : i32 to vector<1xi32>
// CHECK: return %[[cast]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[%idx] : memref<64xi32>, i32 -> vector<1xi32>
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[%idx] : memref<64xi32>, i32 -> vector<1xi32>
func.return %0 : vector<1xi32>
}
@@ -258,7 +258,7 @@ func.func @gpu_gcn_raw_buffer_load_1xi32(%buf: memref<64xi32>, %idx: i32) -> vec
func.func @gpu_gcn_raw_buffer_load_2xi32(%buf: memref<64xi32>, %idx: i32) -> vector<2xi32> {
// CHECK: %[[ret:.*]] = rocdl.raw.ptr.buffer.load %{{.*}}, %{{.*}}, %{{.*}}, 0 : vector<2xi32>
// CHECK: return %[[ret]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[%idx] : memref<64xi32>, i32 -> vector<2xi32>
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[%idx] : memref<64xi32>, i32 -> vector<2xi32>
func.return %0 : vector<2xi32>
}
@@ -270,7 +270,7 @@ func.func @gpu_gcn_raw_buffer_load_i8(%buf: memref<64xi8>, %idx: i32) -> i8 {
// RECORDS45: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %{{.*}}, %[[numRecords]], %{{.*}} : !llvm.ptr, i64 to <8>
// CHECK: %[[ret:.*]] = rocdl.raw.ptr.buffer.load %[[resource]], %{{.*}}, %{{.*}}, 0 : i8
// CHECK: return %[[ret]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[%idx] : memref<64xi8>, i32 -> i8
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[%idx] : memref<64xi8>, i32 -> i8
func.return %0 : i8
}
@@ -283,7 +283,7 @@ func.func @gpu_gcn_raw_buffer_load_2xi8(%buf: memref<64xi8>, %idx: i32) -> vecto
// CHECK: %[[loaded:.*]] = rocdl.raw.ptr.buffer.load %[[resource]], %{{.*}}, %{{.*}}, 0 : i16
// CHECK: %[[ret:.*]] = llvm.bitcast %[[loaded]] : i16 to vector<2xi8>
// CHECK: return %[[ret]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[%idx] : memref<64xi8>, i32 -> vector<2xi8>
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[%idx] : memref<64xi8>, i32 -> vector<2xi8>
func.return %0 : vector<2xi8>
}
@@ -292,7 +292,7 @@ func.func @gpu_gcn_raw_buffer_load_16xi8(%buf: memref<64xi8>, %idx: i32) -> vect
// CHECK: %[[loaded:.*]] = rocdl.raw.ptr.buffer.load %{{.*}}, %{{.*}}, %{{.*}}, 0 : vector<4xi32>
// CHECK: %[[ret:.*]] = llvm.bitcast %[[loaded]] : vector<4xi32> to vector<16xi8>
// CHECK: return %[[ret]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[%idx] : memref<64xi8>, i32 -> vector<16xi8>
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[%idx] : memref<64xi8>, i32 -> vector<16xi8>
func.return %0 : vector<16xi8>
}
@@ -305,7 +305,7 @@ func.func @gpu_gcn_raw_buffer_load_f8E5M2FNUZ(%buf: memref<64xf8E5M2FNUZ>, %idx:
// CHECK: %[[loaded:.*]] = rocdl.raw.ptr.buffer.load %[[resource]], %{{.*}}, %{{.*}}, 0 : i8
// CHECK: %[[ret:.*]] = builtin.unrealized_conversion_cast %[[loaded]] : i8 to f8E5M2FNUZ
// CHECK: return %[[ret]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[%idx] : memref<64xf8E5M2FNUZ>, i32 -> f8E5M2FNUZ
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[%idx] : memref<64xf8E5M2FNUZ>, i32 -> f8E5M2FNUZ
func.return %0 : f8E5M2FNUZ
}
@@ -319,7 +319,7 @@ func.func @gpu_gcn_raw_buffer_load_4xf8E4M3FNUZ(%buf: memref<64xf8E4M3FNUZ>, %id
// CHECK: %[[cast:.*]] = llvm.bitcast %[[loaded]] : i32 to vector<4xi8>
// CHECK: %[[ret:.*]] = builtin.unrealized_conversion_cast %[[cast]] : vector<4xi8> to vector<4xf8E4M3FNUZ>
// CHECK: return %[[ret]]
- %0 = amdgpu.raw_buffer_load {boundsCheck = true} %buf[%idx] : memref<64xf8E4M3FNUZ>, i32 -> vector<4xf8E4M3FNUZ>
+ %0 = amdgpu.raw_buffer_load boundsCheck(true) %buf[%idx] : memref<64xf8E4M3FNUZ>, i32 -> vector<4xf8E4M3FNUZ>
func.return %0 : vector<4xf8E4M3FNUZ>
}
@@ -334,7 +334,7 @@ func.func @gpu_gcn_raw_buffer_store_scalar_i32(%value: i32, %buf: memref<i32>) {
// RECORDS32: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %{{.*}}, %[[numRecords32]], %[[flags]] : !llvm.ptr, i32 to <8>
// RECORDS45: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %{{.*}}, %[[numRecords]], %[[flags]] : !llvm.ptr, i64 to <8>
// CHECK: rocdl.raw.ptr.buffer.store %{{.*}}, %[[resource]], %{{.*}}, %{{.*}}, 0 : i32
- amdgpu.raw_buffer_store {boundsCheck = true} %value -> %buf[] : i32 -> memref<i32>
+ amdgpu.raw_buffer_store boundsCheck(true) %value -> %buf[] : i32 -> memref<i32>
func.return
}
@@ -348,7 +348,7 @@ func.func @gpu_gcn_raw_buffer_store_i32(%value: i32, %buf: memref<64xi32>, %idx:
// RECORDS32: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %{{.*}}, %[[numRecords32]], %[[flags]] : !llvm.ptr, i32 to <8>
// RECORDS45: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %{{.*}}, %[[numRecords]], %[[flags]] : !llvm.ptr, i64 to <8>
// CHECK: rocdl.raw.ptr.buffer.store %{{.*}}, %[[resource]], %{{.*}}, %{{.*}}, 0 : i32
- amdgpu.raw_buffer_store {boundsCheck = true} %value -> %buf[%idx] : i32 -> memref<64xi32>, i32
+ amdgpu.raw_buffer_store boundsCheck(true) %value -> %buf[%idx] : i32 -> memref<64xi32>, i32
func.return
}
@@ -356,7 +356,7 @@ func.func @gpu_gcn_raw_buffer_store_i32(%value: i32, %buf: memref<64xi32>, %idx:
func.func @gpu_gcn_raw_buffer_store_1xf32(%value: vector<1xf32>, %buf: memref<64xf32>, %idx: i32) {
// CHECK: %[[cast:.*]] = llvm.bitcast %{{.*}} : vector<1xf32> to f32
// CHECK: rocdl.raw.ptr.buffer.store %[[cast]], %{{.*}}, %{{.*}}, %{{.*}}, 0 : f32
- amdgpu.raw_buffer_store {boundsCheck = true} %value -> %buf[%idx] : vector<1xf32> -> memref<64xf32>, i32
+ amdgpu.raw_buffer_store boundsCheck(true) %value -> %buf[%idx] : vector<1xf32> -> memref<64xf32>, i32
func.return
}
@@ -364,7 +364,7 @@ func.func @gpu_gcn_raw_buffer_store_1xf32(%value: vector<1xf32>, %buf: memref<64
func.func @gpu_gcn_raw_buffer_store_2xi8(%value: vector<2xi8>, %buf: memref<64xi8>, %idx: i32) {
// CHECK: %[[cast:.*]] = llvm.bitcast %{{.*}} : vector<2xi8> to i16
// CHECK: rocdl.raw.ptr.buffer.store %[[cast]], %{{.*}}, %{{.*}}, %{{.*}}, 0 : i16
- amdgpu.raw_buffer_store {boundsCheck = true} %value -> %buf[%idx] : vector<2xi8> -> memref<64xi8>, i32
+ amdgpu.raw_buffer_store boundsCheck(true) %value -> %buf[%idx] : vector<2xi8> -> memref<64xi8>, i32
func.return
}
@@ -372,7 +372,7 @@ func.func @gpu_gcn_raw_buffer_store_2xi8(%value: vector<2xi8>, %buf: memref<64xi
func.func @gpu_gcn_raw_buffer_store_16xi8(%value: vector<16xi8>, %buf: memref<64xi8>, %idx: i32) {
// CHECK: %[[cast:.*]] = llvm.bitcast %{{.*}} : vector<16xi8> to vector<4xi32>
// CHECK: rocdl.raw.ptr.buffer.store %[[cast]], %{{.*}}, %{{.*}}, %{{.*}}, 0 : vector<4xi32>
- amdgpu.raw_buffer_store {boundsCheck = true} %value -> %buf[%idx] : vector<16xi8> -> memref<64xi8>, i32
+ amdgpu.raw_buffer_store boundsCheck(true) %value -> %buf[%idx] : vector<16xi8> -> memref<64xi8>, i32
func.return
}
@@ -388,7 +388,7 @@ func.func @gpu_gcn_raw_buffer_atomic_fadd_f32(%value: f32, %buf: memref<64xf32>,
// RECORDS45: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %{{.*}}, %[[numRecords]], %[[flags]] : !llvm.ptr, i64 to <8>
// CHECK: %[[old:.*]] = rocdl.raw.ptr.buffer.atomic.fadd %{{.*}}, %[[resource]], %{{.*}}, %{{.*}}, 0 : f32
// CHECK: return %[[old]]
- %old = amdgpu.raw_buffer_atomic_fadd {boundsCheck = true} %value -> %buf[%idx] : f32 -> memref<64xf32>, i32
+ %old = amdgpu.raw_buffer_atomic_fadd boundsCheck(true) %value -> %buf[%idx] : f32 -> memref<64xf32>, i32
func.return %old : f32
}
@@ -403,7 +403,7 @@ func.func @gpu_gcn_raw_buffer_atomic_fadd_v2f16(%value: vector<2xf16>, %buf: mem
// RECORDS45: %[[resource:.*]] = rocdl.make.buffer.rsrc %{{.*}}, %{{.*}}, %[[numRecords]], %[[flags]] : !llvm.ptr, i64 to <8>
// CHECK: %[[old:.*]] = rocdl.raw.ptr.buffer.atomic.fadd %{{.*}}, %[[resource]], %{{.*}}, %{{.*}}, 0 : vector<2xf16>
// CHECK: return %[[old]]
- %old = amdgpu.raw_buffer_atomic_fadd {boundsCheck = true} %value -> %buf[%idx] : vector<2xf16> -> memref<64xf16>, i32
+ %ol...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/216812
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