[llvm-branch-commits] [llvm] [RISCV] Port Opt W Instrs to NewPM (PR #215673)
Sam Elliott via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Aug 11 19:56:59 PDT 2026
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/215673
>From 83abe65070ded78b7beea9c64ac4e1fa93e9126c Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Fri, 7 Aug 2026 17:02:37 -0700
Subject: [PATCH] [RISCV] Port Opt W Instrs to NewPM
Assisted-by: AI
---
llvm/lib/Target/RISCV/RISCV.h | 3 -
.../Target/RISCV/RISCVCodeGenPassBuilder.cpp | 6 +-
llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp | 66 ++++++++++++-------
llvm/lib/Target/RISCV/RISCVOptWInstrs.h | 35 ++++++++++
llvm/lib/Target/RISCV/RISCVPassRegistry.def | 1 +
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 3 +-
llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll | 3 +-
llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll | 3 +-
.../test/CodeGen/RISCV/opt-w-instrs-p-ext.mir | 1 +
llvm/test/CodeGen/RISCV/opt-w-instrs.mir | 1 +
llvm/test/CodeGen/RISCV/prefer-w-inst.mir | 4 ++
.../CodeGen/RISCV/sextw-removal-debug.mir | 1 +
llvm/test/CodeGen/RISCV/zilx-opt-w-instrs.mir | 1 +
13 files changed, 97 insertions(+), 31 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVOptWInstrs.h
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 8532dc20259ba..63a7e0fe96e8b 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -62,9 +62,6 @@ void initializeRISCVLateBranchOptPass(PassRegistry &);
FunctionPass *createRISCVMakeCompressibleOptPass();
void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
-FunctionPass *createRISCVOptWInstrsPass();
-void initializeRISCVOptWInstrsPass(PassRegistry &);
-
FunctionPass *createRISCVMergeBaseOffsetOptPass();
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
index 3a175e34a8e76..10890e5e04206 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
@@ -13,6 +13,7 @@
#include "RISCVAsmPrinter.h"
#include "RISCVFoldMemOffset.h"
#include "RISCVGatherScatterLowering.h"
+#include "RISCVOptWInstrs.h"
#include "RISCVTargetMachine.h"
#include "RISCVVLOptimizer.h"
#include "RISCVVectorPeephole.h"
@@ -118,9 +119,8 @@ void RISCVCodeGenPassBuilder::addMachineSSAOptimization(
Base::addMachineSSAOptimization(PMW);
- if (TM.getTargetTriple().isRISCV64()) {
- // TODO: RISCVOptWInstrsPass
- }
+ if (TM.getTargetTriple().isRISCV64())
+ addMachineFunctionPass(RISCVOptWInstrsPass(), PMW);
}
void RISCVCodeGenPassBuilder::addPreRegAlloc(PassManagerWrapper &PMW) const {
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 0b50bab121abd..335316941b020 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -32,7 +32,7 @@
// * ld/lwu.
//===---------------------------------------------------------------------===//
-#include "RISCV.h"
+#include "RISCVOptWInstrs.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/SmallSet.h"
@@ -60,18 +60,25 @@ static cl::opt<bool> DisableStripWSuffix("riscv-disable-strip-w-suffix",
namespace {
-class RISCVOptWInstrs : public MachineFunctionPass {
+class RISCVOptWInstrsImpl {
public:
- static char ID;
-
- RISCVOptWInstrs() : MachineFunctionPass(ID) {}
+ bool run(MachineFunction &MF);
- bool runOnMachineFunction(MachineFunction &MF) override;
+private:
bool removeSExtWInstrs(MachineFunction &MF, const RISCVInstrInfo &TII,
const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
bool canonicalizeWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,
const RISCVSubtarget &ST,
MachineRegisterInfo &MRI);
+};
+
+class RISCVOptWInstrsLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ RISCVOptWInstrsLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
@@ -83,12 +90,12 @@ class RISCVOptWInstrs : public MachineFunctionPass {
} // end anonymous namespace
-char RISCVOptWInstrs::ID = 0;
-INITIALIZE_PASS(RISCVOptWInstrs, DEBUG_TYPE, RISCV_OPT_W_INSTRS_NAME, false,
- false)
+char RISCVOptWInstrsLegacy::ID = 0;
+INITIALIZE_PASS(RISCVOptWInstrsLegacy, DEBUG_TYPE, RISCV_OPT_W_INSTRS_NAME,
+ false, false)
FunctionPass *llvm::createRISCVOptWInstrsPass() {
- return new RISCVOptWInstrs();
+ return new RISCVOptWInstrsLegacy();
}
static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
@@ -729,10 +736,10 @@ static unsigned getWOp(unsigned Opcode) {
}
}
-bool RISCVOptWInstrs::removeSExtWInstrs(MachineFunction &MF,
- const RISCVInstrInfo &TII,
- const RISCVSubtarget &ST,
- MachineRegisterInfo &MRI) {
+bool RISCVOptWInstrsImpl::removeSExtWInstrs(MachineFunction &MF,
+ const RISCVInstrInfo &TII,
+ const RISCVSubtarget &ST,
+ MachineRegisterInfo &MRI) {
if (DisableSExtWRemoval)
return false;
@@ -783,10 +790,10 @@ bool RISCVOptWInstrs::removeSExtWInstrs(MachineFunction &MF,
// Strips or adds W suffixes to eligible instructions depending on the
// subtarget preferences.
-bool RISCVOptWInstrs::canonicalizeWSuffixes(MachineFunction &MF,
- const RISCVInstrInfo &TII,
- const RISCVSubtarget &ST,
- MachineRegisterInfo &MRI) {
+bool RISCVOptWInstrsImpl::canonicalizeWSuffixes(MachineFunction &MF,
+ const RISCVInstrInfo &TII,
+ const RISCVSubtarget &ST,
+ MachineRegisterInfo &MRI) {
bool ShouldStripW = !(DisableStripWSuffix || ST.preferWInst());
bool ShouldPreferW = ST.preferWInst();
bool MadeChange = false;
@@ -877,10 +884,7 @@ bool RISCVOptWInstrs::canonicalizeWSuffixes(MachineFunction &MF,
return MadeChange;
}
-bool RISCVOptWInstrs::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
- return false;
-
+bool RISCVOptWInstrsImpl::run(MachineFunction &MF) {
MachineRegisterInfo &MRI = MF.getRegInfo();
const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
const RISCVInstrInfo &TII = *ST.getInstrInfo();
@@ -893,3 +897,21 @@ bool RISCVOptWInstrs::runOnMachineFunction(MachineFunction &MF) {
MadeChange |= canonicalizeWSuffixes(MF, TII, ST, MRI);
return MadeChange;
}
+
+bool RISCVOptWInstrsLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+ return RISCVOptWInstrsImpl().run(MF);
+}
+
+PreservedAnalyses
+RISCVOptWInstrsPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ bool Changed = RISCVOptWInstrsImpl().run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.h b/llvm/lib/Target/RISCV/RISCVOptWInstrs.h
new file mode 100644
index 0000000000000..2919be7196705
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.h
@@ -0,0 +1,35 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file declares the RISC-V W-instruction optimization passes.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_RISCV_RISCVOPTWINSTRS_H
+#define LLVM_LIB_TARGET_RISCV_RISCVOPTWINSTRS_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class FunctionPass;
+class PassRegistry;
+
+class RISCVOptWInstrsPass : public OptionalPassInfoMixin<RISCVOptWInstrsPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
+FunctionPass *createRISCVOptWInstrsPass();
+void initializeRISCVOptWInstrsLegacyPass(PassRegistry &);
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_RISCV_RISCVOPTWINSTRS_H
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index 9ec06e23196ec..1273277364027 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -27,6 +27,7 @@ FUNCTION_PASS("riscv-zacas-abi-fix", RISCVZacasABIFixPass(this))
#endif
MACHINE_FUNCTION_PASS("riscv-fold-mem-offset", RISCVFoldMemOffsetPass())
MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
+MACHINE_FUNCTION_PASS("riscv-opt-w-instrs", RISCVOptWInstrsPass())
MACHINE_FUNCTION_PASS("riscv-vector-peephole", RISCVVectorPeepholePass())
MACHINE_FUNCTION_PASS("riscv-vl-optimizer", RISCVVLOptimizerPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index f2d5193593041..5e633fae1ff8a 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -17,6 +17,7 @@
#include "RISCVGatherScatterLowering.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVMachineScheduler.h"
+#include "RISCVOptWInstrs.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "RISCVVLOptimizer.h"
@@ -136,7 +137,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVZacasABIFixLegacyPass(*PR);
initializeRISCVPostRAExpandPseudoPass(*PR);
initializeRISCVMergeBaseOffsetOptPass(*PR);
- initializeRISCVOptWInstrsPass(*PR);
+ initializeRISCVOptWInstrsLegacyPass(*PR);
initializeRISCVFoldMemOffsetLegacyPass(*PR);
initializeRISCVPreRAExpandPseudoPass(*PR);
initializeRISCVExpandPseudoPass(*PR);
diff --git a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
index b26d706a029c9..6d950711f443d 100644
--- a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
@@ -1,7 +1,7 @@
; RUN: llc -enable-new-pm -mtriple=riscv32 -O1 -print-pipeline-passes=tree < %s 2>&1 \
; RUN: | FileCheck %s
; RUN: llc -enable-new-pm -mtriple=riscv64 -O1 -print-pipeline-passes=tree < %s 2>&1 \
-; RUN: | FileCheck %s
+; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
; CHECK: require<MachineModuleAnalysis>
; CHECK-NEXT: require<profile-summary>
@@ -59,6 +59,7 @@
; CHECK-NEXT: machine-sink
; CHECK-NEXT: peephole-opt
; CHECK-NEXT: dead-mi-elimination
+; RV64-NEXT: riscv-opt-w-instrs
; CHECK-NEXT: detect-dead-lanes
; CHECK-NEXT: init-undef
; CHECK-NEXT: process-imp-defs
diff --git a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
index 8354edaefc3c5..696c2874e4075 100644
--- a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
@@ -1,7 +1,7 @@
; RUN: llc -enable-new-pm -mtriple=riscv32 -O3 -print-pipeline-passes=tree < %s 2>&1 \
; RUN: | FileCheck %s
; RUN: llc -enable-new-pm -mtriple=riscv64 -O3 -print-pipeline-passes=tree < %s 2>&1 \
-; RUN: | FileCheck %s
+; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
; CHECK: require<MachineModuleAnalysis>
; CHECK-NEXT: require<profile-summary>
@@ -59,6 +59,7 @@
; CHECK-NEXT: machine-sink
; CHECK-NEXT: peephole-opt
; CHECK-NEXT: dead-mi-elimination
+; RV64-NEXT: riscv-opt-w-instrs
; CHECK-NEXT: detect-dead-lanes
; CHECK-NEXT: init-undef
; CHECK-NEXT: process-imp-defs
diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir
index 55545fab298d8..4253494456854 100644
--- a/llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs -passes=riscv-opt-w-instrs %s -o - | FileCheck %s
---
name: merge_sextw_removed
diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
index 7aef3cb662fe7..879c7b5317eaa 100644
--- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa,+v,+xtheadmempair' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa,+v,+xtheadmempair' -verify-machineinstrs -passes=riscv-opt-w-instrs %s -o - | FileCheck %s
---
name: fcvtmod_w_d
diff --git a/llvm/test/CodeGen/RISCV/prefer-w-inst.mir b/llvm/test/CodeGen/RISCV/prefer-w-inst.mir
index f534567c1f12e..4dc479f5d9075 100644
--- a/llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+++ b/llvm/test/CodeGen/RISCV/prefer-w-inst.mir
@@ -1,8 +1,12 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs -verify-machineinstrs \
# RUN: -mattr=+m -o - | FileCheck %s -check-prefixes=NO-PREFER-W-INST
+# RUN: llc %s -mtriple=riscv64 -passes=riscv-opt-w-instrs -verify-machineinstrs \
+# RUN: -mattr=+m -o - | FileCheck %s -check-prefixes=NO-PREFER-W-INST
# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs -verify-machineinstrs \
# RUN: -mattr=+m,+prefer-w-inst -o - | FileCheck %s -check-prefixes=PREFER-W-INST
+# RUN: llc %s -mtriple=riscv64 -passes=riscv-opt-w-instrs -verify-machineinstrs \
+# RUN: -mattr=+m,+prefer-w-inst -o - | FileCheck %s -check-prefixes=PREFER-W-INST
---
name: addi
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir b/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
index f247c5f38037b..2aae5f0a8348e 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
+++ b/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs -o - | FileCheck %s
+# RUN: llc %s -mtriple=riscv64 -passes=riscv-opt-w-instrs -o - | FileCheck %s
--- |
define void @foo(i32 signext %a, i32 signext %b, ptr %c) !dbg !5 {
diff --git a/llvm/test/CodeGen/RISCV/zilx-opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/zilx-opt-w-instrs.mir
index b620a5371d74d..32636d964d392 100644
--- a/llvm/test/CodeGen/RISCV/zilx-opt-w-instrs.mir
+++ b/llvm/test/CodeGen/RISCV/zilx-opt-w-instrs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr=+experimental-zilx -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+experimental-zilx -verify-machineinstrs -passes=riscv-opt-w-instrs %s -o - | FileCheck %s
# The Zilx doubleword/unsigned-word indexed loads participate in the W-suffix
# canonicalization the same way LD/LWU do: LXD and LXWU can be narrowed to LXW
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