[llvm-branch-commits] [llvm] [RISCV] Port Vector Peephole to NewPM (PR #215671)
Sam Elliott via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Aug 11 14:47:48 PDT 2026
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/215671
>From 64b2924e4a9372fb596986cb062adf2054673462 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Fri, 7 Aug 2026 16:43:46 -0700
Subject: [PATCH] [RISCV] Port Vector Peephole to NewPM
Assisted-by: AI
---
llvm/lib/Target/RISCV/RISCV.h | 3 -
.../Target/RISCV/RISCVCodeGenPassBuilder.cpp | 3 +-
llvm/lib/Target/RISCV/RISCVPassRegistry.def | 1 +
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 3 +-
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 110 +++++++++++-------
llvm/lib/Target/RISCV/RISCVVectorPeephole.h | 39 +++++++
llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll | 1 +
llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll | 1 +
.../RISCV/rvv/allone-masked-to-unmasked.mir | 1 +
.../RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir | 2 +
.../test/CodeGen/RISCV/rvv/vlmax-peephole.mir | 1 +
.../CodeGen/RISCV/rvv/vmerge-peephole.mir | 1 +
.../CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 2 +
13 files changed, 119 insertions(+), 49 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVVectorPeephole.h
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 990531c7e6163..34693c0a5f30f 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -63,9 +63,6 @@ void initializeRISCVLateBranchOptPass(PassRegistry &);
FunctionPass *createRISCVMakeCompressibleOptPass();
void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
-FunctionPass *createRISCVVectorPeepholePass();
-void initializeRISCVVectorPeepholePass(PassRegistry &);
-
FunctionPass *createRISCVOptWInstrsPass();
void initializeRISCVOptWInstrsPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
index 4398814b8826b..68fbeb886b04f 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
@@ -14,6 +14,7 @@
#include "RISCVGatherScatterLowering.h"
#include "RISCVTargetMachine.h"
#include "RISCVVLOptimizer.h"
+#include "RISCVVectorPeephole.h"
#include "llvm/CodeGen/AtomicExpand.h"
#include "llvm/CodeGen/BranchRelaxation.h"
#include "llvm/CodeGen/InterleavedAccess.h"
@@ -111,7 +112,7 @@ void RISCVCodeGenPassBuilder::addMachineSSAOptimization(
addMachineFunctionPass(RISCVVLOptimizerPass(), PMW);
}
- // TODO: RISCVVectorPeepholePass
+ addMachineFunctionPass(RISCVVectorPeepholePass(), PMW);
// TODO: RISCVFoldMemOffsetPass
Base::addMachineSSAOptimization(PMW);
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index e64d84832aada..d112ba5505cce 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -26,5 +26,6 @@ FUNCTION_PASS("riscv-zacas-abi-fix", RISCVZacasABIFixPass(this))
#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
#endif
MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
+MACHINE_FUNCTION_PASS("riscv-vector-peephole", RISCVVectorPeepholePass())
MACHINE_FUNCTION_PASS("riscv-vl-optimizer", RISCVVLOptimizerPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 101917c7435ad..f6f8cc4fcf08d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -19,6 +19,7 @@
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "RISCVVLOptimizer.h"
+#include "RISCVVectorPeephole.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
@@ -138,7 +139,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVFoldMemOffsetPass(*PR);
initializeRISCVPreRAExpandPseudoPass(*PR);
initializeRISCVExpandPseudoPass(*PR);
- initializeRISCVVectorPeepholePass(*PR);
+ initializeRISCVVectorPeepholeLegacyPass(*PR);
initializeRISCVVLOptimizerLegacyPass(*PR);
initializeRISCVVMV0EliminationPass(*PR);
initializeRISCVInsertVSETVLIPass(*PR);
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 2f1b3c409ff2b..a274576065ba4 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -27,7 +27,7 @@
//
//===----------------------------------------------------------------------===//
-#include "RISCV.h"
+#include "RISCVVectorPeephole.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -41,31 +41,15 @@ using namespace llvm;
namespace {
-class RISCVVectorPeephole : public MachineFunctionPass {
+class RISCVVectorPeepholeImpl {
public:
- static char ID;
+ bool run(MachineFunction &MF);
+
+private:
const TargetInstrInfo *TII;
MachineRegisterInfo *MRI;
const TargetRegisterInfo *TRI;
const RISCVSubtarget *ST;
- RISCVVectorPeephole() : MachineFunctionPass(ID) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().setIsSSA();
- }
-
- StringRef getPassName() const override {
- return "RISC-V Vector Peephole Optimization";
- }
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesCFG();
- AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
-
-private:
bool convertToVLMAX(MachineInstr &MI) const;
bool convertToWholeRegister(MachineInstr &MI) const;
bool convertToUnmasked(MachineInstr &MI) const;
@@ -85,17 +69,39 @@ class RISCVVectorPeephole : public MachineFunctionPass {
SmallVectorImpl<MachineInstr *> *Copies = nullptr) const;
};
+class RISCVVectorPeepholeLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ RISCVVectorPeepholeLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().setIsSSA();
+ }
+
+ StringRef getPassName() const override {
+ return "RISC-V Vector Peephole Optimization";
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+};
+
} // namespace
-char RISCVVectorPeephole::ID = 0;
+char RISCVVectorPeepholeLegacy::ID = 0;
-INITIALIZE_PASS(RISCVVectorPeephole, DEBUG_TYPE, "RISC-V Fold Masks", false,
- false)
+INITIALIZE_PASS(RISCVVectorPeepholeLegacy, DEBUG_TYPE, "RISC-V Fold Masks",
+ false, false)
/// Given \p User that has an input operand with EEW=SEW, which uses the dest
/// operand of \p Src with an unknown EEW, return true if their EEWs match.
-bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
- const MachineInstr &Src) const {
+bool RISCVVectorPeepholeImpl::hasSameEEW(const MachineInstr &User,
+ const MachineInstr &Src) const {
unsigned UserLog2SEW =
User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm();
unsigned SrcLog2SEW =
@@ -107,7 +113,7 @@ bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
/// Check if an operand is an immediate or a materialized ADDI $x0, imm.
std::optional<unsigned>
-RISCVVectorPeephole::getConstant(const MachineOperand &VL) const {
+RISCVVectorPeepholeImpl::getConstant(const MachineOperand &VL) const {
if (VL.isImm())
return VL.getImm();
@@ -119,7 +125,7 @@ RISCVVectorPeephole::getConstant(const MachineOperand &VL) const {
}
/// Convert AVLs that are known to be VLMAX to the VLMAX sentinel.
-bool RISCVVectorPeephole::convertToVLMAX(MachineInstr &MI) const {
+bool RISCVVectorPeepholeImpl::convertToVLMAX(MachineInstr &MI) const {
if (!RISCVII::hasVLOp(MI.getDesc().TSFlags) ||
!RISCVII::hasSEWOp(MI.getDesc().TSFlags))
return false;
@@ -180,7 +186,7 @@ bool RISCVVectorPeephole::convertToVLMAX(MachineInstr &MI) const {
return true;
}
-bool RISCVVectorPeephole::isAllOnesMask(const MachineInstr *MaskDef) const {
+bool RISCVVectorPeepholeImpl::isAllOnesMask(const MachineInstr *MaskDef) const {
while (MaskDef->isCopy() && MaskDef->getOperand(1).getReg().isVirtual())
MaskDef = MRI->getVRegDef(MaskDef->getOperand(1).getReg());
@@ -211,7 +217,7 @@ bool RISCVVectorPeephole::isAllOnesMask(const MachineInstr *MaskDef) const {
///
/// %x = VL1RE8_V %ptr
/// VS1R_V %v, %ptr
-bool RISCVVectorPeephole::convertToWholeRegister(MachineInstr &MI) const {
+bool RISCVVectorPeepholeImpl::convertToWholeRegister(MachineInstr &MI) const {
#define CASE_WHOLE_REGISTER_LMUL_SEW(lmul, sew) \
case RISCV::PseudoVLE##sew##_V_M##lmul: \
NewOpc = RISCV::VL##lmul##RE##sew##_V; \
@@ -275,7 +281,8 @@ static unsigned getVMV_V_VOpcodeForVMERGE_VVM(const MachineInstr &MI) {
/// %x = PseudoVMERGE_VVM %passthru, %false, %true, %allones, sew, vl
/// ->
/// %x = PseudoVMV_V_V %passthru, %true, vl, sew, tu_mu
-bool RISCVVectorPeephole::convertAllOnesVMergeToVMv(MachineInstr &MI) const {
+bool RISCVVectorPeepholeImpl::convertAllOnesVMergeToVMv(
+ MachineInstr &MI) const {
unsigned NewOpc = getVMV_V_VOpcodeForVMERGE_VVM(MI);
if (!NewOpc)
return false;
@@ -298,7 +305,7 @@ bool RISCVVectorPeephole::convertAllOnesVMergeToVMv(MachineInstr &MI) const {
// If \p Reg is defined by one or more COPYs of virtual registers, traverses
// the chain and returns the root non-COPY source.
-Register RISCVVectorPeephole::lookThruCopies(
+Register RISCVVectorPeepholeImpl::lookThruCopies(
Register Reg, bool OneUseOnly,
SmallVectorImpl<MachineInstr *> *Copies) const {
while (MachineInstr *Def = MRI->getUniqueVRegDef(Reg)) {
@@ -325,7 +332,7 @@ Register RISCVVectorPeephole::lookThruCopies(
/// ->
/// %true = PseudoVADD_VV_M1_MASK %false, %x, %y, %mask, vl1, sew, policy
/// %x = PseudoVMV_V_V %passthru, %true, vl2, sew, tu_mu
-bool RISCVVectorPeephole::convertSameMaskVMergeToVMv(MachineInstr &MI) {
+bool RISCVVectorPeepholeImpl::convertSameMaskVMergeToVMv(MachineInstr &MI) {
unsigned NewOpc = getVMV_V_VOpcodeForVMERGE_VVM(MI);
if (!NewOpc)
return false;
@@ -400,7 +407,7 @@ bool RISCVVectorPeephole::convertSameMaskVMergeToVMv(MachineInstr &MI) {
return true;
}
-bool RISCVVectorPeephole::convertToUnmasked(MachineInstr &MI) const {
+bool RISCVVectorPeepholeImpl::convertToUnmasked(MachineInstr &MI) const {
const RISCV::RISCVMaskedPseudoInfo *I =
RISCV::getMaskedPseudoInfo(MI.getOpcode());
if (!I)
@@ -475,8 +482,8 @@ static bool strictlyDominates(MachineBasicBlock::const_iterator A,
/// If a register in \p Defs doesn't dominate \p Use, try to move Use so it
/// does. Returns false if any def doesn't dominate and we can't move Use. Each
/// def must be in the same block as Use.
-bool RISCVVectorPeephole::ensureDominates(ArrayRef<const MachineOperand *> Defs,
- MachineInstr &Use) const {
+bool RISCVVectorPeepholeImpl::ensureDominates(
+ ArrayRef<const MachineOperand *> Defs, MachineInstr &Use) const {
MachineInstr *Dest = &Use;
for (const MachineOperand *MO : Defs) {
@@ -500,7 +507,7 @@ bool RISCVVectorPeephole::ensureDominates(ArrayRef<const MachineOperand *> Defs,
}
/// If a PseudoVMV_V_V's passthru is undef then we can replace it with its input
-bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
+bool RISCVVectorPeepholeImpl::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
if (RISCV::getRVVMCOpcode(MI.getOpcode()) != RISCV::VMV_V_V)
return false;
if (MI.getOperand(1).getReg().isValid())
@@ -542,7 +549,7 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
/// ->
///
/// %y = PseudoVADD_V_V_M1 %passthru, %a, %b, vl1, sew, policy
-bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
+bool RISCVVectorPeepholeImpl::foldVMV_V_V(MachineInstr &MI) {
if (RISCV::getRVVMCOpcode(MI.getOpcode()) != RISCV::VMV_V_V)
return false;
@@ -642,7 +649,7 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
///
/// The resulting policy is the effective policy the vmerge would have had,
/// i.e. whether or not it's passthru operand was implicit-def.
-bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
+bool RISCVVectorPeepholeImpl::foldVMergeToMask(MachineInstr &MI) const {
if (RISCV::getRVVMCOpcode(MI.getOpcode()) != RISCV::VMERGE_VVM)
return false;
@@ -787,10 +794,7 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
return true;
}
-bool RISCVVectorPeephole::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
- return false;
-
+bool RISCVVectorPeepholeImpl::run(MachineFunction &MF) {
// Skip if the vector extension is not enabled.
ST = &MF.getSubtarget<RISCVSubtarget>();
if (!ST->hasVInstructions())
@@ -823,6 +827,24 @@ bool RISCVVectorPeephole::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
+bool RISCVVectorPeepholeLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+ return RISCVVectorPeepholeImpl().run(MF);
+}
+
+PreservedAnalyses
+RISCVVectorPeepholePass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ bool Changed = RISCVVectorPeepholeImpl().run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
+
FunctionPass *llvm::createRISCVVectorPeepholePass() {
- return new RISCVVectorPeephole();
+ return new RISCVVectorPeepholeLegacy();
}
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.h b/llvm/lib/Target/RISCV/RISCVVectorPeephole.h
new file mode 100644
index 0000000000000..6b61b66dd6a14
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.h
@@ -0,0 +1,39 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file declares the RISC-V vector peephole passes.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_RISCV_RISCVVECTORPEEPHOLE_H
+#define LLVM_LIB_TARGET_RISCV_RISCVVECTORPEEPHOLE_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class FunctionPass;
+class PassRegistry;
+
+class RISCVVectorPeepholePass
+ : public OptionalPassInfoMixin<RISCVVectorPeepholePass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().setIsSSA();
+ }
+};
+
+FunctionPass *createRISCVVectorPeepholePass();
+void initializeRISCVVectorPeepholeLegacyPass(PassRegistry &);
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_RISCV_RISCVVECTORPEEPHOLE_H
diff --git a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
index 28778276eea09..547ed7f9169b6 100644
--- a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
@@ -47,6 +47,7 @@
; CHECK-NEXT: finalize-isel
; CHECK-NEXT: early-machinelicm
; CHECK-NEXT: riscv-vl-optimizer
+; CHECK-NEXT: riscv-vector-peephole
; CHECK-NEXT: early-tailduplication
; CHECK-NEXT: opt-phis
; CHECK-NEXT: stack-coloring
diff --git a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
index 7af9a28c0aa35..81c4afa7e388c 100644
--- a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
@@ -47,6 +47,7 @@
; CHECK-NEXT: finalize-isel
; CHECK-NEXT: early-machinelicm
; CHECK-NEXT: riscv-vl-optimizer
+; CHECK-NEXT: riscv-vector-peephole
; CHECK-NEXT: early-tailduplication
; CHECK-NEXT: opt-phis
; CHECK-NEXT: stack-coloring
diff --git a/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir b/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir
index 408d533f77074..1c1490640e745 100644
--- a/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole -verify-machineinstrs | FileCheck %s
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -passes=riscv-vector-peephole -verify-machineinstrs | FileCheck %s
# Take into account that the masked vcpop pseudo doesn't have a passthru
---
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
index b74aad5e494b0..269d91a2e5148 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
# RUN: -verify-machineinstrs | FileCheck %s
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -passes=riscv-vector-peephole \
+# RUN: -verify-machineinstrs | FileCheck %s
---
name: undef_passthru
diff --git a/llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir
index d2c34b502941d..f20728b096f0d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole -verify-machineinstrs | FileCheck %s
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -passes=riscv-vector-peephole -verify-machineinstrs | FileCheck %s
# The AVL is defined by an ADDI whose second operand is a frame index rather than
# a register.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
index c06e0b5ee81be..0c6595ed40caa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole -verify-machineinstrs | FileCheck %s
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -passes=riscv-vector-peephole -verify-machineinstrs | FileCheck %s
---
name: vle32
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index 50c87eda56092..6b7a02c83649b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
# RUN: -verify-machineinstrs | FileCheck %s
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -passes=riscv-vector-peephole \
+# RUN: -verify-machineinstrs | FileCheck %s
---
name: move_src
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