[llvm-branch-commits] [llvm] [RISCV] Support i64 accumulator for Zvdot4a8i partial reductions (PR #215517)

[Pengcheng Wang via llvm-branch-commits]

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/215517

>From e252d0cbeb0a1a3ee8c7e03052d1e37035f70d4a Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Tue, 11 Aug 2026 18:58:52 +0800
Subject: [PATCH] Format test

Created using spr 1.3.6-beta.1
---
 .../RISCV/partial-reduce-dot-product-i64.ll            | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product-i64.ll b/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product-i64.ll
index 459c896357809..a1e6d460d32c6 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product-i64.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product-i64.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph:" --version 4
-; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvdot4a8i -riscv-v-register-bit-width-lmul=8 -tail-folding-policy=dont-fold-tail -S < %s | FileCheck %s --check-prefix=NOTAILFOLD
-; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvdot4a8i -riscv-v-register-bit-width-lmul=8 -S < %s | FileCheck %s --check-prefix=TAILFOLD
+; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvdot4a8i -riscv-v-register-bit-width-lmul=8 -tail-folding-policy=dont-fold-tail -S < %s \
+; RUN:   | FileCheck %s --check-prefix=NOTAILFOLD
+; RUN: opt -passes=loop-vectorize -mattr=+v,+experimental-zvdot4a8i -riscv-v-register-bit-width-lmul=8 -S < %s \
+; RUN:   | FileCheck %s --check-prefix=TAILFOLD
 
 ; Dot product with an i64 accumulator and i8 inputs. This forms a scale-8
 ; partial reduction (i8 -> i64), which the RISC-V backend lowers using vdot4a*
@@ -11,7 +13,7 @@
 
 target triple = "riscv64-none-unknown-elf"
 
-define i64 @vqdot_i64(ptr %a, ptr %b) #0 {
+define i64 @vqdot_i64(ptr %a, ptr %b) {
 ; NOTAILFOLD-LABEL: define i64 @vqdot_i64(
 ; NOTAILFOLD-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
 ; NOTAILFOLD-NEXT:  entry:
@@ -102,5 +104,3 @@ for.body:
 for.exit:
   ret i64 %add
 }
-
-attributes #0 = { "target-features"="+v,+experimental-zvdot4a8i" }